When doing a 64-bit to a smaller data type size conversion, the destination should be aligned to 64-bits. Because of that, we need to gather the data after the actual conversion.
Until now, these two operations were done by VEC4_OPCODE_FROM_DOUBLE but now we split them explicitely in two different instructions: VEC4_OPCODE_FROM_DOUBLE just do the conversion and VEC4_OPCODE_PICK_LOW_32BIT will gather the data. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/compiler/brw_vec4_generator.cpp | 8 -------- src/intel/compiler/brw_vec4_nir.cpp | 1 + 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index 34bcd32c958..d0fd694901f 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1965,14 +1965,6 @@ generate_code(struct brw_codegen *p, src[0].width = BRW_WIDTH_4; brw_MOV(p, spread_dst, src[0]); - /* As we have set horizontal stride 1 instead of 2 in IVB/BYT, we - * need to fix it here to have the expected value. - */ - if (devinfo->gen == 7 && !devinfo->is_haswell) - spread_dst = stride(dst, 8, 4, 2); - - brw_MOV(p, dst, spread_dst); - brw_set_default_access_mode(p, BRW_ALIGN_16); break; } diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 23842653997..45d2c9f4a93 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1191,6 +1191,7 @@ vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src, emit(VEC4_OPCODE_FROM_DOUBLE, temp2, src_reg(temp)) ->size_written = 2 * REG_SIZE; + emit(VEC4_OPCODE_PICK_LOW_32BIT, temp2, src_reg(retype(temp2, BRW_REGISTER_TYPE_DF))); vec4_instruction *inst = emit(MOV(dst, src_reg(temp2))); inst->saturate = saturate; } -- 2.11.0 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev