On Thu, Feb 13, 2014 at 07:56:26AM -0800, Matt Arsenault wrote:
On Feb 7, 2014, at 7:46 AM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
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lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 48
++
On Feb 7, 2014, at 7:46 AM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
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lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 48 ++
lib/Target/R600/SIISelLowering.cpp | 29
lib/Target/R600/SIISelLowering.h
I didn't think to try this. Where is the address folding happening?
On 02/07/2014 07:46 AM, Tom Stellard wrote:
From: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 48 ++
lib/Target/R600/SIISelLowering.cpp | 29
On Fri, Feb 07, 2014 at 10:31:20AM -0800, Matt Arsenault wrote:
I didn't think to try this. Where is the address folding happening?
There are TableGen patterns that do the folding. I recently added
several new ones: r200932-r200935.
-Tom
On 02/07/2014 07:46 AM, Tom Stellard wrote:
From: