Re: [Mesa-dev] [PATCH 1/2] radeonsi: disable ReZ

[Edward O'Callaghan]

Why not just squash these two patches together? Either way this series
is, Acked-by: Edward O'Callaghan 

On 10/13/2016 10:22 AM, Andy Furniss wrote:
> Marek Olšák wrote:
>> From: Marek Olšák 
>>
>> This is a serious performance fix. Discovered by luck.
> 
> Hmm, maybe I should bump my bugs more aggressively :-)
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=94354

For a decent enough bug report like that, yes if its stalled poke and
ask why on IRC.

> 
>>
>> Cc: 12.0 
>> ---
>>   src/gallium/drivers/radeonsi/si_state_shaders.c | 11 ---
>>   1 file changed, 4 insertions(+), 7 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
>> b/src/gallium/drivers/radeonsi/si_state_shaders.c
>> index c41c519..be5c659 100644
>> --- a/src/gallium/drivers/radeonsi/si_state_shaders.c
>> +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
>> @@ -801,34 +801,31 @@ static void si_shader_ps(struct si_shader *shader)
>>   si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
>>  S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
>>  S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
>>  S_00B028_DX10_CLAMP(1) |
>>  S_00B028_FLOAT_MODE(shader->config.float_mode));
>>   si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
>>  S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
>>  S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
>> 
>> S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
>>
>> -/* Prefer RE_Z if the shader is complex enough. The requirement
>> is either:
>> - * - the shader uses at least 2 VMEM instructions, or
>> - * - the code size is at least 50 2-dword instructions or 100
>> 1-dword
>> - *   instructions.
>> +/* DON'T USE EARLY_Z_THEN_RE_Z !!!
>> + *
>> + * It decreases performance by 15% in DiRT: Showdown on Ultra
>> settings.
>> + * And it has pretty complex shaders.
>>*
>>* Shaders with side effects that must execute independently of the
>>* depth test require LATE_Z.
>>*/
>>   if (info->writes_memory &&
>>   !info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
>>   shader->z_order = V_02880C_LATE_Z;
>> -else if (info->num_memory_instructions >= 2 ||
>> - shader->binary.code_size > 100*4)
>> -shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
>>   else
>>   shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
>>   }
>>
>>   static void si_shader_init_pm4_state(struct si_screen *sscreen,
>>struct si_shader *shader)
>>   {
>>   switch (shader->selector->type) {
>>   case PIPE_SHADER_VERTEX:
>>   if (shader->key.vs.as_ls)
>>
> 
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Re: [Mesa-dev] [PATCH 1/2] radeonsi: disable ReZ

[Andy Furniss]

Marek Olšák wrote:

From: Marek Olšák 

This is a serious performance fix. Discovered by luck.


Hmm, maybe I should bump my bugs more aggressively :-)

https://bugs.freedesktop.org/show_bug.cgi?id=94354



Cc: 12.0 
---
  src/gallium/drivers/radeonsi/si_state_shaders.c | 11 ---
  1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index c41c519..be5c659 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -801,34 +801,31 @@ static void si_shader_ps(struct si_shader *shader)
si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
   S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
   S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
   S_00B028_DX10_CLAMP(1) |
   S_00B028_FLOAT_MODE(shader->config.float_mode));
si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
   S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
   S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
   S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave 
> 0));

-   /* Prefer RE_Z if the shader is complex enough. The requirement is 
either:
-* - the shader uses at least 2 VMEM instructions, or
-* - the code size is at least 50 2-dword instructions or 100 1-dword
-*   instructions.
+   /* DON'T USE EARLY_Z_THEN_RE_Z !!!
+*
+* It decreases performance by 15% in DiRT: Showdown on Ultra settings.
+* And it has pretty complex shaders.
 *
 * Shaders with side effects that must execute independently of the
 * depth test require LATE_Z.
 */
if (info->writes_memory &&
!info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
shader->z_order = V_02880C_LATE_Z;
-   else if (info->num_memory_instructions >= 2 ||
-shader->binary.code_size > 100*4)
-   shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
else
shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
  }

  static void si_shader_init_pm4_state(struct si_screen *sscreen,
   struct si_shader *shader)
  {
switch (shader->selector->type) {
case PIPE_SHADER_VERTEX:
if (shader->key.vs.as_ls)



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