On Wednesday, October 12, 2016 11:27:59 PM PDT Lionel Landwerlin wrote: > One of the register we happen to program but don't have a description for > yet. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > --- > src/intel/genxml/gen6.xml | 5 +++++ > src/intel/genxml/gen7.xml | 5 +++++ > src/intel/genxml/gen75.xml | 5 +++++ > src/intel/genxml/gen8.xml | 5 +++++ > src/intel/genxml/gen9.xml | 5 +++++ > 5 files changed, 25 insertions(+) > > diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml > index 52d0ecb..8fc02e0 100644 > --- a/src/intel/genxml/gen6.xml > +++ b/src/intel/genxml/gen6.xml > @@ -1968,4 +1968,9 @@ > <field name="System Instruction Pointer" start="36" end="63" > type="offset"/> > </instruction> > > + <register name="SO_WRITE_OFFSET" length="1" num="0x5280"> > + <field name="Write Offset" start="2" end="31" type="uint"/> > + <field name="Reserved" start="0" end="1" type="uint"/> > + </register> > + > </genxml> > diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml > index 44bb2a7..a5a0571 100644 > --- a/src/intel/genxml/gen7.xml > +++ b/src/intel/genxml/gen7.xml > @@ -2521,6 +2521,11 @@ > <field name="SW Tessellation Memory Object Control State" start="40" > end="43" type="MEMORY_OBJECT_CONTROL_STATE"/> > </instruction> > > + <register name="SO_WRITE_OFFSET" length="1" num="0x5280"> > + <field name="Write Offset" start="2" end="31" type="uint"/> > + <field name="Reserved" start="0" end="1" type="uint"/> > + </register>
It looks like this will only handle SO_WRITE_OFFSET0, but not the other three registers? (There's only one on Gen6, but 4 on Gen7+.)
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