Re: [Mesa-dev] [PATCH 3/5] winsys/amdgpu: pad compute rings

[Alex Deucher]

On Thu, Mar 8, 2018 at 11:51 AM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> v2: pad with PKT2 NOPs on SI

Reviewed-by: Alex Deucher 

> ---
>  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index d9a95c0..a3feeb9 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -1521,29 +1521,31 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs 
> *rcs,
>/* pad DMA ring to 8 DWs */
>if (ws->info.chip_class <= SI) {
>   while (rcs->current.cdw & 7)
>  radeon_emit(rcs, 0xf000); /* NOP packet */
>} else {
>   while (rcs->current.cdw & 7)
>  radeon_emit(rcs, 0x); /* NOP packet */
>}
>break;
> case RING_GFX:
> +   case RING_COMPUTE:
>/* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
>if (ws->info.gfx_ib_pad_with_type2) {
>   while (rcs->current.cdw & 7)
>  radeon_emit(rcs, 0x8000); /* type2 nop packet */
>} else {
>   while (rcs->current.cdw & 7)
>  radeon_emit(rcs, 0x1000); /* type3 nop packet */
>}
> -  ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
> +  if (cs->ring_type == RING_GFX)
> + ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
>break;
> case RING_UVD:
> case RING_UVD_ENC:
>while (rcs->current.cdw & 15)
>   radeon_emit(rcs, 0x8000); /* type2 nop packet */
>break;
> case RING_VCN_DEC:
>while (rcs->current.cdw & 15)
>   radeon_emit(rcs, 0x81ff); /* nop packet */
>break;
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 3/5] winsys/amdgpu: pad compute rings

[Christian König]

Am 07.03.2018 um 21:34 schrieb Marek Olšák:

From: Marek Olšák 

---
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index d9a95c0..9cd3343 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1531,20 +1531,24 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
/* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
if (ws->info.gfx_ib_pad_with_type2) {
   while (rcs->current.cdw & 7)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
} else {
   while (rcs->current.cdw & 7)
  radeon_emit(rcs, 0x1000); /* type3 nop packet */
}
ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
break;
+   case RING_COMPUTE:
+  while (rcs->current.cdw & 7)
+ radeon_emit(rcs, 0x1000); /* type3 nop packet */
+  break;


Not 100% sure, but I think we need to handle this like GFX ring as well.

E.g. only pad with 0x1000 when the firmware supports it, otherwise 
we need to use 0x8000.


Christian.


 case RING_UVD:
 case RING_UVD_ENC:
while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x8000); /* type2 nop packet */
break;
 case RING_VCN_DEC:
while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x81ff); /* nop packet */
break;
 default:


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Re: [Mesa-dev] [PATCH 3/5] winsys/amdgpu: pad compute rings

[Alex Deucher]

On Wed, Mar 7, 2018 at 3:34 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index d9a95c0..9cd3343 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -1531,20 +1531,24 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs 
> *rcs,
>/* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
>if (ws->info.gfx_ib_pad_with_type2) {
>   while (rcs->current.cdw & 7)
>  radeon_emit(rcs, 0x8000); /* type2 nop packet */
>} else {
>   while (rcs->current.cdw & 7)
>  radeon_emit(rcs, 0x1000); /* type3 nop packet */
>}
>ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
>break;
> +   case RING_COMPUTE:
> +  while (rcs->current.cdw & 7)
> + radeon_emit(rcs, 0x1000); /* type3 nop packet */
> +  break;

This only works on CIK I think.  SI might still require type2 packets.

Alex

> case RING_UVD:
> case RING_UVD_ENC:
>while (rcs->current.cdw & 15)
>   radeon_emit(rcs, 0x8000); /* type2 nop packet */
>break;
> case RING_VCN_DEC:
>while (rcs->current.cdw & 15)
>   radeon_emit(rcs, 0x81ff); /* nop packet */
>break;
> default:
> --
> 2.7.4
>
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