FWIW I'm not really qualified to review this, but this alleviates the
concerns I had some time ago about doing spilling for r600 before sb.
So this makes all sense to me.
Roland
Am 28.04.2018 um 21:30 schrieb Gert Wollny:
> this is another update of the series I've sent before.
>
> v3:
> -
[...]
>
> $R600_DEBUG=merge ST_DEBUG=tgsi ./run wollny/
>
> ATTENTION: default value of option
> allow_glsl_extension_directive_midshader overridden by environment.
> run: state_tracker/st_glsl_to_tgsi.cpp:5783: ureg_dst
> dst_register(st_translate*, gl_register_file, unsigned int, unsigned
>
Am 29.04.2018 um 21:44 schrieb Gert Wollny:
> Hello Benedict,
>
> thanks for all the testing!
thanks for all the developing ;)
>
> On 29.04.2018 12:12, Benedikt Schemmer wrote:
>>> Which are the names of these test? I'd like to check this on r600,
>>> because here I didn't see any
Hello Benedict,
thanks for all the testing!
On 29.04.2018 12:12, Benedikt Schemmer wrote:
>> Which are the names of these test? I'd like to check this on r600,
>> because here I didn't see any regressions last time I checked.
>>
> might of course be different on r600 (is bindless available?),
>
sorry the last one wasnt correct:
register merge vs yours
Max Increase:
SGPRS: 80 -> 96 (20.00 %) (in
shaders/deusex_mankind/7c39f71090a9db19ac2e1542ea12804ae6c6495b_4864.shader_test)
VGPRS: 64 -> 84 (31.25 %) (in
shaders/dirtrally/0859b69789591d7046e211400b1edd9a7cfca734_742.shader_test)
Real world
(old vs new)
nothing vs register merge:
PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR SpillVGPR PrivVGPR
Scratch CodeSize MaxWaves Waits
0ad6 . . . . .
. . . .
aer
Am 29.04.2018 um 11:34 schrieb Gert Wollny:
> Am Sonntag, den 29.04.2018, 10:43 +0200 schrieb Benedikt Schemmer:
>> Hi Gert,
>>
>> couldn't resist at least to try what would happen if I enable
>> register merge for radeonsi:
>>
>> PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR
>>
Am Sonntag, den 29.04.2018, 10:43 +0200 schrieb Benedikt Schemmer:
> Hi Gert,
>
> couldn't resist at least to try what would happen if I enable
> register merge for radeonsi:
>
> PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR
> SpillVGPR PrivVGPR Scratch CodeSize MaxWaves
Hi Gert,
couldn't resist at least to try what would happen if I enable register merge
for radeonsi:
PERCENTAGE DELTASShaders SGPRs VGPRs SpillSGPR SpillVGPR PrivVGPR
Scratch CodeSize MaxWaves Waits
piglit 80732 -0.16 % -0.02 % . .
Hello Benedikt,
Am Sonntag, den 29.04.2018, 00:06 +0200 schrieb Benedikt Schemmer:
> Hi Gert
>
> Am 28.04.2018 um 23:51 schrieb Gert Wollny:
> > Am Samstag, den 28.04.2018, 22:43 +0200 schrieb Benedikt Schemmer:
> > > The patches apply cleanly, however I just did a shader-db test
> > > run
> >
Hi Gert
Am 28.04.2018 um 23:51 schrieb Gert Wollny:
> Am Samstag, den 28.04.2018, 22:43 +0200 schrieb Benedikt Schemmer:
>> The patches apply cleanly, however I just did a shader-db test run
>> and can't find a difference with your patch
>> applied, am I doing something wrong?
>
> AFAIK radeonsi
Am Samstag, den 28.04.2018, 22:43 +0200 schrieb Benedikt Schemmer:
> The patches apply cleanly, however I just did a shader-db test run
> and can't find a difference with your patch
> applied, am I doing something wrong?
AFAIK radeonsi doesn't use the register-merge optimizer in TGSI.
>
>
The patches apply cleanly, however I just did a shader-db test run and can't
find a difference with your patch
applied, am I doing something wrong?
compile times went up though:
before:
Thread 3 took 113.72 seconds and compiled 17899 shaders (not including SIMD16)
with 2232 GL context switches
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