Re: [Mesa-dev] [PATCH v3 4/9] i965: Add and use a single miptree aux_buf field

[Nanley Chery]

On Mon, Apr 23, 2018 at 11:10:08AM -0700, Jason Ekstrand wrote:
> On Wed, Apr 11, 2018 at 1:42 PM, Nanley Chery  wrote:
> 
> > We want to add and use a function that accesses the auxiliary buffer's
> > clear_color_bo and doesn't care if it has an MCS or HiZ buffer
> > specifically.
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
> >  src/mesa/drivers/dri/i965/brw_clear.c |   4 +-
> >  src/mesa/drivers/dri/i965/brw_wm.c|   2 +-
> >  src/mesa/drivers/dri/i965/gen6_depth_state.c  |   6 +-
> >  src/mesa/drivers/dri/i965/gen7_misc_state.c   |   4 +-
> >  src/mesa/drivers/dri/i965/gen8_depth_state.c  |   6 +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 106
> > +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  42 --
> >  src/mesa/drivers/dri/i965/intel_tex_image.c   |   2 +-
> >  9 files changed, 80 insertions(+), 96 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> > b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 962a316c5cf..a1882abb7cb 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -1212,7 +1212,7 @@ do_single_blorp_clear(struct brw_context *brw,
> > struct gl_framebuffer *fb,
> >
> > /* If the MCS buffer hasn't been allocated yet, we need to allocate it
> > now.
> >  */
> > -   if (can_fast_clear && !irb->mt->mcs_buf) {
> > +   if (can_fast_clear && !irb->mt->aux_buf) {
> >assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
> >if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
> >   /* There are a few reasons in addition to out-of-memory, that can
> > @@ -1611,7 +1611,7 @@ intel_hiz_exec(struct brw_context *brw, struct
> > intel_mipmap_tree *mt,
> > brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
> > }
> >
> > -   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
> > +   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
> >
> > struct isl_surf isl_tmp[2];
> > struct blorp_surf surf;
> > diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
> > b/src/mesa/drivers/dri/i965/brw_clear.c
> > index 487de9b8997..3d540d6d905 100644
> > --- a/src/mesa/drivers/dri/i965/brw_clear.c
> > +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> > @@ -240,7 +240,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
> >* buffer when doing a fast clear. Since we are skipping the fast
> >* clear here, we need to update the clear color ourselves.
> >*/
> > - uint32_t clear_offset = mt->hiz_buf->clear_color_offset;
> > + uint32_t clear_offset = mt->aux_buf->clear_color_offset;
> >   union isl_color_value clear_color = { .f32 = { clear_value, } };
> >
> >   /* We can't update the clear color while the hardware is still
> > using
> > @@ -249,7 +249,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
> >*/
> >   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
> >   for (int i = 0; i < 4; i++) {
> > -brw_store_data_imm32(brw, mt->hiz_buf->clear_color_bo,
> > +brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
> >   clear_offset + i * 4,
> > clear_color.u32[i]);
> >   }
> >   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_
> > INVALIDATE);
> > diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
> > b/src/mesa/drivers/dri/i965/brw_wm.c
> > index 68d4ab88d77..94048cd758f 100644
> > --- a/src/mesa/drivers/dri/i965/brw_wm.c
> > +++ b/src/mesa/drivers/dri/i965/brw_wm.c
> > @@ -384,7 +384,7 @@ brw_populate_sampler_prog_key_data(struct gl_context
> > *ctx,
> >   if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
> >  assert(devinfo->gen >= 7);
> >  assert(intel_tex->mt->surf.samples > 1);
> > -assert(intel_tex->mt->mcs_buf);
> > +assert(intel_tex->mt->aux_buf);
> >  assert(intel_tex->mt->surf.msaa_layout ==
> > ISL_MSAA_LAYOUT_ARRAY);
> >  key->compressed_multisample_layout_mask |= 1 << s;
> >
> > diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > index 3a66b42fec1..8a1d5808051 100644
> > --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > @@ -160,13 +160,13 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
> >   assert(depth_mt);
> >
> >   uint32_t offset;
> > - isl_surf_get_image_offset_B_tile_sa(_mt->hiz_buf->surf,
> > + isl_surf_get_image_offset_B_tile_sa(_mt->aux_buf->surf,
> >   lod, 0, 0, , NULL,
> > NULL);
> >
> >  BEGIN_BATCH(3);
> >  OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
> > -OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
> > -OUT_RELOC(depth_mt->hiz_buf->bo, 

Re: [Mesa-dev] [PATCH v3 4/9] i965: Add and use a single miptree aux_buf field

[Jason Ekstrand]

On Wed, Apr 11, 2018 at 1:42 PM, Nanley Chery  wrote:

> We want to add and use a function that accesses the auxiliary buffer's
> clear_color_bo and doesn't care if it has an MCS or HiZ buffer
> specifically.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
>  src/mesa/drivers/dri/i965/brw_clear.c |   4 +-
>  src/mesa/drivers/dri/i965/brw_wm.c|   2 +-
>  src/mesa/drivers/dri/i965/gen6_depth_state.c  |   6 +-
>  src/mesa/drivers/dri/i965/gen7_misc_state.c   |   4 +-
>  src/mesa/drivers/dri/i965/gen8_depth_state.c  |   6 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 106
> +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  42 --
>  src/mesa/drivers/dri/i965/intel_tex_image.c   |   2 +-
>  9 files changed, 80 insertions(+), 96 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 962a316c5cf..a1882abb7cb 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -1212,7 +1212,7 @@ do_single_blorp_clear(struct brw_context *brw,
> struct gl_framebuffer *fb,
>
> /* If the MCS buffer hasn't been allocated yet, we need to allocate it
> now.
>  */
> -   if (can_fast_clear && !irb->mt->mcs_buf) {
> +   if (can_fast_clear && !irb->mt->aux_buf) {
>assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
>if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
>   /* There are a few reasons in addition to out-of-memory, that can
> @@ -1611,7 +1611,7 @@ intel_hiz_exec(struct brw_context *brw, struct
> intel_mipmap_tree *mt,
> brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
> }
>
> -   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
> +   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
>
> struct isl_surf isl_tmp[2];
> struct blorp_surf surf;
> diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
> b/src/mesa/drivers/dri/i965/brw_clear.c
> index 487de9b8997..3d540d6d905 100644
> --- a/src/mesa/drivers/dri/i965/brw_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> @@ -240,7 +240,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
>* buffer when doing a fast clear. Since we are skipping the fast
>* clear here, we need to update the clear color ourselves.
>*/
> - uint32_t clear_offset = mt->hiz_buf->clear_color_offset;
> + uint32_t clear_offset = mt->aux_buf->clear_color_offset;
>   union isl_color_value clear_color = { .f32 = { clear_value, } };
>
>   /* We can't update the clear color while the hardware is still
> using
> @@ -249,7 +249,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
>*/
>   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
>   for (int i = 0; i < 4; i++) {
> -brw_store_data_imm32(brw, mt->hiz_buf->clear_color_bo,
> +brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
>   clear_offset + i * 4,
> clear_color.u32[i]);
>   }
>   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_
> INVALIDATE);
> diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
> b/src/mesa/drivers/dri/i965/brw_wm.c
> index 68d4ab88d77..94048cd758f 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm.c
> @@ -384,7 +384,7 @@ brw_populate_sampler_prog_key_data(struct gl_context
> *ctx,
>   if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
>  assert(devinfo->gen >= 7);
>  assert(intel_tex->mt->surf.samples > 1);
> -assert(intel_tex->mt->mcs_buf);
> +assert(intel_tex->mt->aux_buf);
>  assert(intel_tex->mt->surf.msaa_layout ==
> ISL_MSAA_LAYOUT_ARRAY);
>  key->compressed_multisample_layout_mask |= 1 << s;
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index 3a66b42fec1..8a1d5808051 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -160,13 +160,13 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>   assert(depth_mt);
>
>   uint32_t offset;
> - isl_surf_get_image_offset_B_tile_sa(_mt->hiz_buf->surf,
> + isl_surf_get_image_offset_B_tile_sa(_mt->aux_buf->surf,
>   lod, 0, 0, , NULL,
> NULL);
>
>  BEGIN_BATCH(3);
>  OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
> -OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
> -OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset);
> +OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
> +OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
>  ADVANCE_BATCH();
>} else {
>  BEGIN_BATCH(3);
> diff --git 

Re: [Mesa-dev] [PATCH v3 4/9] i965: Add and use a single miptree aux_buf field

[Rafael Antognolli]

On Wed, Apr 11, 2018 at 01:42:21PM -0700, Nanley Chery wrote:
> We want to add and use a function that accesses the auxiliary buffer's
> clear_color_bo and doesn't care if it has an MCS or HiZ buffer
> specifically.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
>  src/mesa/drivers/dri/i965/brw_clear.c |   4 +-
>  src/mesa/drivers/dri/i965/brw_wm.c|   2 +-
>  src/mesa/drivers/dri/i965/gen6_depth_state.c  |   6 +-
>  src/mesa/drivers/dri/i965/gen7_misc_state.c   |   4 +-
>  src/mesa/drivers/dri/i965/gen8_depth_state.c  |   6 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 106 
> +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  42 --
>  src/mesa/drivers/dri/i965/intel_tex_image.c   |   2 +-
>  9 files changed, 80 insertions(+), 96 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 962a316c5cf..a1882abb7cb 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -1212,7 +1212,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
>  
> /* If the MCS buffer hasn't been allocated yet, we need to allocate it 
> now.
>  */
> -   if (can_fast_clear && !irb->mt->mcs_buf) {
> +   if (can_fast_clear && !irb->mt->aux_buf) {
>assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
>if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
>   /* There are a few reasons in addition to out-of-memory, that can
> @@ -1611,7 +1611,7 @@ intel_hiz_exec(struct brw_context *brw, struct 
> intel_mipmap_tree *mt,
> brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
> }
>  
> -   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
> +   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
>  
> struct isl_surf isl_tmp[2];
> struct blorp_surf surf;
> diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
> b/src/mesa/drivers/dri/i965/brw_clear.c
> index 487de9b8997..3d540d6d905 100644
> --- a/src/mesa/drivers/dri/i965/brw_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> @@ -240,7 +240,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
>* buffer when doing a fast clear. Since we are skipping the fast
>* clear here, we need to update the clear color ourselves.
>*/
> - uint32_t clear_offset = mt->hiz_buf->clear_color_offset;
> + uint32_t clear_offset = mt->aux_buf->clear_color_offset;
>   union isl_color_value clear_color = { .f32 = { clear_value, } };
>  
>   /* We can't update the clear color while the hardware is still using
> @@ -249,7 +249,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
>*/
>   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
>   for (int i = 0; i < 4; i++) {
> -brw_store_data_imm32(brw, mt->hiz_buf->clear_color_bo,
> +brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
>   clear_offset + i * 4, clear_color.u32[i]);
>   }
>   brw_emit_pipe_control_flush(brw, 
> PIPE_CONTROL_STATE_CACHE_INVALIDATE);
> diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
> b/src/mesa/drivers/dri/i965/brw_wm.c
> index 68d4ab88d77..94048cd758f 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm.c
> @@ -384,7 +384,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
>   if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
>  assert(devinfo->gen >= 7);
>  assert(intel_tex->mt->surf.samples > 1);
> -assert(intel_tex->mt->mcs_buf);
> +assert(intel_tex->mt->aux_buf);
>  assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
>  key->compressed_multisample_layout_mask |= 1 << s;
>  
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
> b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index 3a66b42fec1..8a1d5808051 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -160,13 +160,13 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>   assert(depth_mt);
>  
>   uint32_t offset;
> - isl_surf_get_image_offset_B_tile_sa(_mt->hiz_buf->surf,
> + isl_surf_get_image_offset_B_tile_sa(_mt->aux_buf->surf,
>   lod, 0, 0, , NULL, NULL);
>  
>BEGIN_BATCH(3);
>OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
> -  OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
> -  OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset);
> +  OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
> +  OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
>ADVANCE_BATCH();
>} else {
>BEGIN_BATCH(3);
> diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
>