subject:"Re\: \[Mesa\-dev\] \[PATCH v4 6\/6\] i965\: gl_BaseVertex must be zero for non\-indexed draw calls"

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

2018-04-17 Thread Jason Ekstrand


On April 17, 2018 10:31:53 Ian Romanick  wrote:

On 04/10/2018 09:26 AM, Jason Ekstrand wrote:
On Tue, Apr 10, 2018 at 1:28 AM, Antia Puentes > wrote:

On 07/04/18 08:21, Jason Ekstrand wrote:

Oh, boy, this is tricky... First of all, it's a bit of a bummer
that we can't just load the indirect buffer again for this.  Not
too much to do about it, I guess.

Second, there be very scary dragons here.  It turns out that, at
least on Haswell (and possibly other platforms), reading from
state registers while rendering is in-flight can lead to GPU
hangs.  Yes, I said "reading".  We found this out the hard way
while working on Vulkan indirect clear colors.  The better thing
to do here would be to use GPRs when available (I think they're
safe but I'm not sure) or to do a MI_COPY_MEM_MEM which, of
course, is only available on gen8+.  On Ivy Bridge (and haswell if
we're going to do a store_register_mem from a state register), we
need to do a mi_flush *before* the store as well.

I see that this is complicated, I have thought in a different way to
implement this.
Instead of moving gl_BaseVertex to a VE2 and reading its value from
state registers:

- VE1 remains as: 
-> Patches 1-5 are still valid (I think) and we can still calculate
the VertexID as FirstVertex + VertexIDZeroBased.

- VE2 contains: ,
->when asked for glBaseVertex (nir_instrinsic_load_base_vertex), we
would return the value stored in FirstVertex is the draw call is
indexed, zero if it is not.

How does it sound?.

That sounds fine to me.  It's one extra instruciton in the shader (it

Unless there are objections, I'm going to push patches 1 through 5 (with
the extra comment Jason suggested in patch 4) in the morning.

Fine by me. I don't recall having any major objections.


could be an AND if IsIndexedDraw is 0/~0) and lets us avoid trying to do
command-stream copying of data.  If I understand correcctly, Vulkan will
never hit this path because it will always use FIRST_VERETX and not
BASE_VERTEX.  Is that correct?



___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

2018-04-17 Thread Ian Romanick

On 04/10/2018 09:26 AM, Jason Ekstrand wrote:
> On Tue, Apr 10, 2018 at 1:28 AM, Antia Puentes  > wrote:
> 
> On 07/04/18 08:21, Jason Ekstrand wrote:
> 
>> Oh, boy, this is tricky... First of all, it's a bit of a bummer
>> that we can't just load the indirect buffer again for this.  Not
>> too much to do about it, I guess.
>>
>> Second, there be very scary dragons here.  It turns out that, at
>> least on Haswell (and possibly other platforms), reading from
>> state registers while rendering is in-flight can lead to GPU
>> hangs.  Yes, I said "reading".  We found this out the hard way
>> while working on Vulkan indirect clear colors.  The better thing
>> to do here would be to use GPRs when available (I think they're
>> safe but I'm not sure) or to do a MI_COPY_MEM_MEM which, of
>> course, is only available on gen8+.  On Ivy Bridge (and haswell if
>> we're going to do a store_register_mem from a state register), we
>> need to do a mi_flush *before* the store as well.
>>  
> 
> I see that this is complicated, I have thought in a different way to
> implement this.
> Instead of moving gl_BaseVertex to a VE2 and reading its value from
> state registers:
> 
> - VE1 remains as: 
> -> Patches 1-5 are still valid (I think) and we can still calculate
> the VertexID as FirstVertex + VertexIDZeroBased.
> 
> - VE2 contains: ,
> ->when asked for glBaseVertex (nir_instrinsic_load_base_vertex), we
> would return the value stored in FirstVertex is the draw call is
> indexed, zero if it is not.
> 
> How does it sound?.
> 
> That sounds fine to me.  It's one extra instruciton in the shader (it

Unless there are objections, I'm going to push patches 1 through 5 (with
the extra comment Jason suggested in patch 4) in the morning.

> could be an AND if IsIndexedDraw is 0/~0) and lets us avoid trying to do
> command-stream copying of data.  If I understand correcctly, Vulkan will
> never hit this path because it will always use FIRST_VERETX and not
> BASE_VERTEX.  Is that correct?
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

2018-04-11 Thread Antia Puentes



On 10/04/18 18:26, Jason Ekstrand wrote:
On Tue, Apr 10, 2018 at 1:28 AM, Antia Puentes > wrote:


On 07/04/18 08:21, Jason Ekstrand wrote:


On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick > wrote:

From: Antia Puentes >

We keep 'firstvertex' as it is and move gl_BaseVertex to the
drawID
vertex element. The previous Vertex Elements order was:

  * VE 1: 
  * VE 2: 

and now it is:

  * VE 1: 
  * VE 2: 

To move the BaseVertex keeping VE1 as it is, allows to keep
pointing the
vertex buffer associated to VE 1 to the indirect buffer for
indirect
draw calls.

From the OpenGL 4.6 (11.1.3.9 Shader Inputs) specification:

  "gl_BaseVertex holds the integer value passed to the baseVertex
  parameter to the command that resulted in the current shader
  invocation. In the case where the command has no baseVertex
parameter,
  the value of gl_BaseVertex is zero."

Fixes CTS tests:

  *
KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysParameters
  *

KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters
  *
KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
  *

KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters
  *

KHR-GL45.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters

v2 (idr): Make changes to brw_prepare_shader_draw_parameters
matching
those in genX(emit_vertices).  Reformat commit message to 72
columns.

Signed-off-by: Ian Romanick >
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678

---
 src/intel/compiler/brw_nir.c     | 14 +
 src/intel/compiler/brw_vec4.cpp          | 14 +
 src/mesa/drivers/dri/i965/brw_context.h      | 32
++-
 src/mesa/drivers/dri/i965/brw_draw.c         | 45
++-
 src/mesa/drivers/dri/i965/brw_draw_upload.c  | 14 -
 src/mesa/drivers/dri/i965/genX_state_upload.c | 38
+++---
 6 files changed, 97 insertions(+), 60 deletions(-)

diff --git a/src/intel/compiler/brw_nir.c
b/src/intel/compiler/brw_nir.c
index 16b0d86814f..16ab529737b 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -238,8 +238,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
     */
    const bool has_sgvs =
       nir->info.system_values_read &
-      (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
-       BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
+      (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
        BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
        BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
        BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
@@ -279,7 +278,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,

nir_intrinsic_set_base(load, num_inputs);
                switch (intrin->intrinsic) {
-               case nir_intrinsic_load_base_vertex:
                case nir_intrinsic_load_first_vertex:
 nir_intrinsic_set_component(load, 0);
                   break;
@@ -293,11 +291,15 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
 nir_intrinsic_set_component(load, 3);
                   break;
                case nir_intrinsic_load_draw_id:
-                  /* gl_DrawID is stored right after
gl_VertexID and friends
-                   * if any of them exist.
+               case nir_intrinsic_load_base_vertex:
+                  /* gl_DrawID and gl_BaseVertex are stored
right after
+                     gl_VertexID and friends if any of them
exist.
                    */
 nir_intrinsic_set_base(load, num_inputs + has_sgvs);
- nir_intrinsic_set_component(load, 0);
+                  if (intrin->intrinsic ==
nir_intrinsic_load_draw_id)
+  nir_intrinsic_set_component(load, 0);
+                  else
+  nir_intrinsic_set_component(load, 1);
                   break;
                default:
                   unreachable("Invalid system value intrinsic");
diff --git a/src/intel/compiler/brw_vec4.cpp

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

2018-04-10 Thread Jason Ekstrand

On Tue, Apr 10, 2018 at 1:28 AM, Antia Puentes  wrote:

> On 07/04/18 08:21, Jason Ekstrand wrote:
>
> On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick  wrote:
>
>> From: Antia Puentes 
>>
>> We keep 'firstvertex' as it is and move gl_BaseVertex to the drawID
>> vertex element. The previous Vertex Elements order was:
>>
>>   * VE 1: 
>>   * VE 2: 
>>
>> and now it is:
>>
>>   * VE 1: 
>>   * VE 2: 
>>
>> To move the BaseVertex keeping VE1 as it is, allows to keep pointing the
>> vertex buffer associated to VE 1 to the indirect buffer for indirect
>> draw calls.
>>
>> From the OpenGL 4.6 (11.1.3.9 Shader Inputs) specification:
>>
>>   "gl_BaseVertex holds the integer value passed to the baseVertex
>>   parameter to the command that resulted in the current shader
>>   invocation. In the case where the command has no baseVertex parameter,
>>   the value of gl_BaseVertex is zero."
>>
>> Fixes CTS tests:
>>
>>   * KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysParameters
>>   * KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysInstan
>> cedParameters
>>   * KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
>>   * KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysI
>> ndirectParameters
>>   * KHR-GL45.shader_draw_parameters_tests.MultiDrawArraysIndirec
>> tCountParameters
>>
>> v2 (idr): Make changes to brw_prepare_shader_draw_parameters matching
>> those in genX(emit_vertices).  Reformat commit message to 72 columns.
>>
>> Signed-off-by: Ian Romanick 
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
>> ---
>>  src/intel/compiler/brw_nir.c  | 14 +
>>  src/intel/compiler/brw_vec4.cpp   | 14 +
>>  src/mesa/drivers/dri/i965/brw_context.h   | 32 ++-
>>  src/mesa/drivers/dri/i965/brw_draw.c  | 45
>> ++-
>>  src/mesa/drivers/dri/i965/brw_draw_upload.c   | 14 -
>>  src/mesa/drivers/dri/i965/genX_state_upload.c | 38
>> +++---
>>  6 files changed, 97 insertions(+), 60 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
>> index 16b0d86814f..16ab529737b 100644
>> --- a/src/intel/compiler/brw_nir.c
>> +++ b/src/intel/compiler/brw_nir.c
>> @@ -238,8 +238,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>>  */
>> const bool has_sgvs =
>>nir->info.system_values_read &
>> -  (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
>> -   BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
>> +  (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
>> BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
>> BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
>> BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
>> @@ -279,7 +278,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>>
>> nir_intrinsic_set_base(load, num_inputs);
>> switch (intrin->intrinsic) {
>> -   case nir_intrinsic_load_base_vertex:
>> case nir_intrinsic_load_first_vertex:
>>nir_intrinsic_set_component(load, 0);
>>break;
>> @@ -293,11 +291,15 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>>nir_intrinsic_set_component(load, 3);
>>break;
>> case nir_intrinsic_load_draw_id:
>> -  /* gl_DrawID is stored right after gl_VertexID and
>> friends
>> -   * if any of them exist.
>> +   case nir_intrinsic_load_base_vertex:
>> +  /* gl_DrawID and gl_BaseVertex are stored right after
>> + gl_VertexID and friends if any of them exist.
>> */
>>nir_intrinsic_set_base(load, num_inputs + has_sgvs);
>> -  nir_intrinsic_set_component(load, 0);
>> +  if (intrin->intrinsic == nir_intrinsic_load_draw_id)
>> + nir_intrinsic_set_component(load, 0);
>> +  else
>> + nir_intrinsic_set_component(load, 1);
>>break;
>> default:
>>unreachable("Invalid system value intrinsic");
>> diff --git a/src/intel/compiler/brw_vec4.cpp
>> b/src/intel/compiler/brw_vec4.cpp
>> index 1e384f5bf4d..d33caefdea9 100644
>> --- a/src/intel/compiler/brw_vec4.cpp
>> +++ b/src/intel/compiler/brw_vec4.cpp
>> @@ -2825,14 +2825,19 @@ brw_compile_vs(const struct brw_compiler
>> *compiler, void *log_data,
>>  * incoming vertex attribute.  So, add an extra slot.
>>  */
>> if (shader->info.system_values_read &
>> -   (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
>> -BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
>> +   (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
>>  BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
>>

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

2018-04-10 Thread Antia Puentes


On 07/04/18 08:21, Jason Ekstrand wrote:

On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick > wrote:


From: Antia Puentes >

We keep 'firstvertex' as it is and move gl_BaseVertex to the drawID
vertex element. The previous Vertex Elements order was:

  * VE 1: 
  * VE 2: 

and now it is:

  * VE 1: 
  * VE 2: 

To move the BaseVertex keeping VE1 as it is, allows to keep
pointing the
vertex buffer associated to VE 1 to the indirect buffer for indirect
draw calls.

From the OpenGL 4.6 (11.1.3.9 Shader Inputs) specification:

  "gl_BaseVertex holds the integer value passed to the baseVertex
  parameter to the command that resulted in the current shader
  invocation. In the case where the command has no baseVertex
parameter,
  the value of gl_BaseVertex is zero."

Fixes CTS tests:

  * KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysParameters
  *
KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters
  *
KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
  *

KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters
  *
KHR-GL45.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters

v2 (idr): Make changes to brw_prepare_shader_draw_parameters matching
those in genX(emit_vertices).  Reformat commit message to 72 columns.

Signed-off-by: Ian Romanick >
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678

---
 src/intel/compiler/brw_nir.c                  | 14 +
 src/intel/compiler/brw_vec4.cpp               | 14 +
 src/mesa/drivers/dri/i965/brw_context.h       | 32
++-
 src/mesa/drivers/dri/i965/brw_draw.c          | 45
++-
 src/mesa/drivers/dri/i965/brw_draw_upload.c   | 14 -
 src/mesa/drivers/dri/i965/genX_state_upload.c | 38
+++---
 6 files changed, 97 insertions(+), 60 deletions(-)

diff --git a/src/intel/compiler/brw_nir.c
b/src/intel/compiler/brw_nir.c
index 16b0d86814f..16ab529737b 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -238,8 +238,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
     */
    const bool has_sgvs =
       nir->info.system_values_read &
-      (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
-       BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
+      (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
        BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
        BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
        BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
@@ -279,7 +278,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,

                nir_intrinsic_set_base(load, num_inputs);
                switch (intrin->intrinsic) {
-               case nir_intrinsic_load_base_vertex:
                case nir_intrinsic_load_first_vertex:
                   nir_intrinsic_set_component(load, 0);
                   break;
@@ -293,11 +291,15 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
                   nir_intrinsic_set_component(load, 3);
                   break;
                case nir_intrinsic_load_draw_id:
-                  /* gl_DrawID is stored right after gl_VertexID
and friends
-                   * if any of them exist.
+               case nir_intrinsic_load_base_vertex:
+                  /* gl_DrawID and gl_BaseVertex are stored right
after
+                     gl_VertexID and friends if any of them exist.
                    */
                   nir_intrinsic_set_base(load, num_inputs +
has_sgvs);
-                  nir_intrinsic_set_component(load, 0);
+                  if (intrin->intrinsic ==
nir_intrinsic_load_draw_id)
+                     nir_intrinsic_set_component(load, 0);
+                  else
+                     nir_intrinsic_set_component(load, 1);
                   break;
                default:
                   unreachable("Invalid system value intrinsic");
diff --git a/src/intel/compiler/brw_vec4.cpp
b/src/intel/compiler/brw_vec4.cpp
index 1e384f5bf4d..d33caefdea9 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2825,14 +2825,19 @@ brw_compile_vs(const struct brw_compiler
*compiler, void *log_data,
     * incoming vertex attribute.  So, add an extra slot.
     */
    if (shader->info.system_values_read &
-       (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
-

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

2018-04-07 Thread Jason Ekstrand

On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick  wrote:

> From: Antia Puentes 
>
> We keep 'firstvertex' as it is and move gl_BaseVertex to the drawID
> vertex element. The previous Vertex Elements order was:
>
>   * VE 1: 
>   * VE 2: 
>
> and now it is:
>
>   * VE 1: 
>   * VE 2: 
>
> To move the BaseVertex keeping VE1 as it is, allows to keep pointing the
> vertex buffer associated to VE 1 to the indirect buffer for indirect
> draw calls.
>
> From the OpenGL 4.6 (11.1.3.9 Shader Inputs) specification:
>
>   "gl_BaseVertex holds the integer value passed to the baseVertex
>   parameter to the command that resulted in the current shader
>   invocation. In the case where the command has no baseVertex parameter,
>   the value of gl_BaseVertex is zero."
>
> Fixes CTS tests:
>
>   * KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysParameters
>   * KHR-GL45.shader_draw_parameters_tests.ShaderDrawArraysInstancedParam
> eters
>   * KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
>   * KHR-GL45.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectP
> arameters
>   * KHR-GL45.shader_draw_parameters_tests.MultiDrawArraysIndirectCountPa
> rameters
>
> v2 (idr): Make changes to brw_prepare_shader_draw_parameters matching
> those in genX(emit_vertices).  Reformat commit message to 72 columns.
>
> Signed-off-by: Ian Romanick 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
> ---
>  src/intel/compiler/brw_nir.c  | 14 +
>  src/intel/compiler/brw_vec4.cpp   | 14 +
>  src/mesa/drivers/dri/i965/brw_context.h   | 32 ++-
>  src/mesa/drivers/dri/i965/brw_draw.c  | 45
> ++-
>  src/mesa/drivers/dri/i965/brw_draw_upload.c   | 14 -
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 38 +++---
>  6 files changed, 97 insertions(+), 60 deletions(-)
>
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index 16b0d86814f..16ab529737b 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -238,8 +238,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>  */
> const bool has_sgvs =
>nir->info.system_values_read &
> -  (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
> -   BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
> +  (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
> BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
> BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
> BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
> @@ -279,7 +278,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>
> nir_intrinsic_set_base(load, num_inputs);
> switch (intrin->intrinsic) {
> -   case nir_intrinsic_load_base_vertex:
> case nir_intrinsic_load_first_vertex:
>nir_intrinsic_set_component(load, 0);
>break;
> @@ -293,11 +291,15 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>nir_intrinsic_set_component(load, 3);
>break;
> case nir_intrinsic_load_draw_id:
> -  /* gl_DrawID is stored right after gl_VertexID and
> friends
> -   * if any of them exist.
> +   case nir_intrinsic_load_base_vertex:
> +  /* gl_DrawID and gl_BaseVertex are stored right after
> + gl_VertexID and friends if any of them exist.
> */
>nir_intrinsic_set_base(load, num_inputs + has_sgvs);
> -  nir_intrinsic_set_component(load, 0);
> +  if (intrin->intrinsic == nir_intrinsic_load_draw_id)
> + nir_intrinsic_set_component(load, 0);
> +  else
> + nir_intrinsic_set_component(load, 1);
>break;
> default:
>unreachable("Invalid system value intrinsic");
> diff --git a/src/intel/compiler/brw_vec4.cpp
> b/src/intel/compiler/brw_vec4.cpp
> index 1e384f5bf4d..d33caefdea9 100644
> --- a/src/intel/compiler/brw_vec4.cpp
> +++ b/src/intel/compiler/brw_vec4.cpp
> @@ -2825,14 +2825,19 @@ brw_compile_vs(const struct brw_compiler
> *compiler, void *log_data,
>  * incoming vertex attribute.  So, add an extra slot.
>  */
> if (shader->info.system_values_read &
> -   (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
> -BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
> +   (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
>  BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
>  BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
>  BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) {
>nr_attribute_slots++;
> }
>
> +   if (shader->info.system_values_read &
> +   (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
> +

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

6 matches

Site Navigation

Mail list logo

Footer information