Re: question regarding architecture mailing lists

On Mon, 16 Apr 2018, Theo de Raadt wrote: Discuss what? That OpenBSD doesn't run on it? With pleasant requests that someone will write the code? I know there is arm@, but sgi@ does not seem appropriate for Cavium Octeon or other hardware. lists which very few people pay attention to

Re: question regarding architecture mailing lists

Hello Theo, Diana, Yeah .. it was one of those Misc Responses where I responded to a PS with a n essay ... :) basically i was putting a stick in the ground saying "Here be trouble!!"... and offering my humble experience as a MikroTik User for those who might think the tilera would be super

Re: question regarding architecture mailing lists

Diana Eichert wrote: > On Mon, 16 Apr 2018, Theo de Raadt wrote: > > > Diana Eichert wrote: > > > >> Hi Tom > >> > >> Thanks for educating the misc@ masses on Tile hardware. > > > > Unfortunately I don't think misc@ will do much with the info. > > I

Re: question regarding architecture mailing lists

On Mon, 16 Apr 2018, Theo de Raadt wrote: Diana Eichert wrote: Hi Tom Thanks for educating the misc@ masses on Tile hardware. Unfortunately I don't think misc@ will do much with the info. I doubt they will either, however my original question still stands. Is there

Re: question regarding architecture mailing lists

Diana Eichert wrote: > Hi Tom > > Thanks for educating the misc@ masses on Tile hardware. Unfortunately I don't think misc@ will do much with the info.

Re: question regarding architecture mailing lists

Hi Tom Thanks for educating the misc@ masses on Tile hardware. I have quite a bit of experience with Tile h/w prior to the EZchip sale, however we could no longer work with the hardware after the sale. There was anotherBSD Tile-GX port, however it was never committed to their tree. g.day

Re: question regarding architecture mailing lists

Hi Diana That Mikrotik router board is based on originally a tilera chip the chip owner which was sold to ez chip which then sold to mellanox. Im not sure what mellanox are doing with the tech The chip was a tile architecture meaning adding additional cores was easy (ier) for the manufacturer