there're a lot of rapidly growing set of INTEL parallel-aware instructions :
http://software.intel.com/en-us/articles/introduction-to-intel-advanced-vector-extensions
The hardware AES transcoding (Core i* 4+ generation) is also interesting.
*no* implicit type conversions
===
that's with side (unexpected/unwanted) effects.
But what for to disable :
unsigned := signed ?
Here, user know what he/she wants to get (absolute value of the signed).
--
On 12/16/2013 02:29 PM, Ivanko B wrote:
unsigned := signed ?
Here, user know what he/she wants to get
No he does not.
(absolute value of the signed).
Even you don't :-) .
If you do unsigned := signed; you get the correct positive value if
positive. But if it is negative you'll get
But if it is negative you'll get maxunsigned + value + 1, as
===
Really it should do internally smth like :
unsigned:= ABS(signed)
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On 12/16/2013 02:52 PM, Ivanko B wrote:
But if it is negative you'll get maxunsigned + value + 1, as
===
Really it should do internally smth like :
unsigned:= ABS(signed)
-1
This would be different to any known language and much slower.
-Michael
On Monday 16 December 2013 14:29:05 Ivanko B wrote:
*no* implicit type conversions
===
that's with side (unexpected/unwanted) effects.
But what for to disable :
unsigned := signed ?
var
unsigned: card32;
signed: int32;
...
unsigned:= card32(signed);
Assigns the binary value
Then typecasts ABS should be inline-d.
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On Monday 16 December 2013 16:44:24 Ivanko B wrote:
Then typecasts ABS should be inline-d.
Sure.
Martin
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