Re: [PATCH RESEND net-next v2 1/8] dt-bindings: net: dwmac-sun8i: Clean up clock delay chain descriptions

于 2018年5月14日 GMT+08:00 下午12:59:22, Chen-Yu Tsai 写到: >On Sun, May 13, 2018 at 1:29 PM, Andrew Lunn wrote: >> On Sun, May 13, 2018 at 01:11:08PM -0700, Chen-Yu Tsai wrote: >>> On Sun, May 13, 2018 at 1:05 PM, Andrew Lunn wrote: >>> >> > Hi Chen-Yu

Re: [PATCH RESEND net-next v2 1/8] dt-bindings: net: dwmac-sun8i: Clean up clock delay chain descriptions

于 2018年5月14日 GMT+08:00 上午4:05:29, Andrew Lunn 写到: >> > Hi Chen-Yu >> > >> > Are these delays the MAC applies? Not the PHY. It would be good to >> > make it clear here these are MAC imposed delays. >> >> Yes these are applied on the MAC side. Being described in the device >>

Re: [PATCH net-next v2 15/15] arm64: dts: allwinner: a64: add SRAM controller device tree node

于 2018年5月2日 GMT+08:00 下午5:53:21, Chen-Yu Tsai <w...@csie.org> 写到: >On Wed, May 2, 2018 at 5:51 PM, Maxime Ripard ><maxime.rip...@bootlin.com> wrote: >> Hi, >> >> On Wed, May 02, 2018 at 12:12:27AM +0800, Chen-Yu Tsai wrote: >>> From: Icenowy Zhen

Re: [linux-sunxi] Re: [PATCH 3/5] net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device

PM, Maxime Ripard >>> <maxime.rip...@bootlin.com> wrote: >>> > On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote: >>> >> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng <icen...@aosc.io> >wrote: >>> >> > 于 2018年4月12日 GMT+08:00 下午10:5

Re: [PATCH 1/5] dt-bindings: allow dwmac-sun8i to use other devices' exported regmap

于 2018年4月17日 GMT+08:00 上午2:47:45, Rob Herring <r...@kernel.org> 写到: >On Wed, Apr 11, 2018 at 10:16:37PM +0800, Icenowy Zheng wrote: >> On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i >is >> in another device's memory space. In this situation dwmac-su

Re: [linux-sunxi] Re: [PATCH 3/5] net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device

于 2018年4月16日 GMT+08:00 下午10:31:30, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote: >> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng <icen...@aosc.io> >wrote: >> > 于 2018年4月12日 GMT+08:00 下午10:

Re: [PATCH 3/5] net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device

于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Wed, Apr 11, 2018 at 10:16:39PM +0800, Icenowy Zheng wrote: >> From: Chen-Yu Tsai <w...@csie.org> >> >> On the Allwinner R40 SoC, the "GMAC clock" register is

[PATCH 3/5] net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device

i <w...@csie.org> [Icenowy: change to use regmaps with single register, change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 48 ++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git

[PATCH 4/5] drivers: soc: sunxi: export a regmap for EMAC clock reg on A64

The A64 SRAM controller memory zone has a EMAC clock register, which is needed by the Ethernet MAC driver (dwmac-sun8i). Export a regmap for this register on A64. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/soc/sunxi/sunxi_sram.c | 48 +++

[PATCH 5/5] arm64: allwinner: a64: add SRAM controller device tree node

to acquire its EMAC clock regmap. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23 +++ 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/bo

[PATCH 2/5] net: stmmac: dwmac-sun8i: Use regmap_field for syscon register access

de reg_field based on regmap type, change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 41 --- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-

[PATCH 1/5] dt-bindings: allow dwmac-sun8i to use other devices' exported regmap

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt

[PATCH 0/5] Add support in dwmac-sun8i for accessing EMAC clock

-sun8i: Use regmap_field for syscon register access net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device Icenowy Zheng (3): dt-bindings: allow dwmac-sun8i to use other devices' exported regmap drivers: soc: sunxi: export a regmap for EMAC clock reg on A64 arm64: allwinner: a64: add

Re: [PATCH net-next 02/12] clk: sunxi-ng: r40: export a regmap to access the GMAC register

ote: > > > > On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote: > > > > > From: Icenowy Zheng <icen...@aosc.io> > > > > > > > > > > There's a GMAC configuration register, which exists on > > > > > A64/

Re: [PATCH net-next 02/12] clk: sunxi-ng: r40: export a regmap to access the GMAC register

Chen-Yu Tsai wrote: >>> > On Mon, Mar 19, 2018 at 5:31 AM, Maxime Ripard >>> > <maxime.rip...@bootlin.com> wrote: >>> > > On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote: >>> > >> From: Icenowy Zheng <icen..

Re: [PATCH net-next 02/12] clk: sunxi-ng: r40: export a regmap to access the GMAC register

; > <maxime.rip...@bootlin.com> wrote: >> > > On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote: >> > >> From: Icenowy Zheng <icen...@aosc.io> >> > >> >> > >> There's a GMAC configuration register, which exists on >A64

Re: [PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

于 2018年2月3日 GMT+08:00 上午6:13:01, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Sat, Feb 03, 2018 at 02:04:54AM +0800, Icenowy Zheng wrote: >> The V3s is just a differently packaged version of the V3 chip, which >has >> a MAC with the same capability with H3. The V

Re: [linux-sunxi] [PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

于 2018年2月3日 GMT+08:00 下午2:00:33, Julian Calaby <julian.cal...@gmail.com> 写到: >Hi Icenowy, > >On Sat, Feb 3, 2018 at 5:04 AM, Icenowy Zheng <icen...@aosc.io> wrote: >> The V3s is just a differently packaged version of the V3 chip, which >has >> a MAC with the s

[PATCH 0/3] Allwinner V3s EMAC support

support for V3. Icenowy Zheng (3): net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one ARM: sun8i: v3s: add V3s EMAC device tree node ARM: sun8i: v3s: enable Ethernet port on the Lichee Pi Zero Dock .../devicetree/bindings/net/dwmac-sun8i.txt| 10 ++-- arch/arm/boot/dts/sun8i

[PATCH 2/3] ARM: sun8i: v3s: add V3s EMAC device tree node

The V3/V3s EMAC is just similar to the one in H3 SoC, but as the package of V3s is pin-limited, the external MII/MDIO bus is not wired out. Add V3s EMAC device tree node. As V3s is only capable of using the internal PHY, it's hardcoded in the V3s DTSI file. Signed-off-by: Icenowy Zheng <i

[PATCH 1/3] net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one

all capabilities. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 10 +- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 ++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/Documen

[PATCH 3/3] ARM: sun8i: v3s: enable Ethernet port on the Lichee Pi Zero Dock

The Lichee Pi Zero Dock has an Ethernet port connected to the internal PHY of the V3s SoC. Enable it in the device tree. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 8 1 file changed, 8 insertions(+) diff --git a/ar

Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo <kv...@codeaurora.org> 写到: >Icenowy Zheng <icen...@aosc.io> writes: > >> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard >> <maxime.rip...@free-electrons.com> 写到: >>>On Wed, Oct 04, 2017 at 10:02:48AM +00

Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >> > >> > >> > 于 2017年10月4日 GMT+08:00 下午5:02

Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo <kv...@codeaurora.org> 写到: >Icenowy Zheng <icen...@aosc.io> writes: > >> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to >use >> an out-of-band interrupt pin instead of SDIO in-band interrupt.

[PATCH v3 0/2] Allwinner XR819 SDIO Wi-Fi DT binding and OPi Zero XR819 IRQ

, then adds the interrupt to the device tree of Orange Pi Zero. Icenowy Zheng (1): dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi Sergey Matyukevich (1): ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero .../bindings/net/wireless/allwinner,xr819.txt | 38

[PATCH v3 2/2] ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero

endor prefix to allwinner and modify commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3 by Icenowy: - Change the compatible string vendor prefix to "allwinner". - Modify the commit message. Changes in v2 by Sergey: - Adds the compatible string. arch/arm/boo

[PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use an out-of-band interrupt pin instead of SDIO in-band interrupt. Add the device tree binding of this chip, in order to make it possible to add this interrupt pin to device trees. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v2 1/4] net: stmmac: dwmac-sun8i: support RGMII modes with PHY internal delay

Some boards uses a PHY with internal delay with an Allwinner SoC. Support these PHY modes in the driver. As the driver has no configuration registers for these modes, just treat them as ordinary RGMII. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/ethernet/stmicro/stmmac

[PATCH v2 0/4] Workaround broken RTL8211E on some Pine64+ boards

variants' support to the dwmac-sun8i driver. The second patch renames some macros in RTL PHY driver, and the third patch introduces the hack as the "RGMII-TXID" mode of the PHY. The fourth patch enables the hack in the device tree. Icenowy Zheng (4): net: stmmac: dwmac-sun8i: support R

[PATCH v2 2/4] net: phy: realtek: change macro name for page select register

From: Icenowy Zheng <icen...@aosc.xyz> The page select register also exists on RTL8211E PHY (although it behaves slightly differently). Change the register macro name to remove the F. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- drivers/net/phy/realtek.c | 12 +++-

[PATCH v2 3/4] net: phy: realtek: add disable RX internal delay mode

From: Icenowy Zheng <icen...@aosc.xyz> Some RTL8211E chips have broken GbE function, which needs a hack to fix. It's said that this fix will affect the performance on not-buggy PHYs, so it should only be enabled on boards with the broken PHY. Currently only some Pine64+ boards are known t

[PATCH v2 4/4] arm64: allwinner: a64: disable the RTL8211E internal RX delay on Pine64+

Some Pine64+ boards have a broken RTL8211E PHY, which cannot work reliably in 1000Base-T mode with default configuration. A solution is passed to Pine64, which is said to be disabling the internal RX delay of the PHY. Enable the hack by set the PHY mode to RGMII-TXID. Signed-off-by: Icenowy

Re: [PATCH 2/3] ARM: sunxi: h3/h5: Add sun8i-h3-ephy compatible

于 2017年7月28日 GMT+08:00 下午5:44:51, Chen-Yu Tsai 写到: >On Fri, Jul 28, 2017 at 5:28 PM, Corentin Labbe > wrote: >> This patch adds the sun8i-h3-ephy compatible to the internal PHY. >> >> Signed-off-by: Corentin Labbe >> --- >>

[PATCH] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use an out-of-band interrupt pin instead of SDIO in-band interrupt. Add the device tree binding of this chip, in order to make it possible to add this interrupt pin to device trees. Signed-off-by: Icenowy Zheng <icen...@aosc

Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i

于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara 写到: >Hi, > >On 27/06/17 10:41, Maxime Ripard wrote: >> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> (CC:ing some people from that Rockchip dmwac series) >>> >>> On 27/06/17 09:21,

Re: [linux-sunxi] Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i

于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai 写到: >On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard > wrote: >> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> (CC:ing some people from that Rockchip dmwac series)

[PATCH 0/4] net-next: stmmac: dwmac-sun8i: add support for V3s

SoCs doesn't have extra xtal input for EPHY, and the main xtal is 24MHz. The default value of H3 is set to 24MHz, but the V3s default value is set to 25MHz). First two patches are device tree binding patches, the third forces the frequency to 24MHz and the fourth really add the V3s support. Icenowy

[PATCH 2/4] dt-bindings: syscon: Add DT bindings documentation for Allwinner V3s syscon

Allwinner V3s SoC has a syscon like the one in H3. Add its compatible string. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/misc/allwinner,syscon.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/all

[PATCH 3/4] net-next: stmmac: dwmac-sun8i: force EPHY clock freq to 24MHz

the EPHY clock frequency to 24MHz. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

[PATCH 4/4] net-next: stmmac: dwmac-sun8i: add support for V3s EMAC

-related register seems to have changed from H3, but it seems to be a harmless change. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + 2 files changed, 9 inse

[PATCH 1/4] dt-bindings: net-next: Add DT bindings documentation for Allwinner V3s EMAC

Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but have no external MII capability. That means that it can only use the EPHY and cannot do Gbps transmission. Add binding for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/net

[PATCH] net-next: stmmac: dwmac-sun8i: ensure the EPHY is properly reseted

ot-plugged in. Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/dr

Re: [linux-sunxi] Re: [PATCH 2/4] dt-bindings: add binding for RTL8211E Ethernet PHY

于 2017年5月5日 GMT+08:00 上午2:21:29, Florian Fainelli <f.faine...@gmail.com> 写到: >On 05/04/2017 11:10 AM, icen...@aosc.io wrote: >> 在 2017-04-22 08:22，Florian Fainelli 写道： >>> On 04/21/2017 04:24 PM, Icenowy Zheng wrote: >>>> From: Icenowy Zheng <icen...@aos

[PATCH 4/4] [DO NOT MERGE] arm64: allwinner: a64: enable RTL8211E PHY workaround

From: Icenowy Zheng <icen...@aosc.xyz> Some Pine64+ boards are said to have broken RTL8211E PHY. Enable the workaround in Pine64+ device tree file. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 4 1 fil

[PATCH 3/4] net: phy: realtek: add disable RX delay hack for RTL8211E

From: Icenowy Zheng <icen...@aosc.xyz> Some RTL8211E chips have broken GbE function, which needs a hack to fix. It's said that this fix will affect the performance on not-buggy PHYs, so it should only be enabled on boards with the broken PHY. Currently only some Pine64+ boards are known t

[PATCH 2/4] dt-bindings: add binding for RTL8211E Ethernet PHY

From: Icenowy Zheng <icen...@aosc.xyz> Some RTL8211E Ethernet PHY have an issue that needs a workaround indicated with device tree. Add the binding for a property that indicates this workaround. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- .../devicetree/bindings

[PATCH 1/4] net: phy: realtek: change macro name for page select register

From: Icenowy Zheng <icen...@aosc.xyz> The page select register also exists on RTL8211E PHY (although it behaves slightly differently). Change the register macro name to remove the F. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- drivers/net/phy/realtek.c | 12 +++-

[PATCH 0/4] RTL8211E-specified hacks

eal driver part of this hack, which contains some magic numbers from Pine64/Realtek. The fourth patch is for reference only and should not be merged -- to use it you will need sun8i-emac or dwmac-sun8i patchset applied. Icenowy Zheng (4): net: phy: realtek: change macro name for page select reg