Hi,
On Tue, May 15, 2018 at 11:47:16PM -0700, Chen-Yu Tsai wrote:
> On Mon, May 14, 2018 at 1:03 AM, Maxime Ripard
> <maxime.rip...@bootlin.com> wrote:
> > 1;5201;0c
> > On Sun, May 13, 2018 at 12:37:49PM -0700, Chen-Yu Tsai wrote:
> >> On Wed, May 2, 2018 at 4
1;5201;0c
On Sun, May 13, 2018 at 12:37:49PM -0700, Chen-Yu Tsai wrote:
> On Wed, May 2, 2018 at 4:54 AM, Maxime Ripard <maxime.rip...@bootlin.com>
> wrote:
> > On Wed, May 02, 2018 at 06:19:51PM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 于 2
because
> that is the range supported by the control register. Not implementing, i.e.
> supporting the whole range from the property, which might get truncated,
> doesn't make much sense to me.
With that driver we don't, but the previous design had the same
feature and it was used on more boards. It was simply initialized
statically in U-Boot, and not in Linux through the DT like it is done
here.
Maxime
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On Thu, May 03, 2018 at 02:40:42PM -0400, David Miller wrote:
> From: Maxime Ripard <maxime.rip...@bootlin.com>
> Date: Thu, 3 May 2018 15:12:57 +0200
>
> > Hi Dave,
> >
> > On Wed, May 02, 2018 at 11:06:17AM -0400, David Miller wrote:
> >> From: Chen
ll the patches relevant to enable a
particular feature, even if it means getting multiple maintainers
involved.
Just to make sure we understood you fully, do you want Chen-Yu to
resend his serie following your comments, or was that just a general
remark for next time?
Thanks!
Maxime
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On Wed, May 02, 2018 at 06:19:51PM +0800, Icenowy Zheng wrote:
>
>
> 于 2018年5月2日 GMT+08:00 下午5:53:21, Chen-Yu Tsai <w...@csie.org> 写到:
> >On Wed, May 2, 2018 at 5:51 PM, Maxime Ripard
> ><maxime.rip...@bootlin.com> wrote:
> >> Hi,
> >>
> >
ng preventing us from keeping the
-system-controller compatible. It's what was in the DT before, and
it's how it's called in the datasheet.
Otherwise, the whole serie looks good to me:
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com>
Maxime
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On Mon, Apr 16, 2018 at 10:51:55PM +0800, Chen-Yu Tsai wrote:
> On Mon, Apr 16, 2018 at 10:31 PM, Maxime Ripard
> <maxime.rip...@bootlin.com> wrote:
> > On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
> >> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zh
On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> > 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard
> > <maxime.rip...@bootlin.com> 写到:
> >>On Wed, Apr 11, 2018 at 1
llwinner,sun50i-a64-sram-c";
> + reg = <0x 0x28000>;
> + };
> + };
That doesn't look related at all to what's being discussed here, so
you'd rather add it as part of your DE2-enablement
lling sites
everywhere in the kernel, which will be a pain and will break
bisectability.
Chen-Yu's (or was it yours?) initial solution with a custom writeable
hook only allowing a single register seemed like a better one.
Maxime
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On Tue, Apr 03, 2018 at 05:58:05PM +0800, Chen-Yu Tsai wrote:
> On Tue, Apr 3, 2018 at 5:54 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> >
> >
> > 于 2018年4月3日 GMT+08:00 下午5:53:08, Chen-Yu Tsai <w...@csie.org> 写到:
> >>On Tue, Apr 3, 2018 at 5:50 PM, Ma
On Tue, Apr 03, 2018 at 11:48:45AM +0200, Maxime Ripard wrote:
> On Tue, Mar 20, 2018 at 03:15:02PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Mar 19, 2018 at 5:31 AM, Maxime Ripard
> > <maxime.rip...@bootlin.com> wrote:
> > > On Sat, Mar 17, 2018 at 05:28:47PM +0800, C
On Tue, Mar 20, 2018 at 03:15:02PM +0800, Chen-Yu Tsai wrote:
> On Mon, Mar 19, 2018 at 5:31 AM, Maxime Ripard
> <maxime.rip...@bootlin.com> wrote:
> > On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote:
> >> From: Icenowy Zheng <icen...@aosc.io>
>
the first place...
And I'm not really looking forward the time where SCPI et al. will be
mature and we'll have the clock controller completely outside of our
control.
Maxime
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Hi,
On Sat, Feb 03, 2018 at 03:23:28PM +0800, Icenowy Zheng wrote:
> 于 2018年2月3日 GMT+08:00 上午6:13:01, Maxime Ripard <maxime.rip...@bootlin.com> 写到:
> >On Sat, Feb 03, 2018 at 02:04:54AM +0800, Icenowy Zheng wrote:
> >> The V3s is just a differently packaged version of t
mpatible string of V3s in the dwmac-sun8i driver, and add a
> V3 compatible string, which has all capabilities.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>
This breaks the DT ABI, so NAK.
Maxime
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blink,
> > nobody see that it was broken.
>
> Hi Corentin
>
> So it never worked?
>
> If it never worked, moving the DT properties into the PHY node, where
> they belong, won't introduce a regression :-)
That's even truer since it's been queued for 4.15 which hasn't been
released yet.
Maxime
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ied the patches, and I'll send a PR for it tomorrow after one
linux-next run.
Hopefully it will be merged in time for 4.15.
Thanks for your persistence,
Maxime
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;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mdio-parent-bus = <>;
And you should have a line here.
Thanks!
Maxime
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35 insertions(+)
Can you split the changes between the A64 and the H5? It's going to be
difficult to merge otherwise.
(You also forgot to add Florian's Acked-by on your whole serie).
Maxime
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t; > > };
> > >
> > > + {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <_rgmii_pins>;
> > > + phy-supply = <_gmac_3v3>;
> > > + phy-handle = <_rgmii_phy>;
> > > + phy-mode = "rgmii";
&g
and reset. (this is done in
> get_ephy_nodes)
> The current version set those clock in mdio-mux node, and as you can see it
> is already ugly (lots of get next node),
> if the clk/rst nodes were as it should be, in phy nodes, it will be more bad.
>
> So, since the MAC have a dep
Icenowy Zheng <icen...@aosc.xyz>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>
> Signed-off-by: Rob Herring <r...@kernel.org>
> """
>
> Regardless the bindings are in principle independent of the kernel and just
> describing hardware. I think there have been discussions to move the
> bindings to their own repository, but apparently it was decided otherwise.
Yeah, I guess especially how it could be merged with the cw1200 driver
would be very relevant to that commit log.
Maxime
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Hi,
On Wed, Sep 27, 2017 at 07:34:08AM +, Corentin Labbe wrote:
> This patch add documentation about the MDIO switch used on sun8i-h3-emac
> for integrated PHY.
>
> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>
This should be squashed with patch 1.
Maxime
802.3-c22";
> + reg = <1>;
> + clocks = <
> CLK_BUS_EPHY>;
> + resets = <
> RST_BUS_EPHY>;
> +
clk_disable_unprepare(gmac->ephy_clk);
> reset_control_assert(gmac->rst_ephy);
> + reset_control_put(gmac->rst_ephy);
Putting it here is weird.
What would happen if power_phy / unpower_phy is called several times?
Can't we just make it symetric and undo in remove wh
PHY
> +
> +emac: ethernet@1c0b000 {
> + compatible = "allwinner,sun8i-a83t-emac";
> + syscon = <>;
> + reg = <0x01c0b000 0x104>;
> + interrupts = ;
> + interrupt-names = "macirq";
> + resets = < RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> + clocks = < CLK_BUS_EMAC>;
> + clock-names = "stmmaceth";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy-handle = <_rgmii_phy>;
> + phy-mode = "rgmii";
> +
> mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> #address-cells = <1>;
> #size-cells = <0>;
> - int_mii_phy: ethernet-phy@1 {
> + ext_rgmii_phy: ethernet-phy@1 {
> reg = <1>;
> - clocks = < CLK_BUS_EPHY>;
> - resets = < RST_BUS_EPHY>;
> };
> };
> };
> --
> 2.13.5
>
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phy-mode = "rgmii";
> + status = "okay";
> +};
> +
> + {
> + ext_rgmii_phy: ethernet-phy@7 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + };
> +};
> +
This won't compile, you don't have that node in the H5 DTSI.
Maxime
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This binding still doesn't please everyone, and we're getting far too
close from the release to allow it to reach a stable version.
Let's remove it until the discussion settles down.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
.../devicetree/bindings/net/dwmac-sun
Maxime Ripard (4):
dt-bindings: net: Revert sun8i dwmac binding
arm64: dts: allwinner: Revert EMAC changes
arm: dts: sunxi: Revert EMAC changes
net: stmmac: sun8i: Remove the compatibles
.../devicetree/bindings/net/dwmac-sun8i.txt| 84 --
arch/arm/boot/dts/sun8i-h2
Since the discussion is not settled yet for the EMAC, and that the release
in getting really close, let's revert the changes for now, and we'll
reintroduce them later.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
Since the discussion is not settled yet for the EMAC, and that the release
in getting really close, let's revert the changes for now, and we'll
reintroduce them later.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dt
implemented. This commit will
obviously need to be reverted in due time.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8
On Fri, Aug 25, 2017 at 05:17:33PM +0200, Corentin Labbe wrote:
> On Fri, Aug 25, 2017 at 04:48:32PM +0200, Maxime Ripard wrote:
> > On Fri, Aug 25, 2017 at 04:38:05PM +0200, Corentin Labbe wrote:
> > > The current dwmac_sun8i module cannot be rmmod/modprobe due to that
> >
ice *pdev)
> return -EINVAL;
> }
>
> - gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
> + gmac->rst_ephy =
> of_reset_control_get_exclusive(plat_dat->phy_node, NULL);
Why not just use devm_re
On Wed, Aug 23, 2017 at 09:31:53AM -0700, Florian Fainelli wrote:
> On 08/23/2017 12:49 AM, Maxime Ripard wrote:
> > Hi Florian,
> >
> > On Tue, Aug 22, 2017 at 11:35:01AM -0700, Florian Fainelli wrote:
> >>>>> So I think what you are saying is either imposs
h all the internal and external PHY node definition
> (in its entirety) to the per-board DTS file, does not that work?
If possible, I'd really like to have the internal PHY in the
DTSI. It's always there in hardware anyway, and duplicating the PHY,
with its clock, reset line, and whatever info we might n
t if we don't have an
agreement and a patch implementing it with the proper acks by the end
of the week, we'll have to revert all the DT bits and the bindings.
Maxime
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y afaik, or do you
want to simply introduce a new compatible / property?
Thanks!
Maxime
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a new phy-mode value, e.g: "internal-rmii"
> > which describes that, either way would probably be fine, but the former
> > scales better
>
> We have the same problem on Allwinner SoCs for dwmac-sun8i, we need
> to set a syscon for chossing between internal/external PHY.
>
> Having this phy-is-internal would be very helpfull. (adding
> internal-xmii will add too many flags in our case)
In our case, we'll always have a phy node, so we can have a compatible
that will give you the same information.
Maxime
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("arm: sun8i:
orangepi-2: use internal phy-mode") that should be merged
through the arm-soc tree, and end up in merge conflicts and build failures.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 8 --
ndre Przywara <andre.przyw...@arm.com>
> > > 写到:
> > >> Hi,
> > >>
> > >> On 27/06/17 10:41, Maxime Ripard wrote:
> > >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
> > >>>> Hi,
> > >>>
On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote:
> Hi,
>
> On 27/06/17 11:23, Icenowy Zheng wrote:
> >
> >
> > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przyw...@arm.com>
> > 写到:
> >> Hi,
> >>
> >>
t; >
> > https://lkml.org/lkml/2017/6/23/479
> >
> >>
> >> I'm not a fan of using phy-mode for this. There's no guarantee what
> >> mode the internal PHY uses. That's what phy-mode is for.
>
> I can understand Chen-Yu's concerns, but ...
>
> > For each soc the internal PHY mode is know and setted in
> > emac_variant/internal_phy
> > So its not a problem.
>
> that is true as well, at least for now.
>
> So while I agree that having a separate property to indicate the usage
> of the internal PHY would be nice, I am bit tempted to use this easier
> approach and piggy back on the existing phy-mode property.
We're trying to fix an issue that works for now too.
If we want to consider future weird cases, then we must consider all
of them. And the phy mode changing is definitely not really far
fetched.
I agree with Chen-Yu, and I really feel like the compatible solution
you suggested would cover both your concerns, and ours.
Maxime
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On Sat, Jun 03, 2017 at 12:24:22AM +0200, Maxime Ripard wrote:
> Hi,
>
> On Fri, Jun 02, 2017 at 10:22:05AM -0400, David Miller wrote:
> > From: Maxime Ripard <maxime.rip...@free-electrons.com>
> > Date: Fri, 2 Jun 2017 11:13:20 +0200
> >
> > > On Fri
Hi,
On Fri, Jun 02, 2017 at 10:22:05AM -0400, David Miller wrote:
> From: Maxime Ripard <maxime.rip...@free-electrons.com>
> Date: Fri, 2 Jun 2017 11:13:20 +0200
>
> > On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote:
> >> On Thu, Jun 01, 2017 at 02:58:
On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote:
> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
> > From: Corentin Labbe <clabbe.montj...@gmail.com>
> > Date: Wed, 31 May 2017 09:18:31 +0200
> >
> > > This patch series add the
on Allwinner H3/H5/A83T/A64 SoCs.
>
> Series applied, but wow that's a lot of DT file changes :-(
The DT patches should not go through your tree, but arm-soc, so I
guess this is not an issue for you?
Maximee
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On Wed, Apr 12, 2017 at 01:14:00PM +0200, Corentin Labbe wrote:
> Enable the dwmac-sun8i driver in the multi_v7 default configuration
>
> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>
Maybe we should enable that in arm64's defconfig too?
Maxime
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xt
patch also have this issue).
Maxime
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"PD17", "PD18", "PD19", "PD20",
> + "PD22", "PD23";
Please align the wrapped lines on the first pin.
> + function = "emac";
> +
> chosen {
> @@ -184,3 +185,10 @@
> /* USB VBUS is always on */
> status = "okay";
> };
> +
> + {
> + phy-handle = <_mii_phy>;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + status = "okay"
On Mon, Apr 03, 2017 at 11:14:44AM +0200, Corentin Labbe wrote:
> Enable the dwmac-sun8i driver in the multi_v7 default configuration
Your prefix should be arm: multi_v7:
Maxime
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" as your title
prefix. It applies to all your other patches (and the arm ones should
be "arm: : :".
Thanks!
Maxime
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pins = "PG11";
> function = "gpio_out";
> };
> +
> + gmac_power_pin_orangepi: gmac_power_pin@0 {
> + pins = "PD6";
> + function = "gpio_out";
> + drive-strength = <10>;
&
ontroller"
> + "allwinner,sun8i-a64-system-controller"
> + "allwinner,sun8i-a83t-system-controller"
> +
> +Example:
> +syscon: syscon@01c0 {
> + compatible = "syscon", "allwinner,sun8i-h3-system-controller"
+Optional properties:
> +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07.
> Default is 0)
> +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F.
> Default is 0)
> +Both delay properties are in 0.1ns step.
allwinner,tx-delay-ps and a
On Fri, Feb 17, 2017 at 02:18:02PM +0100, Corentin Labbe wrote:
> On Thu, Feb 16, 2017 at 08:05:24PM +0100, Maxime Ripard wrote:
> > Hi,
> >
>
> [...]
> > > +
> > > +struct emac_variant {
> > > + u32 default_syscon_value;
> >
>
n8i-h3-emac":
> +- clocks: an extra phandle to the reference clock for the EPHY
> +- resets: an extra phandle to the reset control for the EPHY
> +
> +Required properties for the system controller:
> +- reg: address and length of the register for the device.
> +- compatible: should be &qu
ot;PD17";
> + allwinner,function = "emac";
Please use the generic pin config properties (ie. pins and functions).
> + allwinner,drive = ;
Why do you need to use 40mA?
> + allwinner,pull = ;
This is the default now.
Thanks!
Maxime
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ret = PTR_ERR(gmac->regmap);
> + dev_err(>dev, "unable to map SYSCON:%d\n", ret);
> + return ret;
> + }
> +
> + plat_dat->interface = of_get_phy_mode(dev->of_node);
> + if (plat_dat->interface == gmac->variant->internal_phy) {
> + dev_info(>dev, "Will use internal PHY\n");
> + gmac->use_internal_phy = true;
> + gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
> + if (IS_ERR(gmac->ephy_clk)) {
> + ret = PTR_ERR(gmac->ephy_clk);
> + dev_err(>dev, "Cannot get EPHY clock err=%d\n",
> + ret);
> + return -EINVAL;
> + }
> +
> + gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
> + if (IS_ERR(gmac->rst_ephy)) {
> + ret = PTR_ERR(gmac->rst_ephy);
> + if (ret == -EPROBE_DEFER)
> + return ret;
> + dev_err(>dev, "No EPHY reset control found %d\n",
> + ret);
> + return -EINVAL;
> + }
> + } else {
> + dev_info(>dev, "Will use external PHY\n");
> + gmac->use_internal_phy = false;
> + }
> +
> + /* platform data specifying hardware features and callbacks.
> + * hardware features were copied from Allwinner drivers.
> + */
> + plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
> + plat_dat->tx_coe = 1;
> + plat_dat->has_sun8i = true;
> + plat_dat->bsp_priv = gmac;
> + plat_dat->init = sun8i_dwmac_init;
> + plat_dat->exit = sun8i_dwmac_exit;
> + plat_dat->setup = sun8i_dwmac_setup;
> +
> + ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
> + if (ret)
> + return ret;
> +
> + ret = stmmac_dvr_probe(>dev, plat_dat, _res);
> + if (ret)
> + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id sun8i_dwmac_match[] = {
> + { .compatible = "allwinner,sun8i-h3-emac",
> + .data = _variant_h3 },
> + { .compatible = "allwinner,sun8i-a83t-emac",
> + .data = _variant_a83t },
> + { .compatible = "allwinner,sun50i-a64-emac",
> + .data = _variant_a64 },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
> +
> +static struct platform_driver sun8i_dwmac_driver = {
> + .probe = sun8i_dwmac_probe,
> + .remove = stmmac_pltfr_remove,
> + .driver = {
> + .name = "sun8i-dwmac",
> + .pm = _pltfr_pm_ops,
> + .of_match_table = sun8i_dwmac_match,
> + },
> +};
> +module_platform_driver(sun8i_dwmac_driver);
> +
> +MODULE_AUTHOR("Corentin Labbe <clabbe.montj...@gmail.com>");
> +MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> index 5ff6bc4..11db658 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> @@ -450,6 +450,9 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
> for (i = 0; i < 22; i++)
> reg_space[i + 55] =
> readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
> + } else if (priv->plat->has_sun8i) {
Surely we don't want to add a new flag to the common structure for
every new platform supported.
Can't you base that on the compatible instead?
Thanks a lot for your work,
Maxime
--
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gt; @@ -40,6 +40,7 @@ CONFIG_ATA=y
> CONFIG_AHCI_SUNXI=y
> CONFIG_NETDEVICES=y
> CONFIG_SUN4I_EMAC=y
> +CONFIG_DWMAC_SUN8I=m
I think I'd prefer to have it compiled statically, just like the other
net drivers, and drivers in general.
Thanks!
Maxime
--
Maxime Ripard, Free Elec
t; after calling of_parse_phandle")
> Signed-off-by: Johan Hovold <jo...@kernel.org>
For the sunxi part,
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Thanks!
Maxime
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Add the ability to switch diagnostic messages on using either a module
> parameter debug or ethtool -s msglvl .
>
> Signed-off-by: Michael Weiser <michael.wei...@gmx.de>
> Cc: Maxime Ripard <maxime.rip...@free-electrons.com>
> Cc: netdev@vger.kernel.org
Acked-by: Maxime Ripard
e swapped to CPU endianness to make sense to the driver. This
> is already done for the "receive header" but not rxhdr.
>
> Read rxhdr using readl in order for sun4i-emac to work correctly when
> running a big-endian kernel.
>
> Signed-off-by: Michael Weiser <mich
aliases {
> > serial0 =
> > + ethernet0 =
>
> As there is no 'of_alias_get_id' in the driver, this alias is
> useless.
Not really, this is used by U-Boot to set the mac address.
Maxime
--
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On Mon, Oct 10, 2016 at 02:50:21PM +0200, Jean-Francois Moine wrote:
> On Mon, 10 Oct 2016 14:31:51 +0200
> Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
>
> > Hi,
> >
> > On Fri, Oct 07, 2016 at 10:25:51AM +0200, Corentin Labbe wrote:
> > >
On Mon, Oct 10, 2016 at 03:09:43PM +0200, Jean-Francois Moine wrote:
> On Mon, 10 Oct 2016 14:35:11 +0200
> LABBE Corentin <clabbe.montj...@gmail.com> wrote:
>
> > On Mon, Oct 10, 2016 at 02:30:46PM +0200, Maxime Ripard wrote:
> > > On Fri, Oct 07, 2016 at 10:25:57
e a more specific compatible here in addition
to the syscon, like "allwinner,sun8i-h3-system-controller".
Thanks,
Maxime
--
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;;
> + phy-mode = "mii";
> + allwinner,leds-active-low;
> + mdio: mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + int_mii_phy: ethernet-phy@1 {
> + reg = <1>;
> + clocks = < CLK_BUS_EPHY>;
> + resets = < RST_BUS_EPHY>;
That works for me, let's see how the DT maintainers feel about it.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
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t; CONFIG_VIRTIO_NET=y
> CONFIG_HIX5HD2_GMAC=y
> CONFIG_SUN4I_EMAC=y
> +CONFIG_SUN8I_EMAC=y
Any reason to build it statically?
Thanks,
Maxime
--
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emac",
> > > .data = _variant_a83t },
> > > @@ -2246,6 +2302,8 @@ static struct platform_driver sun8i_emac_driver = {
> > > .name = "sun8i-emac",
> > > .of_match_table = sun8i_emac_of_match_table,
> > > },
> > > + .suspend= sun8i_emac_suspend,
> > > + .resume = sun8i_emac_resume,
> >
> > These are not the runtime PM hooks. How did you test that?
> >
>
> Anyway I didnt test suspend/resume so I will remove it until I
> successfully found how to hibernate my board.
So you submit code you never tested? That's usually a recipe for
disaster.
Maxime
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with NAPI, the phy and so on is irrelevant here, but
the clocks, resets, for example, are.
> static const struct of_device_id sun8i_emac_of_match_table[] = {
> { .compatible = "allwinner,sun8i-a83t-emac",
> .data = _variant_a83t },
> @@ -2246,6 +2302,8 @@ static struct platform_driver sun8i_emac_driver = {
> .name = "sun8i-emac",
> .of_match_table = sun8i_emac_of_match_table,
> },
> + .suspend= sun8i_emac_suspend,
> + .resume = sun8i_emac_resume,
These are not the runtime PM hooks. How did you test that?
Maxime
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Hi,
On Fri, Sep 09, 2016 at 02:45:16PM +0200, Corentin Labbe wrote:
> Enable the sun8i-emac driver in the sunxi default configuration
>
> Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>
Could you make the same patch for multi_v7 ?
Thanks,
Maxime
--
Maxime Ripard,
resets = < RST_BUS_EMAC>, < RST_BUS_EPHY>;
> + reset-names = "ahb", "ephy";
> + clocks = < CLK_BUS_EMAC>, < CLK_BUS_EPHY>;
> + clock-names = "ahb", "ephy";
I still believe that having the same node for both the PHY and the MAC
is wrong.
Maxime
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ld be nice here. syscon doesn't mean anything
by itself.
> + reg = <0x01c0 0x34>;
And the size of our system controller is 0x1000
Maxime
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nt think that tuning it give any gain
> - Knowing it's value is of little interest
You don't have to implement anything, you can just register a clk_div
driver, and everything works, and you would use the proper clock APIs
(ie. clk_set_rate, and that's it).
That would be exposed just like any o
t TX descriptor
> >> > > + * and TX DMA FSM is suspended.
> >> > > + */
> >> > > + if (v & BIT(2))
> >> > > + priv->estats.tx_dma_ua++;
> >> > > +
> >> > > + if (v & BIT(3))
> >> > > +
; I have searched for txdelay in Documentation, and found a few driver
> that give the units (us/ps).
>
> But in that case, the value in ps/us must be found in a table
> indexed by the Xxdelay value.
>
> So the settings seems always a raw number, and for sun8i-emac
> nothing in user m
running from).
> > > +}
> > > +
> > > +static int sun8i_emac_probe(struct platform_device *pdev)
> > > +{
> > > + struct device_node *node = pdev->dev.of_node;
> > > + struct sun8i_emac_priv *priv;
> > > + struct net_device *ndev;
> > > + struct resource *res;
> > > + int ret;
> > > +
> > > + ret = dma_set_mask_and_coherent(>dev, DMA_BIT_MASK(32));
> > > + if (ret) {
> > > + dev_err(>dev, "No suitable DMA available\n");
> > > + return ret;
> > > + }
> >
> > Isn't that the default?
> >
> No, it is necessary on arm64 as apritzel requested.
http://lxr.free-electrons.com/source/drivers/of/device.c#L93
It seems to be shared between the two.
Thanks!
Maxime
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
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On Thu, Jul 28, 2016 at 03:40:31PM +0200, LABBE Corentin wrote:
> On Thu, Jul 21, 2016 at 09:55:19AM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > On Wed, Jul 20, 2016 at 10:03:18AM +0200, LABBE Corentin wrote:
> > > This patch adds documentation for Device-Tree bi
On Wed, Jul 20, 2016 at 10:03:16AM +0200, LABBE Corentin wrote:
> This patch add support for sun8i-emac ethernet MAC hardware.
> It could be found in Allwinner H3/A83T/A64 SoCs.
>
> It supports 10/100/1000 Mbit/s speed with half/full duplex.
> It can use an internal PHY (MII 10/100) or an
roperties for "allwinner,sun8i-h3-emac":
> +- allwinner,use-internal-phy: Use the H3 SoC's internal E(thernet) PHY
Can't that be derived from the presence of the phy property?
> +- allwinner,leds-active-low: EPHY LEDs are active low
That also seems PHY related. Overall, I feel like we really need a phy
node for the internal phy.
Maxime
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t;
> And while at it also add error checking to the clk_prepare_enable call
> done on probe.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Ker
t;
> And while at it also add error checking to the clk_prepare_enable call
> done on probe.
>
> Signed-off-by: Hans de Goede <hdego...@redhat.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Ker
On Wed, Sep 16, 2015 at 01:21:19PM +0200, Gerhard Bertelsmann wrote:
> Devicetree bindings for Allwinner A10/A20 CAN
>
> Signed-off-by: Gerhard Bertelsmann <i...@gerhard-bertelsmann.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Thanks!
Maxime
--
Maxime R
0 0x400>;
> > + interrupts = <0 26 4>;
> > + clocks = <_gates 4>;
> > + status = "disabled";
> > + };
>
> What about adding this snippet to SoC where the CAN core is available?
> Maxime, what's the policy on si
On Wed, Sep 16, 2015 at 01:21:18PM +0200, Gerhard Bertelsmann wrote:
> Hi,
>
> please find attached the next version of my patch set. I have
> taken all remarks from Maxime Ripard into the new version
>
> Please review, test and report bugs if exists.
>
> The patchs
On Thu, Sep 17, 2015 at 08:12:31PM +0200, Oliver Hartkopp wrote:
>
>
> On 17.09.2015 19:54, Maxime Ripard wrote:
> >On Wed, Sep 16, 2015 at 01:21:18PM +0200, Gerhard Bertelsmann wrote:
> >>Hi,
> >>
> >>please find attached the next version of my pa
On Wed, Sep 16, 2015 at 01:21:22PM +0200, Gerhard Bertelsmann wrote:
> Kernel module for Allwinner A10/A20 CAN
>
> Signed-off-by: Gerhard Bertelsmann <i...@gerhard-bertelsmann.de>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Thanks!
Maxime
--
Maxime R
un4i_can.txt
> @@ -0,0 +1,38 @@
> +Allwinner A10/A20 CAN controller Device Tree Bindings
> +-
> +
> +Required properties:
> +- compatible: "allwinner,sun4ican"
A bit better, but still not the one I told you to us
arm/configs/sunxi_defconfig | 2 +
> 2 files changed, 3 insertions(+)
Sorry if it wasn't clear, I meant one patch for each defconfig.
Thanks!
Maxime
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> +static const struct of_device_id sunxican_of_match[] = {
> + {.compatible = "allwinner,sun4ican"},
allwinner,sun4i-a10-can
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, sunxican_of_match);
> +
> +static int sunxican_remove(struct platform_device *pdev)
> +{
> + struct net_device *dev = platform_get_drvdata(pdev);
> +
> + unregister_netdev(dev);
> + free_candev(dev);
> +
> + return 0;
> +}
> +
> +static int sunxican_probe(struct platform_device *pdev)
> +{
> + struct resource *mem;
> + struct clk *clk;
> + void __iomem *addr;
> + int err, irq;
> + struct net_device *dev;
> + struct sunxican_priv *priv;
> +
> + clk = devm_clk_get(>dev, "apb1_can");
You still don't use the DT for the lookup and use the global
name. This relies on the fact that we use clkdev, which will be
removed soon, causes issue if you have several can controllers in the
device, and makes your clock property useless.
As I said before, just passing NULL as the ID will do the right thing.
> + if (IS_ERR(clk)) {
> + dev_err(>dev, "no clock defined\n");
> + err = -ENODEV;
> + goto exit;
> + }
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(>dev, "could not get a valid irq\n");
> + err = -ENODEV;
> + goto exit;
> + }
> +
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + addr = devm_ioremap_resource(>dev, mem);
> + if (IS_ERR(addr)) {
> + err = -EBUSY;
> + goto exit;
> + }
> +
> + dev = alloc_candev(sizeof(struct sunxican_priv), 1);
> + if (!dev) {
> + dev_err(>dev,
> + "could not allocate memory for CAN device\n");
> + err = -ENOMEM;
> + goto exit;
> + }
> +
> + dev->netdev_ops = _netdev_ops;
> + dev->irq = irq;
> + dev->flags |= IFF_ECHO;
> +
> + priv = netdev_priv(dev);
> + priv->can.clock.freq = clk_get_rate(clk);
> + priv->can.bittiming_const = _bittiming_const;
> + priv->can.do_set_mode = sunxican_set_mode;
> + priv->can.do_get_berr_counter = sunxican_get_berr_counter;
> + priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
> +CAN_CTRLMODE_LISTENONLY |
> +CAN_CTRLMODE_LOOPBACK |
> +CAN_CTRLMODE_PRESUME_ACK |
> +CAN_CTRLMODE_3_SAMPLES;
> + priv->base = addr;
> + priv->clk = clk;
> + spin_lock_init(>cmdreg_lock);
> +
> + platform_set_drvdata(pdev, dev);
> + SET_NETDEV_DEV(dev, >dev);
> +
> + err = register_candev(dev);
> + if (err) {
> + dev_err(>dev, "registering %s failed (err=%d)\n",
> + DRV_NAME, err);
> + goto exit_free;
> + }
> + devm_can_led_init(dev);
> +
> + dev_info(>dev, "device registered (base=%p, irq=%d)\n",
> + priv->base, dev->irq);
> +
> + return 0;
> +
> +exit_free:
> + free_candev(dev);
> +exit:
> + return err;
> +}
> +
> +static struct platform_driver sunxi_can_driver = {
> + .driver = {
> + .name = DRV_NAME,
> + .of_match_table = sunxican_of_match,
> + },
> + .probe = sunxican_probe,
> + .remove = sunxican_remove,
> +};
> +
> +module_platform_driver(sunxi_can_driver);
> +
> +MODULE_AUTHOR("Peter Chen <xingkon...@gmail.com>");
> +MODULE_AUTHOR("Gerhard Bertelsmann <i...@gerhard-bertelsmann.de>");
> +MODULE_LICENSE("Dual BSD/GPL");
> +MODULE_DESCRIPTION(DRV_NAME "CAN driver for Allwinner SoCs (A10/A20)");
Looks good otherwise!
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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tion = "can";
> > + allwinner,drive = <0>;
> > + allwinner,pull = <0>;
> > + };
> > +
> > + can0: can 01c2bc00 {
>
> can0@01c2bc00
Actually, beside '' vs '@', he was right.
The name of the node in the DT sh
On Mon, Aug 24, 2015 at 11:17:43AM +0200, Hans de Goede wrote:
Hi,
On 24-08-15 09:46, Maxime Ripard wrote:
Hi Hans,
On Sun, Aug 23, 2015 at 08:31:38PM +0200, Hans de Goede wrote:
Claim the emac sram ourselves, rather then relying on the bootloader
having mapped the sram to the emac
)
clk_prepare_enable(db-clk);
+ ret = sunxi_sram_claim(pdev-dev);
+ if (ret) {
+ dev_err(pdev-dev, Error couldn't map SRAM to device\n);
+ goto out;
Shouldn't you disable you clock too?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android
On Sun, Jul 05, 2015 at 03:00:11PM +0200, Willy Tarreau wrote:
Hi Thomas,
On Fri, Jul 03, 2015 at 04:46:24PM +0200, Thomas Petazzoni wrote:
Maxime,
On Fri, 3 Jul 2015 16:25:51 +0200, Maxime Ripard wrote:
+static void mvneta_percpu_enable(void *arg)
+{
+ struct mvneta_port
Hi Willy,
On Sun, Jul 05, 2015 at 02:37:08PM +0200, Willy Tarreau wrote:
Hi Maxime,
On Fri, Jul 03, 2015 at 04:25:49PM +0200, Maxime Ripard wrote:
Now that our interrupt controller is allowing us to use per-CPU interrupts,
actually use it in the mvneta driver.
This involves obviously
or not.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/irqchip/irq-armada-370-xp.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-armada-370-xp.c
b/drivers/irqchip/irq-armada-370-xp.c
index daccc8bdbb42..42c69bd95bf8 100644
1 - 100 of 106 matches
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