he coalesce frames
> to 25.
>
> Tested in B2B setup between XGMAC2 and GMAC5.
I will run a test today,
Thanks,
Neil
>
> Signed-off-by: Jose Abreu
> Cc: Florian Fainelli
> Cc: Neil Armstrong
> Cc: Jerome Brunet
> Cc: Martin Blumenstingl
> Cc: David S. Miller
Hi Jose,
On 11/09/2018 10:17, Jose Abreu wrote:
> On 10-09-2018 19:15, Neil Armstrong wrote:
>>
>> RX is still ok but now TX fails almost immediately...
>>
>> With 100ms report :
>>
>> $ iperf3 -c 192.168.1.47 -t 0 -p 5202 -R -i 0.1
>> Connecting to
Hi Jose,
On 10/09/2018 18:21, Jose Abreu wrote:
> On 10-09-2018 16:49, Neil Armstrong wrote:
>> Hi Jose,
>>
>> On 10/09/2018 16:44, Jose Abreu wrote:
>>> On 10-09-2018 14:46, Neil Armstrong wrote:
>>>> hi Jose,
>>>>
>>>> On 10/09/2
Hi Jose,
On 10/09/2018 16:44, Jose Abreu wrote:
> On 10-09-2018 14:46, Neil Armstrong wrote:
>> hi Jose,
>>
>> On 10/09/2018 14:55, Jose Abreu wrote:
>>> On 10-09-2018 13:52, Jose Abreu wrote:
>>>> Can you please try attached follow-up patch ?
>&
hi Jose,
On 10/09/2018 14:55, Jose Abreu wrote:
> On 10-09-2018 13:52, Jose Abreu wrote:
>>
>> Can you please try attached follow-up patch ?
>
> Oh, please apply the whole series otherwise this will not apply
> cleanly.
Indeed, it helps!
With the fixups, it fails later, around 15s instead of
Hi Jose,
On 10/09/2018 11:14, Jose Abreu wrote:
> This follows David Miller advice and tries to fix coalesce timer in
> multi-queue scenarios.
>
> We are now using per-queue coalesce values and per-queue TX timer.
>
> Coalesce timer default values was changed to 1ms and the coalesce frames
> to
On 07/12/2017 16:46, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:10PM +0100, Jerome Brunet wrote:
>> Add read and write helpers to manipulate banked registers on this PHY
>> This helps clarify the settings applied to these registers in the init
>> function and upcoming changes.
>>
>>
"eth_rxd1_y",
> +"eth_rxd2_rgmii",
> + "eth_rxd3_rgmii",
> +"eth_rgmii_tx_clk",
> +"eth_txen_y",
> +"eth_txd0_y",
> +"eth_txd1_y",
> +"eth_txd2_rgmii",
> +"eth_txd3_rgmii";
> + function = "eth";
> + };
> + };
> };
> };
>
>
Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
{
> int v;
>
> - v = of_mdio_parse_addr(dev, child_bus_node);
> - if (v < 0) {
> + r = of_property_read_u32(child_bus_node, "reg", );
> + if (r) {
> dev_err(dev,
>
On 01/02/2017 12:56 PM, Johan Hovold wrote:
> These patches fixes of-node and fixed-phydev leaks in the recently added
> dwmac-oxnas driver, and ultimately switches over to using the generic pm
> implementation as the required callbacks are now in place.
>
> Note that this series has only been
t; +++---
> include/dt-bindings/net/mdio.h | 19 +
> include/linux/phy.h| 3 +
> 6 files changed, 114 insertions(+), 9 deletions(-)
> create mode 100644 include/dt-bindings/net/mdio.h
>
Tested using Nexbox A1 (S912) and Amlogic P230 (S905D) devices (DWMAC +
RTL8211F).
Tested-by: Neil Armstrong <narmstr...@baylibre.com>
/1477932987-27871-1-git-send-email-narmstr...@baylibre.com
Neil Armstrong (2):
net: mdio-mux-mmioreg: Add support for 16bit and 32bit register sizes
net: phy: Add Meson GXL Internal PHY driver
.../devicetree/bindings/net/mdio-mux-mmioreg.txt | 4 +-
drivers/net/phy/Kconfig
In order to support PHY switching on Amlogic GXL SoCs, add support for
16bit and 32bit registers sizes.
Reviewed-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../devicetree/bindings/net/mdio-mux-mmioreg.txt | 4 +-
drivers/net/
until clarification about these registers names and
registers fields are provided by Amlogic.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/phy/Kconfig | 5 +++
drivers/net/phy/Makefile| 1 +
drivers/net/phy/meson-gxl.
On 10/31/2016 05:56 PM, Neil Armstrong wrote:
> The Amlogic Meson GXL SoCs have an internal RMII PHY that is muxed with the
> external RGMII pins.
>
> In order to support switching between the two PHYs links, extended registers
> size for mdio-mux-mmioreg must be added.
>
>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../devicetree/bindings/net/oxnas-dwmac.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/oxnas-dwmac.txt
diff --git a/Documentation/devicetree/bi
Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
Acked-by: Joachim Eastwood <manab...@gmail.com>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
drivers/net/ethernet/stmicro/stm
://patchwork.kernel.org/patch/9387257 :
- Drop init/exit callbacks
- Implement proper remove and PM callback
- Call init from probe
- Disable/Unprepare clock if stmmac probe fails
Neil Armstrong (2):
net: stmmac: Add OXNAS Glue Driver
dt-bindings: net: Add OXNAS DWMAC Bindings
On 10/31/2016 12:12 PM, Joachim Eastwood wrote:
> Hi Neil,
>
> On 31 October 2016 at 11:54, Neil Armstrong <narmstr...@baylibre.com> wrote:
>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>
>> Acked-by: Joachim Eastwood <manab.
On 10/31/2016 08:05 PM, Andrew Lunn wrote:
> On Mon, Oct 31, 2016 at 05:56:24PM +0100, Neil Armstrong wrote:
>> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>>
>> This PHY seems to only implement some standard registers and need some
>> wor
- Add external PHY support for p230
[1]
http://lkml.kernel.org/r/1477932286-27482-1-git-send-email-narmstr...@baylibre.com
[2]
http://lkml.kernel.org/r/1477060838-14164-1-git-send-email-narmstr...@baylibre.com
Neil Armstrong (5):
net: mdio-mux-mmioreg: Add support for 16bit and 32bit register
Enable Ethernet on the p23x board, pinctrl attribute is only added for
the p230 board since the p231 only uses the Internal PHY.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 16
arch/arm64/boot/dts/a
In order to support PHY switching on Amlogic GXL SoCs, add support for
16bit and 32bit registers sizes.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../devicetree/bindings/net/mdio-mux-mmioreg.txt | 4 +-
drivers/net/phy/mdio-mux-mmioreg.c
Add Ethernet node with Internal PHY selection for the Amlogic GXL SoCs
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 45 ++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
index 07f0e0b..08237ee
until clarification about these registers names and
registers fields are provided by Amlogic.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/phy/Kconfig | 5 +++
drivers/net/phy/Makefile| 1 +
drivers/net/phy/meson-gxl.
On 10/21/2016 10:56 PM, Florian Fainelli wrote:
> On 10/21/2016 07:40 AM, Neil Armstrong wrote:
>> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>>
>> This PHY seems to only implement some standard registers and need some
>> workarounds to
On 10/21/2016 06:08 PM, Andrew Lunn wrote:
> Hi Neil
>
>> Yes this would be a good idea if we were able to scan the internal
>> and external PHYs at the same time, but with our limited knowledge
>> the values we write in the register seems to switch a mux for the
>> whole RMII and MDIO signals to
if stmmac probe fails
Neil Armstrong (2):
net: stmmac: Add OXNAS Glue Driver
dt-bindings: net: Add OXNAS DWMAC Bindings
.../devicetree/bindings/net/oxnas-dwmac.txt| 39
drivers/net/ethernet/stmicro/stmmac/Kconfig| 11 ++
drivers/net/ethernet/stmicro/stmmac/Makefile
Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
Acked-by: Joachim Eastwood <manab...@gmail.com>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
drivers/net/ethernet/stmicro/stm
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../devicetree/bindings/net/oxnas-dwmac.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/oxnas-dwmac.txt
diff --git a/Documentation/devicetree/bi
On 10/31/2016 11:20 AM, Joachim Eastwood wrote:
> Hi Neil,
>
> On 31 October 2016 at 10:55, Neil Armstrong <narmstr...@baylibre.com> wrote:
>> On 10/30/2016 09:41 PM, Rob Herring wrote:
>>> On Fri, Oct 21, 2016 at 10:44:45AM +0200, Neil Armstrong wrote:
>>>&
On 10/30/2016 09:41 PM, Rob Herring wrote:
> On Fri, Oct 21, 2016 at 10:44:45AM +0200, Neil Armstrong wrote:
>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>
>> Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
>> ---
>
On 10/24/2016 03:03 AM, Linus Walleij wrote:
> On Fri, Oct 21, 2016 at 4:40 PM, Neil Armstrong <narmstr...@baylibre.com>
> wrote:
>
>> Add support for the Amlogic Meson GXL SoC, this is a partially complete
>> definition only based on the Amlogic Vendor tree.
>>
On 10/21/2016 05:54 PM, Andrew Lunn wrote:
> On Fri, Oct 21, 2016 at 04:40:33PM +0200, Neil Armstrong wrote:
>> The Meson GXL dwmac Glue Layer also provides switching between an external
>> PHY
>> and an internal RMII 10/100 PHY.
>> Add a way to setup the correct PHY s
On 10/21/2016 01:53 PM, Giuseppe CAVALLARO wrote:
> Hello
>
> some my minor cents below
>
> On 10/21/2016 12:20 PM, Joachim Eastwood wrote:
>> Hi Neil,
>>
>> On 21 October 2016 at 10:44, Neil Armstrong <narmstr...@baylibre.com> wrote:
>>> Add S
Add support for the Amlogic Meson GXL SoC, this is a partially complete
definition only based on the Amlogic Vendor tree.
This definition differs a lot from the GXBB and needs a separate entry.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../devicetree/bindings/pinctrl
Add pinctrl attribute to p23x uart node.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
b/arch/arm64/boot/dts/a
and clock nodes for GXL
- Adds correct GXL P23X boards uart pinctrl
- Adds the GXL Internal PHY driver
- Add a temporary workaround to select the internal PHY
- Add Ethernet nodes for GXL and the P23X boards
- Add SD/MMC and SDIO WiFi support support for P23X boards
Neil Armstrong (13):
pinctrl
On 10/21/2016 12:20 PM, Joachim Eastwood wrote:
> Hi Neil,
>
> On 21 October 2016 at 10:44, Neil Armstrong <narmstr...@baylibre.com> wrote:
>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>
>> Signed-off-by: Neil A
Move common nodes between GXBB and GXL in to the common GX dtsi.
Leave the clock attributes in the GXBB dtsi for now.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 131 +++
arch/arm64/boot/dts/amlogic/meson-gxb
Add clock node for Amlogic Meson GXL.
The GXBB compatible is retained since the GXBB clock tree is used for now.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/bo
Add Ethernet node with Internal PHY selection for the Amlogic GXL SoCs
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic
Enable Ethernet on the p23x board, pinctrl attribute are not added since
the current setup uses the Internal PHY.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch
Add i2c nodes clock attributes for Amlogic Meson GXL.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
b/arch/arm64/boot/dts/a
Add MMC/SD/SDIO nodes clock attributes for Amlogic Meson GXL.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
b/arch
Add SD/SDIO/MMC nodes and PWM 32768Hz clock configuration to provide
storage and WiFi functionality on the p23x boards.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 112 +
1 file changed, 112 inse
on the registers fields is received from Amlogic.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 25 ++
1 file changed, 25 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drive
Add pinctrl nodes and pin definitions for Amlogic Meson GXL.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 168 +
1 file changed, 168 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.d
until clarification about these registers names and
registers fields are provided by Amlogic.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/phy/Kconfig | 5 ++
drivers/net/phy/Makefile| 1 +
drivers/net/phy/meson-gxl.c
Enable the Infraread Receiver on the p23x board.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
b/arch/arm6
Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../devicetree/bindings/net/oxnas-dwmac.txt| 44 +
drivers/net/ethernet/stmicro/stmmac/Kconfig| 11 ++
drivers/net/ethernet/stmicro/
On 10/20/2016 06:26 PM, Joachim Eastwood wrote:
> Hi Neil,
>
> On 20 October 2016 at 17:54, Neil Armstrong <narmstr...@baylibre.com> wrote:
>> Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
>>
>> Signed-off-by: Neil A
Add Synopsys Designware MAC Glue layer for the Oxford Semiconductor OX820.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
.../devicetree/bindings/net/oxnas-dwmac.txt| 44 ++
drivers/net/ethernet/stmicro/stmmac/Kconfig| 11 ++
drivers/net/ethernet/stmicro/
When configured in fixed link, the DaVinci emac driver sets the
priv->phydev to NULL and further ioctl calls to the phy_mii_ioctl()
causes the kernel to crash.
Cc: Brian Hutchinson <b.hutch...@gmail.com>
Fixes: 1bb6aa56bb38 ("net: davinci_emac: Add support for fixed-link PHY")
c: add pm_runtime support")
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/ti/davinci_emac.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/ti/davinci_emac.c
b/drivers/net/ethernet/ti/davinci_emac.c
index 5d9abed..e9fe3fb 100644
-
upport")
Cc: Brian Hutchinson <b.hutch...@gmail.com>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/ti/davinci_emac.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ethernet/ti/davinci_emac.c
b/drivers/net/ethernet/ti/davinci_e
ts the RX queue before restarting the reception from a clean
> state.
>
> This patch is a rework of an older patch proposed by Neil Armstrong:
> http://patchwork.ozlabs.org/patch/371525/
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
> ---
&
ule removal ")
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
net/dsa/dsa.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
David, Florian, Andrew,
This fix is quite urgent since it breaks all the removal cleanup.
Thanks,
Neil
diff --git a/net/dsa
ret, slave_dev->name);
>> -phy_disconnect(p->phy);
>> ds->ports[port] = NULL;
>> free_netdev(slave_dev);
>> return ret;
>
> I'm adding Neil in the loop, since he did some work similar to this, if
> I'm not mistaken.
>
> Thanks,
> -v
>
He's right, the phy is not yet created in this error path.
Acked-by: Neil Armstrong <narmstr...@baylibre.com>
Thanks Vivien,
Neil
Add NP4 macb SoC variant.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
Documentation/devicetree/bindings/net/macb.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
index 3
platforms.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/cadence/macb.c | 27 +++
drivers/net/ethernet/cadence/macb.h | 1 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/d
:
http://lkml.kernel.org/r/1451900573-22657-1-git-send-email-narmstr...@baylibre.com
v5: switch SoC name to non-generic NP4 name
Neil Armstrong (3):
net: ethernet: cadence-macb: Add disabled usrio caps
net: macb: Add NP4 macb config using USRIO_DISABLED
dt-bindings: net: macb: Add NP4 macb
Declare a new NP4 SoC variant having USRIO_DISABLED as capability bit.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/cadence/macb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/ethernet/c
On 01/04/2016 11:38 AM, Nicolas Ferre wrote:
> Le 04/01/2016 10:42, Neil Armstrong a écrit :
>> static const struct macb_config zynqmp_config = {
>> .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
>> @@ -2801,6 +2806,7 @@ static const struct of_
platforms.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/cadence/macb.c | 27 +++
drivers/net/ethernet/cadence/macb.h | 1 +
2 files changed, 16 insertions(+), 12 deletions(-)
Nicolas,
I post only the first patch of the previo
...@baylibre.com
v3:
http://lkml.kernel.org/r/1451898103-21868-1-git-send-email-narmstr...@baylibre.com
v4: as nicolas suggested, use a new macb config and a new product/vendor prefix
Neil Armstrong (3):
net: ethernet: cadence-macb: Add disabled usrio caps
net: macb: Add NPx macb config using
platforms.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/cadence/macb.c | 27 +++
drivers/net/ethernet/cadence/macb.h | 1 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/d
Declare a new SoC variant for NPx SoCs having USRIO_DISABLED as
capability bit.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/cadence/macb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/drivers/net/et
Add NPx macb variant for NPx SoCs.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
Documentation/devicetree/bindings/net/macb.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
Hi Josh,
2015-12-07 20:32 GMT+01:00 Josh Cartwright <jo...@ni.com>:
> On Mon, Dec 07, 2015 at 11:58:33AM +0100, Neil Armstrong wrote:
>> On some platforms, the macb integration does not use the USRIO
>> register to configure the (R)MII port and clocks.
>> When the
Add 1:1 mapping of software defines caps parsing from DT in case the
generic macb compatible form is used.
These properties will provide support for futures implementations
only defined from DT without need to update the driver code to support
new variants.
Signed-off-by: Neil Armstrong <narm
platforms.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/ethernet/cadence/macb.c | 27 +++
drivers/net/ethernet/cadence/macb.h | 1 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.c
b/d
software CAPS_* as DT properties
Neil Armstrong (3):
net: ethernet: cadence-macb: Add disabled usrio caps
net: ethernet: cadence-macb: Add fallback to read DT provided caps
bindings: ethernet: macb: Add optional caps properties
Documentation/devicetree/bindings/net/macb.txt | 10
Add generic caps properties to the binding in order to support
future macb/gem implementations with the generic macb compatible form.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
Documentation/devicetree/bindings/net/macb.txt | 10 ++
1 file changed, 10 insertions(+)
On some platforms, the macb integration does not use the USRIO
register to configure the (R)MII port and clocks.
When the register is not implemented and the MACB error signal
is connected to the bus error, reading or writing to the USRIO
register can trigger some Imprecise External Aborts on ARM
This patchet introduces an optional DT property to disable usage of the
USRIO register on platform not implementing it thus avaiding some external
impresise aborts of ARM based platforms.
Neil Armstrong (2):
net: cadence: macb: Disable USRIO register on some platforms
bindings: net: macb: add
Add the no-usrio optional property to disable usage of the USRIO
register on platforms not implementing it.
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
On 10/29/2015 03:45 PM, Neil Armstrong wrote:
> Introduce a new remove callback to allow DSA drivers to cleanup their
> ressources.
> Then add a remove implementation for bcm_sf2 and mv88e6xxx.
>
> This patch was not tested due of a lack of hardware.
>
> v2: add
Upon probe failure or unbinding, add missing dev_put() calls.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
net/dsa/dsa.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index d9e0172..d22d303e 100644
--- a/net/dsa/dsa.c
Move dsa slave dedicated code from dsa_switch_destroy to a new
dsa_slave_destroy function in slave.c.
Add the netif_carrier_off and phy_disconnect calls in order to
correctly cleanup the netdev state and PHY state machine.
Signed-off-by: Frode Isaksen <fisak...@baylibre.com>
Signed-off-by
Make sure that we unassign the master_netdev dsa_ptr to make the packet
processing go through the regular Ethernet receive path.
Suggested-by: Florian Fainelli <f.faine...@gmail.com>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
net/dsa/dsa.c | 8
1 fil
Since no more DSA driver uses the polling callback, and since
the phylib handles the link detection, remove the link polling
work and timer code.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
include/net/dsa.h | 12
net/dsa/dsa.c
://lkml.kernel.org/r/562f8ecb.6050...@baylibre.com
v2: http://lkml.kernel.org/r/56321d9a.8010...@baylibre.com
remove phy fix and add missing calls in dsa_switch_destroy
then add dedicated dsa_slave_destroy
v3: remove polling instead of fixing it, make single patch for
dsa slave destroy
Neil Armstrong (4
Hi Andrew,
On 11/19/2015 12:29 AM, Andrew Lunn wrote:
> + gpio = of_get_named_gpio_flags(child, "reset-gpios", 0,
> +);
> + if (gpio_is_valid(gpio)) {
> + ret = devm_gpio_request_one(dev, gpio, flags,
> +
On 11/10/2015 05:14 PM, Andrew Lunn wrote:
> On Tue, Nov 10, 2015 at 04:51:09PM +0100, Neil Armstrong wrote:
>> This patchset introduces some fixes and a registers addressing cleanup for
>> the mv88e6060 DSA driver.
>
> Hi Neil
>
> It is normal for netdev to put into t
.
v2: cleanup InitReady patch, add missing Acked-by and fix header copyright
notice
Neil Armstrong (6):
net: dsa: mv88e6060: remove poll_link callback
net: dsa: mv88e6060: use the correct InitReady bit
net: dsa: mv88e6060: use the correct MaxFrameSize bit
net: dsa: mv88e6060: use
According to the mv88e6060 datasheet, the InitReady bit position
is 11 and the polarity is inverted.
Use the bit correctly to detect the end of initialization.
Acked-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv88e6060
According to the mv88e6060 datasheet, the MaxFrameSize bit position
is 10 instead of 11 which is reserved.
Use the bit correctly to setup max frame size to 1536.
Acked-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv8
As of mv88e6xxx remove the poll_link callback since the link
state change polling is now handled by the phylib.
Tested on a mv88e6060 B0 device with a TI DM816X SoC.
Suggested-by: Andrew Lunn <and...@lunn.ch>
Acked-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Neil Armstr
.ch>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv88e6060.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c
index 10647ad..cd08079 100644
--- a/drivers/net/dsa/mv88e6060.c
+++ b/dri
To align with the mv88e6xxx code, add a similar header file
with all the register defines.
The file is based on the mv88e6xxx header for coherency.
Acked-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv88e
To align with the mv88e6xxx code, use the register defines to
access all the register addresses and bit fields.
Acked-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv88e6060.c | 64 ++--
On 11/10/2015 03:25 PM, Vivien Didelot wrote:
> Hi Neil,
>
> On Nov. Tuesday 10 (46) 02:25 PM, Neil Armstrong wrote:
>> To align with the mv88e6xxx code, add a similar header file
>> with all the register defines.
>> The file is based on the mv88e6xxx header for
As of mv88e6xxx remove the poll_link callback since the link
state change polling is now handled by the phylib.
Tested on a mv88e6060 B0 device with a TI DM816X SoC.
Suggested-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/d
.
Neil Armstrong (6):
net: dsa: mv88e6060: remove poll_link callback
net: dsa: mv88e6060: use the correct InitReady bit
net: dsa: mv88e6060: use the correct MaxFrameSize bit
net: dsa: mv88e6060: use the correct bit shift for mac0
net: dsa: mv88e6060: add register defines header file
net
To align with the mv88e6xxx code, use the register defines to
access all the register addresses and bit fields.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv88e6060.c | 64 ++---
1 file changed, 37 insertions(
According to the mv88e6060 datasheet, the MaxFrameSize bit position
is 10 instead of 11 which is reserved.
Use the bit correctly to setup max frame size to 1536.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv88e6060.c | 2 +-
1 file changed, 1 insertion
According to the mv88e6060 datasheet, the first mac byte must
be at position 9 instead of 8 since the bit 8 is used to select
if the mac address must differ for each port for Pause frames.
Use the correct shift and set the same mac address for all port.
Signed-off-by: Neil Armstrong <narm
According to the mv88e6060 datasheet, the InitReady bit position
is 11 and the polarity is inverted.
Use the bit correctly to detect the end of initialization.
Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
drivers/net/dsa/mv88e6060.c | 2 +-
1 file changed, 1 insertion
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