On 09/11/2018 12:01 AM, Rob Herring wrote:
> On Sun, Sep 09, 2018 at 10:20:27PM +0200, Hauke Mehrtens wrote:
>> This adds the binding for the GSWIP (Gigabit switch) core found in the
>> xrx200 / VR9 Lantiq / Intel SoC.
>>
>> This part takes care of the switch, MDIO bus, and loading the FW into
>>
On Mon, Sep 10, 2018 at 5:05 PM Andrew Lunn wrote:
>
> > > +See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
> > > +additional required and optional properties.
> > > +
> > > +
>
> snip
>
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible =
> > +See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
> > +additional required and optional properties.
> > +
> > +
snip
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "lantiq,xrx200-gswip";
> > + reg = < 0xE108000 0x3000 /* switch */
> > +
On Sun, Sep 09, 2018 at 10:20:27PM +0200, Hauke Mehrtens wrote:
> This adds the binding for the GSWIP (Gigabit switch) core found in the
> xrx200 / VR9 Lantiq / Intel SoC.
>
> This part takes care of the switch, MDIO bus, and loading the FW into
> the embedded GPHYs.
>
> Signed-off-by: Hauke
This adds the binding for the GSWIP (Gigabit switch) core found in the
xrx200 / VR9 Lantiq / Intel SoC.
This part takes care of the switch, MDIO bus, and loading the FW into
the embedded GPHYs.
Signed-off-by: Hauke Mehrtens
Cc: devicet...@vger.kernel.org
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