Hello Giuseppe,
On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:
> I tested the SMSC on other platform (+ stmmac), not on SPEAr.
>
> ok for reset, keep the radar on clock. Hmm, can you attach a piece of
> log file to see the failure?
We finally identified the issue: in a MII
Viresh, Shiraz,
As the SPEAr600 platform maintainers, have you tested Ethernet in
recent times, especially with a MII PHY ? I'm still struggling to get
it working. Quick summary:
- The same kernel works fine on another SPEAr600 platform that has a
GMII PHY
- The SPEAr600 platform with a
Hello,
Thanks again for your answer, sorry for the delay, I was away from the
spear600 board for a while.
On Mon, 3 Apr 2017 08:16:50 +0200, Giuseppe CAVALLARO wrote:
> I tested the SMSC on other platform (+ stmmac), not on SPEAr.
OK. But I believe there might be a SPEAr specific issue here,
Hi Thomas
I tested the SMSC on other platform (+ stmmac), not on SPEAr.
ok for reset, keep the radar on clock. Hmm, can you attach a piece of
log file to see the failure?
Regards
Peppe
On 4/2/2017 11:30 PM, Thomas Petazzoni wrote:
Hello,
On Thu, 23 Mar 2017 11:33:23 +0100, Giuseppe
Hello,
On Thu, 23 Mar 2017 11:33:23 +0100, Giuseppe CAVALLARO wrote:
> > Further research has revealed that everything is working fine on a
> > platform with a Gigabit PHY connected via GMII.
> >
> > However, on a different platform (which I'm using) with a 10/100 PHY
> > connected via MII,
Hello Thomas
On 3/21/2017 3:50 PM, Thomas Petazzoni wrote:
Hello,
On Thu, 9 Mar 2017 15:56:31 +0100, Giuseppe CAVALLARO wrote:
On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
that never clears, contrary to what the
Hello,
On Thu, 9 Mar 2017 15:56:31 +0100, Giuseppe CAVALLARO wrote:
> On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
>
> > OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
> > that never clears, contrary to what the datasheet says. Are there some
> > erratas?
>
> I
Hello Thomas
On 3/9/2017 10:32 AM, Thomas Petazzoni wrote:
OK, I'll have a look. However, I'm still confused by this DMA_RESET bit
that never clears, contrary to what the datasheet says. Are there some
erratas?
I suggest you to take a look at the tx/rx clocks from PHY.
You have to provide
Hello Giuseppe,
Thanks for your answer.
On Thu, 9 Mar 2017 10:09:02 +0100, Giuseppe CAVALLARO wrote:
> We do not test stmmac on this spear board since many years
> and I guess you have to provide parameters from the platform.
Ok, that's what I was afraid of :-/
> In fact, stmmac is recently
On 09-03-17, 10:09, Giuseppe CAVALLARO wrote:
> Hello
>
> We do not test stmmac on this spear board since many years
> and I guess you have to provide parameters from the platform.
> In fact, stmmac is recently tested with DT.
> IIRC, the mac on spear600 could not have the HW cap register
> so it
Hello
We do not test stmmac on this spear board since many years
and I guess you have to provide parameters from the platform.
In fact, stmmac is recently tested with DT.
IIRC, the mac on spear600 could not have the HW cap register
so it is mandatory to provide all the right parameters and
11 matches
Mail list logo