Re: [PATCH v7 02/37] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU

[Greentime Hu]

2018-02-21 19:37 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Wed, Feb 21, 2018 at 12:21 PM, Greentime Hu <green...@gmail.com> wrote:
>> 2018-02-16 18:47 GMT+08:00 kbuild test robot <l...@intel.com>:
>
>>
>> From: Greentime Hu <greent...@andestech.com>
>> Date: Wed, 21 Feb 2018 14:21:23 +0800
>> Subject: [PATCH] xtensa: add ioremap_nocache declaration before include
>>  asm-generic/io.h.
>>
>> A future commit for the nds32 architecture bootstrap("asm-generic/io.h:
>> move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
>> CONFIG_MMU") will move the ioremap_nocache out of the CONFIG_MMU ifdef.
>> This means that in order to suppress re-definition errors we need to
>> setup #define's before importing asm-generic/io.h.
>>
>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>
> Don't you need to override both ioremap and ioremap_nocache?

Hi, Arnd:

It can fix the building error to override ioremap_nocache.
Why should I override ioremap?

Do you mean remove this implementation
"
static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
{
return ioremap_nocache(offset, size);
}
"
and replace it with
#define ioremap ioremap_nocache

Because I think this patch is just used to fix the build error.
Thank you.

>> ---
>>  arch/xtensa/include/asm/io.h | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
>> index c38e5a732d86..acc5bb2cf1c7 100644
>> --- a/arch/xtensa/include/asm/io.h
>> +++ b/arch/xtensa/include/asm/io.h
>> @@ -52,6 +52,7 @@ static inline void __iomem *ioremap_cache(unsigned
>> long offset,
>> return xtensa_ioremap_cache(offset, size);
>>  }
>>  #define ioremap_cache ioremap_cache
>> +#define ioremap_nocache ioremap_nocache
>>
>>  #define ioremap_wc ioremap_nocache

Re: [PATCH v7 02/37] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU

[Greentime Hu]

2018-02-16 18:47 GMT+08:00 kbuild test robot <l...@intel.com>:
> Hi Greentime,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.16-rc1 next-20180216]
> [if your patch is applied to the wrong git tree, please drop us a note to 
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Greentime-Hu/Andes-nds32-Linux-Kernel-Port/20180216-155013
> config: xtensa-allmodconfig (attached as .config)
> compiler: xtensa-linux-gcc (GCC) 7.2.0
> reproduce:
> wget 
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=xtensa
>
> All error/warnings (new ones prefixed by >>):
>
>In file included from 
> /kbuild/src/consumer/arch/xtensa/include/asm/io.h:82:0,
> from /kbuild/src/consumer/include/linux/io.h:25,
> from 
> /kbuild/src/consumer/drivers//staging/comedi/drivers/comedi_8254.c:118:
>>> /kbuild/src/consumer/include/asm-generic/io.h:864:15: error: conflicting 
>>> types for 'ioremap'
> void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
>   ^~~
>In file included from /kbuild/src/consumer/include/linux/io.h:25:0,
> from 
> /kbuild/src/consumer/drivers//staging/comedi/drivers/comedi_8254.c:118:
>/kbuild/src/consumer/arch/xtensa/include/asm/io.h:59:29: note: previous 
> definition of 'ioremap' was here
> static inline void __iomem *ioremap(unsigned long offset, unsigned long 
> size)
> ^~~
>In file included from 
> /kbuild/src/consumer/arch/xtensa/include/asm/io.h:82:0,
> from /kbuild/src/consumer/include/linux/io.h:25,
> from 
> /kbuild/src/consumer/drivers//staging/comedi/drivers/comedi_8254.c:118:
>>> /kbuild/src/consumer/include/asm-generic/io.h:865:25: error: conflicting 
>>> types for 'ioremap_nocache'
> #define ioremap_nocache ioremap_nocache
> ^
>>> /kbuild/src/consumer/include/asm-generic/io.h:866:29: note: in expansion of 
>>> macro 'ioremap_nocache'
> static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t 
> size)
> ^~~
>In file included from /kbuild/src/consumer/include/linux/io.h:25:0,
> from 
> /kbuild/src/consumer/drivers//staging/comedi/drivers/comedi_8254.c:118:
>/kbuild/src/consumer/arch/xtensa/include/asm/io.h:35:29: note: previous 
> definition of 'ioremap_nocache' was here
> static inline void __iomem *ioremap_nocache(unsigned long offset,
> ^~~
> --
>In file included from 
> /kbuild/src/consumer/arch/xtensa/include/asm/io.h:82:0,
> from /kbuild/src/consumer/include/linux/io.h:25,
> from /kbuild/src/consumer/include/linux/irq.h:25,
> from 
> /kbuild/src/consumer/include/asm-generic/hardirq.h:13,
> from ./arch/xtensa/include/generated/asm/hardirq.h:1,
> from /kbuild/src/consumer/include/linux/hardirq.h:9,
> from /kbuild/src/consumer/include/linux/interrupt.h:13,
> from 
> /kbuild/src/consumer/drivers//scsi/sym53c8xx_2/sym_glue.h:45,
> from 
> /kbuild/src/consumer/drivers//scsi/sym53c8xx_2/sym_fw.c:40:
>>> /kbuild/src/consumer/include/asm-generic/io.h:864:15: error: conflicting 
>>> types for 'ioremap'
> void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
>   ^~~
>In file included from /kbuild/src/consumer/include/linux/io.h:25:0,
> from /kbuild/src/consumer/include/linux/irq.h:25,
> from 
> /kbuild/src/consumer/include/asm-generic/hardirq.h:13,
> from ./arch/xtensa/include/generated/asm/hardirq.h:1,
> from /kbuild/src/consumer/include/linux/hardirq.h:9,
> from /kbuild/src/consumer/include/linux/interrupt.h:13,
> from 
> /kbuild/src/consumer/drivers//scsi/sym53c8xx_2/sym_glue.h:45,
> from 
> /kbuild/src/consumer/drivers//scsi/sym53c8xx_2/sym_fw.c:40:
>/kbuild/src/consumer/arch/xtensa/include/asm/io.h:59:29: note: previous 
> definition of 'ioremap' was here
> static inline void __iomem *ioremap(unsigned long offset, unsigned long 
> size)
> ^~~
>I

Re: [PATCH v7 03/37] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

[Greentime Hu]

2018-02-14 22:43 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Tue, Feb 13, 2018 at 10:09 AM, Greentime Hu <green...@gmail.com> wrote:
>> A commit for the nds32 architecture bootstrap("asm-generic/io.h: move
>> ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU")
>> will move the ioremap_nocache out of the CONFIG_MMU ifdef. This means that
>> in order to suppress re-definition errors we need to remove the #define
>> in io_32.h.
>>
>> Also, the change adds a prototype for ioremap where size is size_t and
>> offset is phys_addr_t so fix that as well.
>>
>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>
> This patch should have been addressed to the sparclinux mailing list to
> the maintainers can see it, otherwise they are unlikely to notice.
>
> Added it to Cc now.
>
> Can you confirm that the patches are ordered correctly in your series so that
> at no point, sparc is in a state that fails to be build cleanly?
>
> If not, this may have to get merged into the other patch.

Hi, Arnd:

These 2 patch will cause sparc building error in any order.

commit af84603e339a6832052071aca1f2a16b8963cc2e
Author: Greentime Hu <green...@gmail.com>
Date:   Tue Feb 13 17:09:07 2018 +0800

sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

A commit for the nds32 architecture bootstrap("asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
CONFIG_MMU")
will move the ioremap_nocache out of the CONFIG_MMU ifdef. This means that
in order to suppress re-definition errors we need to remove the #define
in io_32.h.

Also, the change adds a prototype for ioremap where size is size_t and
offset is phys_addr_t so fix that as well.

Signed-off-by: Greentime Hu <greent...@andestech.com>

commit 1995b30ea6628b261192662741940c22ac978884
Author: Greentime Hu <green...@gmail.com>
Date:   Tue Feb 13 17:09:06 2018 +0800

asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
CONFIG_MMU

It allows some architectures to use this generic macro instead of
defining theirs.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>

Should I merge them together like this?

asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of
ifndef CONFIG_MMU

It allows some architectures to use this generic macro instead of
defining theirs.

sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h
It will move the ioremap_nocache out of the CONFIG_MMU ifdef. This means that
in order to suppress re-definition errors we need to remove the #define
in arch/sparc/include/asm/io_32.h. Also, the change adds a prototype for
ioremap where size is size_t and offset is phys_addr_t so fix that as well.

Signed-off-by: Greentime Hu <greent...@andestech.com>

Re: [PATCH v7 31/37] MAINTAINERS: Add nds32

[Greentime Hu]

2018-02-14 0:02 GMT+08:00 Joe Perches <j...@perches.com>:
> On Tue, 2018-02-13 at 17:09 +0800, Greentime Hu wrote:
>> Add a maintainer information for the nds32(Andes) architecture.
> []
>> diff --git a/MAINTAINERS b/MAINTAINERS
> []
>> @@ -868,6 +868,17 @@ X:   drivers/iio/*/adjd*
>>  F:   drivers/staging/iio/*/ad*
>>  F:   drivers/staging/iio/trigger/iio-trig-bfin-timer.c
>>
>> +ANDES ARCHITECTURE
>> +M:   Greentime Hu <green...@gmail.com>
>> +M:   Vincent Chen <deanbo...@gmail.com>
>> +T:   git https://github.com/andestech/linux.git
>> +S:   Supported
>> +F:   arch/nds32
>
> This should have a trailing /
>
> F:  arch/nds32/

Thank you Joe.
I will add this trailing /
>
>> +F:   
>> Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
>> +F:   Documentation/devicetree/bindings/nds32

And here

>> +K:   nds32
>
> Perhaps this should be
>
> K:  \bnds32
>
> as there are some existing uses of nds32 in the current tree.
>
> or maybe case insensitive like
>
> K:  (?i:\bnds32)
> or
> K:  (?:\bnds32|\bNDS32)
>

I think it might be better to keep it "nds32" becaue some intrinsic
functions are defined with __nds32__xxx.

[PATCH v7 00/37] Andes(nds32) Linux Kernel Port

[Greentime Hu]

s
 - Select NO_BOOTMEM and delete HAVE_MEMBLOCK_NODE_MAP
 - make CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN are dependent
 - Add cpu type to select HWZOL/CPU_CACHE_ALIASING
 - Change CPU_CACHE_NONALIASING to CPU_CACHE_ALIASING
 - Remove bootarg from device tree script
 - Update ag101p.dts and ae3xx.dts for correct board name.
 - Clear and simplify defconfig
 - Implement L2C_R_REG/ L2C_W_REG with readl/writel instead of 
__raw_readl/__raw_writel for endian save
 - Remove early_init_dt_add_memory_arch/early_init_dt_alloc_memory_arch to use 
the generic ones
 - Refine devicetree.c
 - Fix bug https://lkml.kernel.org/r/1499782590-31366-1-git-send-ema...
 - Refine irqchip/irq-ativic32.c implementations
 - Add COMPILE_TEST in drivers/net/ethernet/faraday/Kconfig
 - Refine cache operations
 - Add CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
 - Fix ZERO_PAGE define
 - Remove SA_RESTORER
 - Remove uapi/asm/signal.h
 - Redefine user_pt_regs
 - Remove spinlock.h
 - Remove __ARCH_WANT_RENAMEAT and __ARCH_WANT_SYSCALL_OFF_T from unistd.h
 - Remove set_fs(USER_DS) because flush_old_exec() will do this setting
 - Replace in_atomic() with faulthandler_disabled()
 - Add barrier.h
 - Select COMMON_CLK
 - Add clk_pll in dts
 - Add of_clk_init() in arch/nds32/kernel/time.c

Changes in v2:
 - Set GENERIC_CALIBRATE_DELAY default n
 - Add earlycon support
 - Remove earlyprintk
 - Add CPU_BIG_ENDIAN, CPU_LITTLE_ENDIAN support
 - Refine unalignment access exception handler
 - Add VMSPLIT support
 - Use only one defconfig
 - Change interrupt-cells from 2 to 1
 - Refine andestech cpu names in bindings/nds32/cpus.txt
 - Get clock frequency in dts because fpga bitmap doesn't include this feature
 - Update MAINTAINERS for bindings
 - Remove unused configs in Kconfig
 - Refine device tree scripts
 - Refine coding style
 - Use generic ioremap_nocache
 - Remove L2CC_PA_BASE define and its codes in head.S. It will be moved to 
bootloader.
 - Set PHYS_OFFSET to 0x0 instead of CONFIG_MEMORY_START
 - Remove unused macros
 - Simplify cpu_cache_* API
 - Change __asm__ __volatile__ to asm volatile
 - Refine uaccess.h
 - Remove unused/deprecated syscall
 - Use generic posix_types.h
 - Remove arch_trace_hardirqs_on/arch_trace_hardirqs_off
 - Fix bug of restart syscall
 - Refine syscall implementations
 - Use IS_ENABLED to replace ifdef as possible
 - Remove device_initcall(nds32_device_probe)
 - Refine vdso implementations
 - Refine 
copy_from_user()/copy_to_user()/clear_user()/get_user()/memmove()/memcpy()
 - Refine ioremap.c
 - Refine irq-ativic32.c
 - Fix a bug of earlycon.c
 - Export ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt
 - Add atcpit100 driver


Greentime Hu (37):
  openrisc: add ioremap_nocache declaration before include
asm-generic/io.h and sync ioremap prototype with it.
  asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
CONFIG_MMU
  sparc: io: To use the define of ioremap_[nocache|wc|wb] in
asm-generic/io.h
  earlycon: add reg-offset to physical address before mapping
  drivers/video/concole: add negative dependency for VGA_CONSOLE on
nds32
  nds32: Assembly macros and definitions
  nds32: Kernel booting and initialization
  nds32: Exception handling
  nds32: MMU definitions
  nds32: MMU initialization
  nds32: MMU fault handling and page table management
  nds32: Cache and TLB routines
  nds32: Process management
  nds32: IRQ handling
  nds32: Atomic operations
  nds32: Device specific operations
  nds32: DMA mapping API
  nds32: ELF definitions
  nds32: System calls handling
  nds32: VDSO support
  nds32: Signal handling support
  nds32: Library functions
  nds32: Debugging support
  nds32: L2 cache support
  nds32: Loadable modules
  nds32: Generic timers support
  nds32: Device tree support
  nds32: Miscellaneous header files
  nds32: defconfig
  nds32: Build infrastructure
  MAINTAINERS: Add nds32
  dt-bindings: nds32 CPU Bindings
  dt-bindings: nds32 L2 cache controller Bindings
  dt-bindings: nds32 SoC Bindings
  dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt
Controller
  irqchip: Andestech Internal Vector Interrupt Controller driver
  net: faraday add nds32 support.

 .../interrupt-controller/andestech,ativic32.txt|  19 +
 .../devicetree/bindings/nds32/andestech-boards |  40 +
 Documentation/devicetree/bindings/nds32/atl2c.txt  |  28 +
 Documentation/devicetree/bindings/nds32/cpus.txt   |  38 +
 MAINTAINERS|  11 +
 arch/nds32/Kconfig | 103 +++
 arch/nds32/Kconfig.cpu | 174 
 arch/nds32/Makefile|  66 ++
 arch/nds32/boot/Makefile   |  15 +
 arch/nds32/boot/dts/Makefile   |   8 +
 arch/nds32/boot/dts/ae3xx.dts  |  85 ++
 arch/nds32/configs/defconfig   | 104 +++
 arch/nds32/include/asm/Kbuild  |  55 ++
 a

[PATCH v7 02/37] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU

[Greentime Hu]

It allows some architectures to use this generic macro instead of
defining theirs.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 include/asm-generic/io.h | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b4531e3b2120..7c6a39e64749 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -852,7 +852,16 @@ static inline void __iomem *__ioremap(phys_addr_t offset, 
size_t size,
 }
 #endif
 
+#ifndef iounmap
+#define iounmap iounmap
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+#endif
+#endif /* CONFIG_MMU */
 #ifndef ioremap_nocache
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
 #define ioremap_nocache ioremap_nocache
 static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
 {
@@ -884,15 +893,6 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, 
size_t size)
 }
 #endif
 
-#ifndef iounmap
-#define iounmap iounmap
-
-static inline void iounmap(void __iomem *addr)
-{
-}
-#endif
-#endif /* CONFIG_MMU */
-
 #ifdef CONFIG_HAS_IOPORT_MAP
 #ifndef CONFIG_GENERIC_IOMAP
 #ifndef ioport_map
-- 
2.16.1

[PATCH v7 01/37] openrisc: add ioremap_nocache declaration before include asm-generic/io.h and sync ioremap prototype with it.

[Greentime Hu]

A future commit for the nds32 architecture bootstrap("asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU")
will move the ioremap_nocache out of the CONFIG_MMU ifdef. This means that
in order to suppress re-definition errors we need to setup #define's before
importing asm-generic/io.h.

Also, the change adds a prototype for ioremap where size is size_t so fix that
as well.

Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Stafford Horne <sho...@gmail.com>
---
 arch/openrisc/include/asm/io.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index 7c691399da3f..6709b28a0221 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -29,13 +29,14 @@
 #define PIO_OFFSET 0
 #define PIO_MASK   0
 
+#define ioremap_nocache ioremap_nocache
 #include 
 #include 
 
 extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size,
pgprot_t prot);
 
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
return __ioremap(offset, size, PAGE_KERNEL);
 }
-- 
2.16.1

[PATCH v7 04/37] earlycon: add reg-offset to physical address before mapping

[Greentime Hu]

It will get the wrong virtual address because port->mapbase is not added
the correct reg-offset yet. We have to update it before earlycon_map()
is called

Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
Cc: Peter Hurley <pe...@hurleysoftware.com>
Cc: sta...@vger.kernel.org
Fixes: 088da2a17619 ("of: earlycon: Initialize port fields from DT
properties")
---
 drivers/tty/serial/earlycon.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index 870e84fb6e39..a24278380fec 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -245,11 +245,12 @@ int __init of_setup_earlycon(const struct earlycon_id 
*match,
}
port->mapbase = addr;
port->uartclk = BASE_BAUD * 16;
-   port->membase = earlycon_map(port->mapbase, SZ_4K);
 
val = of_get_flat_dt_prop(node, "reg-offset", NULL);
if (val)
port->mapbase += be32_to_cpu(*val);
+   port->membase = earlycon_map(port->mapbase, SZ_4K);
+
val = of_get_flat_dt_prop(node, "reg-shift", NULL);
if (val)
port->regshift = be32_to_cpu(*val);
-- 
2.16.1

[PATCH v7 03/37] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

[Greentime Hu]

A commit for the nds32 architecture bootstrap("asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU")
will move the ioremap_nocache out of the CONFIG_MMU ifdef. This means that
in order to suppress re-definition errors we need to remove the #define
in io_32.h.

Also, the change adds a prototype for ioremap where size is size_t and
offset is phys_addr_t so fix that as well.

Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/sparc/include/asm/io_32.h | 5 -
 arch/sparc/kernel/ioport.c | 4 ++--
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index cd51a89b393c..df2dc1784673 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -127,12 +127,7 @@ static inline void sbus_memcpy_toio(volatile void __iomem 
*dst,
  * Bus number may be embedded in the higher bits of the physical address.
  * This is why we have no bus number argument to ioremap().
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size);
-#define ioremap_nocache(X,Y)   ioremap((X),(Y))
-#define ioremap_wc(X,Y)ioremap((X),(Y))
-#define ioremap_wt(X,Y)ioremap((X),(Y))
 void iounmap(volatile void __iomem *addr);
-
 /* Create a virtual mapping cookie for an IO port range */
 void __iomem *ioport_map(unsigned long port, unsigned int nr);
 void ioport_unmap(void __iomem *);
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 7eeef80c02f7..3bcef9ce74df 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -122,12 +122,12 @@ static void xres_free(struct xresource *xrp) {
  *
  * Bus type is always zero on IIep.
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size)
+void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
char name[14];
 
sprintf(name, "phys_%08x", (u32)offset);
-   return _sparc_alloc_io(0, offset, size, name);
+   return _sparc_alloc_io(0, (unsigned long)offset, size, name);
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
2.16.1

[PATCH v7 05/37] drivers/video/concole: add negative dependency for VGA_CONSOLE on nds32

[Greentime Hu]

nds32 does not support VGA console, so prevent that kconfig symbol from
being enabled for nds32, thus fixing these build errors:

  drivers/video/console/vgacon.o: In function `vgacon_save_screen':
  
/NOBACKUP/sqa2/greentime/contrib/src_pkg/linux-nds32/drivers/video/console/vgacon.c:1327:
  undefined reference to `screen_info'
  
/NOBACKUP/sqa2/greentime/contrib/src_pkg/linux-nds32/drivers/video/console/vgacon.c:1327:
  undefined reference to `screen_info'
  
/NOBACKUP/sqa2/greentime/contrib/src_pkg/linux-nds32/drivers/video/console/vgacon.c:1328:
  undefined reference to `screen_info'
  
/NOBACKUP/sqa2/greentime/contrib/src_pkg/linux-nds32/drivers/video/console/vgacon.c:1328:
  undefined reference to `screen_info'
  drivers/video/console/vgacon.o: In function `vgacon_init':
  
/NOBACKUP/sqa2/greentime/contrib/src_pkg/linux-nds32/drivers/video/console/vgacon.c:591:
  undefined reference to `screen_info'
  
drivers/video/console/vgacon.o:/NOBACKUP/sqa2/greentime/contrib/src_pkg/linux-nds32/drivers/video/console/vgacon.c:591:
  more undefined references to `screen_info' follow
  make: *** [vmlinux] Error 1

Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 drivers/video/console/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 7f1f1fbcef9e..27bb893cf6b2 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -9,7 +9,7 @@ config VGA_CONSOLE
depends on !4xx && !PPC_8xx && !SPARC && !M68K && !PARISC && !FRV && \
!SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !CRIS && \
(!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) 
&& \
-   !ARM64 && !ARC && !MICROBLAZE && !OPENRISC
+   !ARM64 && !ARC && !MICROBLAZE && !OPENRISC && !NDS32
default y
help
  Saying Y here will allow you to use Linux in text mode through a
-- 
2.16.1

[PATCH v7 06/37] nds32: Assembly macros and definitions

[Greentime Hu]

This patch includes assembly macros, bit field definitions used in .S
files across arch/nds32/.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/assembler.h |  39 ++
 arch/nds32/include/asm/bitfield.h  | 963 +
 arch/nds32/include/asm/nds32.h |  81 
 arch/nds32/kernel/asm-offsets.c|  28 ++
 4 files changed,  insertions(+)
 create mode 100644 arch/nds32/include/asm/assembler.h
 create mode 100644 arch/nds32/include/asm/bitfield.h
 create mode 100644 arch/nds32/include/asm/nds32.h
 create mode 100644 arch/nds32/kernel/asm-offsets.c

diff --git a/arch/nds32/include/asm/assembler.h 
b/arch/nds32/include/asm/assembler.h
new file mode 100644
index ..c3855782a541
--- /dev/null
+++ b/arch/nds32/include/asm/assembler.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASSEMBLER_H__
+#define __NDS32_ASSEMBLER_H__
+
+.macro gie_disable
+   setgie.d
+   dsb
+.endm
+
+.macro gie_enable
+   setgie.e
+   dsb
+.endm
+
+.macro gie_save oldpsw
+   mfsr \oldpsw, $ir0
+   setgie.d
+dsb
+.endm
+
+.macro gie_restore oldpsw
+   andi \oldpsw, \oldpsw, #0x1
+   beqz \oldpsw, 7001f
+   setgie.e
+   dsb
+7001:
+.endm
+
+
+#define USER(insn,  reg, addr, opr)\
+:  insn  reg, addr, opr;   \
+   .section __ex_table,"a";\
+   .align 3;   \
+   .long   b, 9001f;   \
+   .previous
+
+#endif /* __NDS32_ASSEMBLER_H__ */
diff --git a/arch/nds32/include/asm/bitfield.h 
b/arch/nds32/include/asm/bitfield.h
new file mode 100644
index ..c73f71d67744
--- /dev/null
+++ b/arch/nds32/include/asm/bitfield.h
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BITFIELD_H__
+#define __NDS32_BITFIELD_H__
+/**
+ * cr0: CPU_VER (CPU Version Register)
+ */
+#define CPU_VER_offCFGID   0   /* Minor configuration */
+#define CPU_VER_offREV 16  /* Revision of the CPU version */
+#define CPU_VER_offCPUID   24  /* Major CPU versions */
+
+#define CPU_VER_mskCFGID   ( 0x  << CPU_VER_offCFGID )
+#define CPU_VER_mskREV ( 0xFF  << CPU_VER_offREV )
+#define CPU_VER_mskCPUID   ( 0xFF  << CPU_VER_offCPUID )
+
+/**
+ * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
+ */
+#define ICM_CFG_offISET0   /* I-cache sets (# of cache 
lines) per way */
+#define ICM_CFG_offIWAY3   /* I-cache ways */
+#define ICM_CFG_offISZ 6   /* I-cache line size */
+#define ICM_CFG_offILCK9   /* I-cache locking support */
+#define ICM_CFG_offILMB10  /* On-chip ILM banks */
+#define ICM_CFG_offBSAV13  /* ILM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define ICM_CFG_mskISET( 0x7  << ICM_CFG_offISET )
+#define ICM_CFG_mskIWAY( 0x7  << ICM_CFG_offIWAY )
+#define ICM_CFG_mskISZ ( 0x7  << ICM_CFG_offISZ )
+#define ICM_CFG_mskILCK( 0x1  << ICM_CFG_offILCK )
+#define ICM_CFG_mskILMB( 0x7  << ICM_CFG_offILMB )
+#define ICM_CFG_mskBSAV( 0x3  << ICM_CFG_offBSAV )
+
+/**
+ * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
+ */
+#define DCM_CFG_offDSET0   /* D-cache sets (# of cache 
lines) per way */
+#define DCM_CFG_offDWAY3   /* D-cache ways */
+#define DCM_CFG_offDSZ 6   /* D-cache line size */
+#define DCM_CFG_offDLCK9   /* D-cache locking support */
+#define DCM_CFG_offDLMB10  /* On-chip DLM banks */
+#define DCM_CFG_offBSAV13  /* DLM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define DCM_CFG_mskDSET( 0x7  << DCM_CFG_offDSET )
+#define DCM_CFG_mskDWAY( 0x7  << DCM_CFG_offDWAY )
+#define DCM_CFG_mskDSZ ( 0x7  << DCM_CFG_offDSZ )
+#define DCM_CFG_mskDLCK( 0x1  << DCM_CFG_offDLCK )
+#define DCM_CFG_mskDLMB( 0x7  << DCM_CFG_offDLMB )
+#define DCM_CFG_mskBSAV( 0x3 

[PATCH v7 08/37] nds32: Exception handling

[Greentime Hu]

This patch includes the exception/interrupt entries, pt_reg structure and
related accessors.

/* Unaligned accessing handling*/
Andes processors cannot load/store information which is not naturally
aligned on the bus, i.e., loading a 4 byte data whose start address must
be divisible by 4. If unaligned data accessing is happened, data
unaligned exception will be triggered and user will get SIGSEGV or
kernel oops according to the unaligned address. In order to make user be
able to load/store data from an unaligned address, software load/store
emulation is implemented in arch/nds32/mm/alignment.c to address data
unaligned exception.

Unaligned accessing handling is disabled by default because it is not a
normal case. User can enable this feature by following steps.

A. Compile time:
1. Enable kernel config CONFIG_ALIGNMENT_TRAP
B. Run time:
1. Enter /proc/sys/nds32/unaligned_acess folder
2. Write 1 to file enable_mode to enable unaligned accessing
   handling. User can disable it by writing 0 to this file.
3. Write 1 to file debug to show which unaligned address is under
   processing. User can disable it by writing 0 to this file.

However, unaligned accessing handler cannot work if this unaligned
address is not accessible such as protection violation. On this
condition, the default behaviors for addressing data unaligned exception
still happen

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/ptrace.h |  77 ++
 arch/nds32/kernel/ex-entry.S| 157 +++
 arch/nds32/kernel/ex-exit.S | 184 +
 arch/nds32/kernel/stacktrace.c  |  47 
 arch/nds32/kernel/traps.c   | 442 ++
 arch/nds32/mm/alignment.c   | 576 
 6 files changed, 1483 insertions(+)
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ex-entry.S
 create mode 100644 arch/nds32/kernel/ex-exit.S
 create mode 100644 arch/nds32/kernel/stacktrace.c
 create mode 100644 arch/nds32/kernel/traps.c
 create mode 100644 arch/nds32/mm/alignment.c

diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index ..c4538839055c
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PTRACE_H
+#define __ASM_NDS32_PTRACE_H
+
+#include 
+
+/*
+ * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
+ * a syscall -- i.e., its most recent entry into the kernel from
+ * userspace was not via syscall, or otherwise a tracer cancelled the
+ * syscall.
+ *
+ * This must have the value -1, for ABI compatibility with ptrace etc.
+ */
+#define NO_SYSCALL (-1)
+#ifndef __ASSEMBLY__
+#include 
+
+struct pt_regs {
+   union {
+   struct user_pt_regs user_regs;
+   struct {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+#if defined(CONFIG_HWZOL)
+   long lb;
+   long le;
+   long lc;
+#else
+   long dummy[3];
+#endif
+   long syscallno;
+   };
+   };
+   long orig_r0;
+   long ir0;
+   long ipsw;
+   long pipsw;
+   long pipc;
+   long pp0;
+   long pp1;
+   long fucop_ctl;
+   long osp;
+};
+
+static inline bool in_syscall(struct pt_regs const *regs)
+{
+   return regs->syscallno != NO_SYSCALL;
+}
+
+static inline void forget_syscall(struct pt_regs *regs)
+{
+   regs->syscallno = NO_SYSCALL;
+}
+static inline unsigned long regs_return_value(struct pt_regs *regs)
+{
+   return regs->uregs[0];
+}
+extern void show_regs(struct pt_regs *);
+/* Avoid circular header include via sched.h */
+struct task_struct;
+
+#define arch_has_single_step() (1)
+#define user_mode(regs)(((regs)->ipsw & PSW_mskPOM) == 
0)
+#define interrupts_enabled(regs)   (!!((regs)->ipsw & PSW_mskGIE))
+#define user_stack_pointer(regs)   ((regs)->sp)
+#define instruction_pointer(regs)  ((regs)->ipc)
+#define profile_pc(regs)   instruction_pointer(regs)
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S
new file mode 100644
index ..a72e83d804f5
--- /dev/null
+++ b/arch/nds32/kernel/ex-entry.S
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_HWZOL
+   .macro push_zol
+   mfusr   $r14, $LB
+   mfusr   $r15, $L

[PATCH v7 10/37] nds32: MMU initialization

[Greentime Hu]

This patch includes memory initializations and highmem supporting.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/mm/highmem.c  |  79 ++
 arch/nds32/mm/init.c | 277 +++
 arch/nds32/mm/mm-nds32.c |  90 +++
 3 files changed, 446 insertions(+)
 create mode 100644 arch/nds32/mm/highmem.c
 create mode 100644 arch/nds32/mm/init.c
 create mode 100644 arch/nds32/mm/mm-nds32.c

diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
new file mode 100644
index ..e17cb8a69315
--- /dev/null
+++ b/arch/nds32/mm/highmem.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void *kmap(struct page *page)
+{
+   unsigned long vaddr;
+   might_sleep();
+   if (!PageHighMem(page))
+   return page_address(page);
+   vaddr = (unsigned long)kmap_high(page);
+   return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap);
+
+void kunmap(struct page *page)
+{
+   BUG_ON(in_interrupt());
+   if (!PageHighMem(page))
+   return;
+   kunmap_high(page);
+}
+
+EXPORT_SYMBOL(kunmap);
+
+void *kmap_atomic(struct page *page)
+{
+   unsigned int idx;
+   unsigned long vaddr, pte;
+   int type;
+   pte_t *ptep;
+
+   preempt_disable();
+   pagefault_disable();
+   if (!PageHighMem(page))
+   return page_address(page);
+
+   type = kmap_atomic_idx_push();
+
+   idx = type + KM_TYPE_NR * smp_processor_id();
+   vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+   pte = (page_to_pfn(page) << PAGE_SHIFT) | (PAGE_KERNEL);
+   ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+   set_pte(ptep, pte);
+
+   __nds32__tlbop_inv(vaddr);
+   __nds32__mtsr_dsb(vaddr, NDS32_SR_TLB_VPN);
+   __nds32__tlbop_rwr(pte);
+   __nds32__isb();
+   return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap_atomic);
+
+void __kunmap_atomic(void *kvaddr)
+{
+   if (kvaddr >= (void *)FIXADDR_START) {
+   unsigned long vaddr = (unsigned long)kvaddr;
+   pte_t *ptep;
+   kmap_atomic_idx_pop();
+   __nds32__tlbop_inv(vaddr);
+   __nds32__isb();
+   ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+   set_pte(ptep, 0);
+   }
+   pagefault_enable();
+   preempt_enable();
+}
+
+EXPORT_SYMBOL(__kunmap_atomic);
diff --git a/arch/nds32/mm/init.c b/arch/nds32/mm/init.c
new file mode 100644
index ..93ee0160720b
--- /dev/null
+++ b/arch/nds32/mm/init.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 1995-2005 Russell King
+// Copyright (C) 2012 ARM Ltd.
+// Copyright (C) 2013-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+DEFINE_SPINLOCK(anon_alias_lock);
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern unsigned long phys_initrd_start;
+extern unsigned long phys_initrd_size;
+
+/*
+ * empty_zero_page is a special page that is used for
+ * zero-initialized data and COW.
+ */
+struct page *empty_zero_page;
+
+static void __init zone_sizes_init(void)
+{
+   unsigned long zones_size[MAX_NR_ZONES];
+
+   /* Clear the zone sizes */
+   memset(zones_size, 0, sizeof(zones_size));
+
+   zones_size[ZONE_NORMAL] = max_low_pfn;
+#ifdef CONFIG_HIGHMEM
+   zones_size[ZONE_HIGHMEM] = max_pfn;
+#endif
+   free_area_init(zones_size);
+
+}
+
+/*
+ * Map all physical memory under high_memory into kernel's address space.
+ *
+ * This is explicitly coded for two-level page tables, so if you need
+ * something else then this needs to change.
+ */
+static void __init map_ram(void)
+{
+   unsigned long v, p, e;
+   pgd_t *pge;
+   pud_t *pue;
+   pmd_t *pme;
+   pte_t *pte;
+   /* These mark extents of read-only kernel pages...
+* ...from vmlinux.lds.S
+*/
+
+   p = (u32) memblock_start_of_DRAM() & PAGE_MASK;
+   e = min((u32) memblock_end_of_DRAM(), (u32) __pa(high_memory));
+
+   v = (u32) __va(p);
+   pge = pgd_offset_k(v);
+
+   while (p < e) {
+   int j;
+   pue = pud_offset(pge, v);
+   pme = pmd_offset(pue, v);
+
+   if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) {
+   panic("%s: Kernel hardcoded for "
+ "two-level page tables", __func__);
+   }
+
+   /* Alloc one page for holding PTE's... */
+   pte = (pte_t *) __va(membloc

[PATCH v7 12/37] nds32: Cache and TLB routines

[Greentime Hu]

This patch contains cache and TLB maintenance functions.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/cache.h |  12 +
 arch/nds32/include/asm/cache_info.h|  13 +
 arch/nds32/include/asm/cacheflush.h|  44 +++
 arch/nds32/include/asm/mmu_context.h   |  68 +
 arch/nds32/include/asm/proc-fns.h  |  44 +++
 arch/nds32/include/asm/tlb.h   |  28 ++
 arch/nds32/include/asm/tlbflush.h  |  47 +++
 arch/nds32/include/uapi/asm/cachectl.h |  14 +
 arch/nds32/kernel/cacheinfo.c  |  49 +++
 arch/nds32/mm/cacheflush.c | 322 
 arch/nds32/mm/proc.c   | 533 +
 arch/nds32/mm/tlb.c|  50 
 12 files changed, 1224 insertions(+)
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/cache_info.h
 create mode 100644 arch/nds32/include/asm/cacheflush.h
 create mode 100644 arch/nds32/include/asm/mmu_context.h
 create mode 100644 arch/nds32/include/asm/proc-fns.h
 create mode 100644 arch/nds32/include/asm/tlb.h
 create mode 100644 arch/nds32/include/asm/tlbflush.h
 create mode 100644 arch/nds32/include/uapi/asm/cachectl.h
 create mode 100644 arch/nds32/kernel/cacheinfo.c
 create mode 100644 arch/nds32/mm/cacheflush.c
 create mode 100644 arch/nds32/mm/proc.c
 create mode 100644 arch/nds32/mm/tlb.c

diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index ..347db4881c5f
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHE_H__
+#define __NDS32_CACHE_H__
+
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
+
+#define ARCH_DMA_MINALIGN   L1_CACHE_BYTES
+
+#endif /* __NDS32_CACHE_H__ */
diff --git a/arch/nds32/include/asm/cache_info.h 
b/arch/nds32/include/asm/cache_info.h
new file mode 100644
index ..38ec458ba543
--- /dev/null
+++ b/arch/nds32/include/asm/cache_info.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+struct cache_info {
+   unsigned char ways;
+   unsigned char line_size;
+   unsigned short sets;
+   unsigned short size;
+#if defined(CONFIG_CPU_CACHE_ALIASING)
+   unsigned short aliasing_num;
+   unsigned int aliasing_mask;
+#endif
+};
diff --git a/arch/nds32/include/asm/cacheflush.h 
b/arch/nds32/include/asm/cacheflush.h
new file mode 100644
index ..7b9b20a381cb
--- /dev/null
+++ b/arch/nds32/include/asm/cacheflush.h
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHEFLUSH_H__
+#define __NDS32_CACHEFLUSH_H__
+
+#include 
+
+#define PG_dcache_dirty PG_arch_1
+
+#ifdef CONFIG_CPU_CACHE_ALIASING
+void flush_cache_mm(struct mm_struct *mm);
+void flush_cache_dup_mm(struct mm_struct *mm);
+void flush_cache_range(struct vm_area_struct *vma,
+  unsigned long start, unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long pfn);
+void flush_cache_kmaps(void);
+void flush_cache_vmap(unsigned long start, unsigned long end);
+void flush_cache_vunmap(unsigned long start, unsigned long end);
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+void flush_dcache_page(struct page *page);
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+  unsigned long vaddr, void *dst, void *src, int len);
+void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+unsigned long vaddr, void *dst, void *src, int len);
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+void flush_anon_page(struct vm_area_struct *vma,
+struct page *page, unsigned long vaddr);
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+void flush_kernel_dcache_page(struct page *page);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#define flush_dcache_mmap_lock(mapping)   spin_lock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_unlock(mapping) 
spin_unlock_irq(&(mapping)->tree_lock)
+
+#else
+#include 
+#endif
+
+#endif /* __NDS32_CACHEFLUSH_H__ */
diff --git a/arch/nds32/include/asm/mmu_context.h 
b/arch/nds32/include/asm/mmu_context.h
new file mode 100644
index ..fd7d13cefccc
--- /dev/null
+++ b/arch/nds32/include/asm/mmu_context.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MMU_CONTEXT_H
+#define __ASM_NDS32_MMU_CONTEXT_H
+
+#include 
+#include 
+#include 
+#include 
+
+static inline int
+ini

[PATCH v7 14/37] nds32: IRQ handling

[Greentime Hu]

This patch includes irq related functions and irqchip_init().

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/irqflags.h | 36 
 arch/nds32/kernel/irq.c   |  9 +
 2 files changed, 45 insertions(+)
 create mode 100644 arch/nds32/include/asm/irqflags.h
 create mode 100644 arch/nds32/kernel/irq.c

diff --git a/arch/nds32/include/asm/irqflags.h 
b/arch/nds32/include/asm/irqflags.h
new file mode 100644
index ..2bfd00f8bc48
--- /dev/null
+++ b/arch/nds32/include/asm/irqflags.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+#define arch_local_irq_disable()   \
+   GIE_DISABLE();
+
+#define arch_local_irq_enable()\
+   GIE_ENABLE();
+static inline unsigned long arch_local_irq_save(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   GIE_DISABLE();
+   return flags;
+}
+
+static inline unsigned long arch_local_save_flags(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+   if(flags)
+   GIE_ENABLE();
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+   return !flags;
+}
diff --git a/arch/nds32/kernel/irq.c b/arch/nds32/kernel/irq.c
new file mode 100644
index ..6ff5a672be27
--- /dev/null
+++ b/arch/nds32/kernel/irq.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+
+void __init init_IRQ(void)
+{
+   irqchip_init();
+}
-- 
2.16.1

[PATCH v7 13/37] nds32: Process management

[Greentime Hu]

This patch includes copy_thread(), start_thread() implementation and cpu_context
structure definition. nds32 uses $r25 to get current task_struct.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/current.h |  12 ++
 arch/nds32/include/asm/processor.h   | 103 +
 arch/nds32/include/asm/thread_info.h |  76 +
 arch/nds32/kernel/process.c  | 208 +++
 4 files changed, 399 insertions(+)
 create mode 100644 arch/nds32/include/asm/current.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/thread_info.h
 create mode 100644 arch/nds32/kernel/process.c

diff --git a/arch/nds32/include/asm/current.h b/arch/nds32/include/asm/current.h
new file mode 100644
index ..b4dcd22b7bcb
--- /dev/null
+++ b/arch/nds32/include/asm/current.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_CURRENT_H
+#define _ASM_NDS32_CURRENT_H
+
+#ifndef __ASSEMBLY__
+register struct task_struct *current asm("$r25");
+#endif /* __ASSEMBLY__ */
+#define tsk $r25
+
+#endif /* _ASM_NDS32_CURRENT_H */
diff --git a/arch/nds32/include/asm/processor.h 
b/arch/nds32/include/asm/processor.h
new file mode 100644
index ..9c83caf4269f
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PROCESSOR_H
+#define __ASM_NDS32_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#ifdef __KERNEL__
+
+#include 
+#include 
+#include 
+
+#define KERNEL_STACK_SIZE  PAGE_SIZE
+#define STACK_TOP  TASK_SIZE
+#define STACK_TOP_MAX   TASK_SIZE
+
+struct cpu_context {
+   unsigned long r6;
+   unsigned long r7;
+   unsigned long r8;
+   unsigned long r9;
+   unsigned long r10;
+   unsigned long r11;
+   unsigned long r12;
+   unsigned long r13;
+   unsigned long r14;
+   unsigned long fp;
+   unsigned long pc;
+   unsigned long sp;
+};
+
+struct thread_struct {
+   struct cpu_context cpu_context; /* cpu context */
+   /* fault info */
+   unsigned long address;
+   unsigned long trap_no;
+   unsigned long error_code;
+};
+
+#define INIT_THREAD  { }
+
+#ifdef __NDS32_EB__
+#define PSW_DE PSW_mskBE
+#else
+#define PSW_DE 0x0
+#endif
+
+#ifdef CONFIG_WBNA
+#define PSW_valWBNAPSW_mskWBNA
+#else
+#define PSW_valWBNA0x0
+#endif
+
+#ifdef CONFIG_HWZOL
+#definePSW_valINIT (PSW_CPL_ANY | PSW_mskAEN | PSW_valWBNA | PSW_mskDT 
| PSW_mskIT | PSW_DE | PSW_mskGIE)
+#else
+#definePSW_valINIT (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT 
| PSW_DE | PSW_mskGIE)
+#endif
+
+#define start_thread(regs,pc,stack)\
+({ \
+   memzero(regs, sizeof(struct pt_regs));  \
+   forget_syscall(regs);   \
+   regs->ipsw = PSW_valINIT;   \
+   regs->ir0 = (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE 
| PSW_SYSTEM | PSW_INTL_1); \
+   regs->ipc = pc; \
+   regs->sp = stack;   \
+})
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)   do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define cpu_relax()barrier()
+
+#define task_pt_regs(task) \
+   ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+   - 8) - 1)
+
+/*
+ * Create a new kernel thread
+ */
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
+
+#define KSTK_EIP(tsk)  instruction_pointer(task_pt_regs(tsk))
+#define KSTK_ESP(tsk)  user_stack_pointer(task_pt_regs(tsk))
+
+#endif
+
+#endif /* __ASM_NDS32_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/thread_info.h 
b/arch/nds32/include/asm/thread_info.h
new file mode 100644
index ..bff741ff337b
--- /dev/null
+++ b/arch/nds32/include/asm/thread_info.h
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_THREAD_INFO_H
+#define __ASM_NDS32_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#define THREAD_SIZE_ORDER  (1)
+#define THREAD_SIZE(PAGE_SIZE << THREAD_SIZE_ORDER)
+
+#ifndef __ASSEMBLY__
+
+stru

[PATCH v7 16/37] nds32: Device specific operations

[Greentime Hu]

This patch introduces ioremap implementations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/io.h | 83 +
 arch/nds32/mm/ioremap.c | 62 +
 2 files changed, 145 insertions(+)
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/mm/ioremap.c

diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index ..966e71b3c960
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_IO_H
+#define __ASM_NDS32_IO_H
+
+extern void iounmap(volatile void __iomem *addr);
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+   asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+   asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+   asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+   u8 val;
+
+   asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+   u16 val;
+
+   asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+   u32 val;
+
+   asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __iormb()   rmb()
+#define __iowmb()   wmb()
+
+#define mmiowb()__asm__ __volatile__ ("msync all" : : : "memory");
+
+/*
+ * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
+ * are not guaranteed to provide ordering against spinlocks or memory
+ * accesses.
+ */
+
+#define readb_relaxed(c)   ({ u8  __v = __raw_readb(c); __v; })
+#define readw_relaxed(c)   ({ u16 __v = le16_to_cpu((__force 
__le16)__raw_readw(c)); __v; })
+#define readl_relaxed(c)   ({ u32 __v = le32_to_cpu((__force 
__le32)__raw_readl(c)); __v; })
+#define writeb_relaxed(v,c)((void)__raw_writeb((v),(c)))
+#define writew_relaxed(v,c)((void)__raw_writew((__force 
u16)cpu_to_le16(v),(c)))
+#define writel_relaxed(v,c)((void)__raw_writel((__force 
u32)cpu_to_le32(v),(c)))
+
+/*
+ * {read,write}{b,w,l,q}() access little endian memory and return result in
+ * native endianness.
+ */
+#define readb(c)   ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)   ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)   ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)({ __iowmb(); writeb_relaxed((v),(c)); })
+#define writew(v,c)({ __iowmb(); writew_relaxed((v),(c)); })
+#define writel(v,c)({ __iowmb(); writel_relaxed((v),(c)); })
+#include 
+#endif /* __ASM_NDS32_IO_H */
diff --git a/arch/nds32/mm/ioremap.c b/arch/nds32/mm/ioremap.c
new file mode 100644
index ..690140bb23a2
--- /dev/null
+++ b/arch/nds32/mm/ioremap.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
+
+static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size,
+ void *caller)
+{
+   struct vm_struct *area;
+   unsigned long addr, offset, last_addr;
+   pgprot_t prot;
+
+   /* Don't allow wraparound or zero size */
+   last_addr = phys_addr + size - 1;
+   if (!size || last_addr < phys_addr)
+   return NULL;
+
+   /*
+* Mappings have to be page-aligned
+*/
+   offset = phys_addr & ~PAGE_MASK;
+   phys_addr &= PAGE_MASK;
+   size = PAGE_ALIGN(last_addr + 1) - phys_addr;
+
+   /*
+* Ok, go for it..
+*/
+   area = get_vm_area_caller(size, VM_IOREMAP, caller);
+   if (!area)
+   return NULL;
+
+   area->phys_addr = phys_addr;
+   addr = (unsigned long)area->addr;
+   prot = __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D |
+   _PAGE_G | _PAGE_C_DEV);
+

[PATCH v7 15/37] nds32: Atomic operations

[Greentime Hu]

This patch includes the atomic and futex operations. Many atomic operations use
the load-lock word(llw) and store-condition word(scw) operations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/barrier.h |  15 ++
 arch/nds32/include/asm/futex.h   | 103 +++
 2 files changed, 118 insertions(+)
 create mode 100644 arch/nds32/include/asm/barrier.h
 create mode 100644 arch/nds32/include/asm/futex.h

diff --git a/arch/nds32/include/asm/barrier.h b/arch/nds32/include/asm/barrier.h
new file mode 100644
index ..faafc373ea6c
--- /dev/null
+++ b/arch/nds32/include/asm/barrier.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASM_BARRIER_H
+#define __NDS32_ASM_BARRIER_H
+
+#ifndef __ASSEMBLY__
+#define mb()   asm volatile("msync all":::"memory")
+#define rmb()  asm volatile("msync all":::"memory")
+#define wmb()  asm volatile("msync store":::"memory")
+#include 
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __NDS32_ASM_BARRIER_H */
diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h
new file mode 100644
index ..eab5e84bd991
--- /dev/null
+++ b/arch/nds32/include/asm/futex.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_FUTEX_H__
+#define __NDS32_FUTEX_H__
+
+#include 
+#include 
+#include 
+
+#define __futex_atomic_ex_table(err_reg)   \
+   "   .pushsection __ex_table,\"a\"\n"\
+   "   .align  3\n"\
+   "   .long   1b, 4f\n"   \
+   "   .long   2b, 4f\n"   \
+   "   .popsection\n"  \
+   "   .pushsection .fixup,\"ax\"\n"   \
+   "4: move%0, " err_reg "\n"  \
+   "   j   3b\n"   \
+   "   .popsection"
+
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)\
+   smp_mb();   \
+   asm volatile(   \
+   "   movi$ta, #0\n"  \
+   "1: llw %1, [%2+$ta]\n" \
+   "   " insn "\n" \
+   "2: scw %0, [%2+$ta]\n" \
+   "   beqz%0, 1b\n"   \
+   "   movi%0, #0\n"   \
+   "3:\n"  \
+   __futex_atomic_ex_table("%4")   \
+   : "=" (ret), "=" (oldval)   \
+   : "r" (uaddr), "r" (oparg), "i" (-EFAULT)   \
+   : "cc", "memory")
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr,
+ u32 oldval, u32 newval)
+{
+   int ret = 0;
+   u32 val, tmp, flags;
+
+   if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+   return -EFAULT;
+
+   smp_mb();
+   asm volatile ("   movi$ta, #0\n"
+ "1: llw %1, [%6 + $ta]\n"
+ "   sub %3, %1, %4\n"
+ "   cmovz   %2, %5, %3\n"
+ "   cmovn   %2, %1, %3\n"
+ "2: scw %2, [%6 + $ta]\n"
+ "   beqz%2, 1b\n"
+ "3:\n   " __futex_atomic_ex_table("%7")
+ :"+"(ret), "="(val), "="(tmp), "="(flags)
+ :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT)
+ :"$ta", "memory");
+   smp_mb();
+
+   *uval = val;
+   return ret;
+}
+
+static inline int
+arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
+{
+   int oldval = 0, ret;
+
+
+   pagefault_disable();
+   switch (op) {
+   case FUTEX_OP_SET:
+   __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr,
+ oparg);
+

[PATCH v7 18/37] nds32: ELF definitions

[Greentime Hu]

This patch adds definitions for the ELF format, relocation types, vdso
locations and EXEC_PAGESIZE.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/elf.h | 171 +++
 arch/nds32/include/uapi/asm/auxvec.h |  12 +++
 arch/nds32/include/uapi/asm/param.h  |  11 +++
 3 files changed, 194 insertions(+)
 create mode 100644 arch/nds32/include/asm/elf.h
 create mode 100644 arch/nds32/include/uapi/asm/auxvec.h
 create mode 100644 arch/nds32/include/uapi/asm/param.h

diff --git a/arch/nds32/include/asm/elf.h b/arch/nds32/include/asm/elf.h
new file mode 100644
index ..56c479058802
--- /dev/null
+++ b/arch/nds32/include/asm/elf.h
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASMNDS32_ELF_H
+#define __ASMNDS32_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include 
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_freg_t[3];
+
+extern unsigned int elf_hwcap;
+
+#define EM_NDS32   167
+
+#define R_NDS32_NONE   0
+#define R_NDS32_16_RELA19
+#define R_NDS32_32_RELA20
+#define R_NDS32_9_PCREL_RELA   22
+#define R_NDS32_15_PCREL_RELA  23
+#define R_NDS32_17_PCREL_RELA  24
+#define R_NDS32_25_PCREL_RELA  25
+#define R_NDS32_HI20_RELA  26
+#define R_NDS32_LO12S3_RELA27
+#define R_NDS32_LO12S2_RELA28
+#define R_NDS32_LO12S1_RELA29
+#define R_NDS32_LO12S0_RELA30
+#define R_NDS32_SDA15S3_RELA   31
+#define R_NDS32_SDA15S2_RELA   32
+#define R_NDS32_SDA15S1_RELA   33
+#define R_NDS32_SDA15S0_RELA   34
+#define R_NDS32_GOT20  37
+#define R_NDS32_25_PLTREL  38
+#define R_NDS32_COPY   39
+#define R_NDS32_GLOB_DAT   40
+#define R_NDS32_JMP_SLOT   41
+#define R_NDS32_RELATIVE   42
+#define R_NDS32_GOTOFF 43
+#define R_NDS32_GOTPC2044
+#define R_NDS32_GOT_HI20   45
+#define R_NDS32_GOT_LO12   46
+#define R_NDS32_GOTPC_HI20 47
+#define R_NDS32_GOTPC_LO12 48
+#define R_NDS32_GOTOFF_HI2049
+#define R_NDS32_GOTOFF_LO1250
+#define R_NDS32_INSN16 51
+#define R_NDS32_LABEL  52
+#define R_NDS32_LONGCALL1  53
+#define R_NDS32_LONGCALL2  54
+#define R_NDS32_LONGCALL3  55
+#define R_NDS32_LONGJUMP1  56
+#define R_NDS32_LONGJUMP2  57
+#define R_NDS32_LONGJUMP3  58
+#define R_NDS32_LOADSTORE  59
+#define R_NDS32_9_FIXED_RELA   60
+#define R_NDS32_15_FIXED_RELA  61
+#define R_NDS32_17_FIXED_RELA  62
+#define R_NDS32_25_FIXED_RELA  63
+#define R_NDS32_PLTREL_HI2064
+#define R_NDS32_PLTREL_LO1265
+#define R_NDS32_PLT_GOTREL_HI2066
+#define R_NDS32_PLT_GOTREL_LO1267
+#define R_NDS32_LO12S0_ORI_RELA72
+#define R_NDS32_DWARF2_OP1_RELA77
+#define R_NDS32_DWARF2_OP2_RELA78
+#define R_NDS32_DWARF2_LEB_RELA79
+#define R_NDS32_WORD_9_PCREL_RELA  94
+#define R_NDS32_LONGCALL4  107
+#define R_NDS32_RELA_NOP_MIX   192
+#define R_NDS32_RELA_NOP_MAX   255
+
+#define ELF_NGREG (sizeof (struct user_pt_regs) / sizeof(elf_greg_t))
+#define ELF_CORE_COPY_REGS(dest, regs) \
+   *(struct user_pt_regs *)&(dest) = (regs)->user_regs;
+
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* Core file format: The core file is written in such a way that gdb
+   can understand it and provide useful information to the user (under
+   linux we use the 'trad-core' bfd).  There are quite a number of
+   obstacles to being able to view the contents of the floating point
+   registers, and until these are solved you will not be able to view the
+   contents of them.  Actually, you can read in the core file and look at
+   the contents of the user struct to find out what the floating point
+   registers contain.
+   The actual file contents are as follows:
+   UPAGE: 1 page consisting of a user struct that tells gdb what is present
+   in the file.  Directly after this is a copy of the task_struct, which
+   is currently not used by gdb, but it may come in useful at some point.
+   All of the registers are stored as part of the upage.  The upage should
+   always be only one page.
+   DATA: The data area is stored.  We use current->end_text to
+   current->brk to pick up all of the user variables, plus any memory
+   that may have been malloced.  No attempt is made to determine if a page
+   is demand-zero or if a 

[PATCH v7 17/37] nds32: DMA mapping API

[Greentime Hu]

This patch adds support for the DMA mapping API. It uses dma_map_ops for
flexibility.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/dma-mapping.h |  14 +
 arch/nds32/kernel/dma.c  | 477 +++
 2 files changed, 491 insertions(+)
 create mode 100644 arch/nds32/include/asm/dma-mapping.h
 create mode 100644 arch/nds32/kernel/dma.c

diff --git a/arch/nds32/include/asm/dma-mapping.h 
b/arch/nds32/include/asm/dma-mapping.h
new file mode 100644
index ..2dd47d245c25
--- /dev/null
+++ b/arch/nds32/include/asm/dma-mapping.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef ASMNDS32_DMA_MAPPING_H
+#define ASMNDS32_DMA_MAPPING_H
+
+extern struct dma_map_ops nds32_dma_ops;
+
+static inline struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+{
+   return _dma_ops;
+}
+
+#endif
diff --git a/arch/nds32/kernel/dma.c b/arch/nds32/kernel/dma.c
new file mode 100644
index ..d291800fc621
--- /dev/null
+++ b/arch/nds32/kernel/dma.c
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * This is the page table (2MB) covering uncached, DMA consistent allocations
+ */
+static pte_t *consistent_pte;
+static DEFINE_RAW_SPINLOCK(consistent_lock);
+
+enum master_type {
+   FOR_CPU = 0,
+   FOR_DEVICE = 1,
+};
+
+/*
+ * VM region handling support.
+ *
+ * This should become something generic, handling VM region allocations for
+ * vmalloc and similar (ioremap, module space, etc).
+ *
+ * I envisage vmalloc()'s supporting vm_struct becoming:
+ *
+ *  struct vm_struct {
+ *struct vm_region region;
+ *unsigned longflags;
+ *struct page  **pages;
+ *unsigned int nr_pages;
+ *unsigned longphys_addr;
+ *  };
+ *
+ * get_vm_area() would then call vm_region_alloc with an appropriate
+ * struct vm_region head (eg):
+ *
+ *  struct vm_region vmalloc_head = {
+ * .vm_list= LIST_HEAD_INIT(vmalloc_head.vm_list),
+ * .vm_start   = VMALLOC_START,
+ * .vm_end = VMALLOC_END,
+ *  };
+ *
+ * However, vmalloc_head.vm_start is variable (typically, it is dependent on
+ * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
+ * would have to initialise this each time prior to calling vm_region_alloc().
+ */
+struct arch_vm_region {
+   struct list_head vm_list;
+   unsigned long vm_start;
+   unsigned long vm_end;
+   struct page *vm_pages;
+};
+
+static struct arch_vm_region consistent_head = {
+   .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
+   .vm_start = CONSISTENT_BASE,
+   .vm_end = CONSISTENT_END,
+};
+
+static struct arch_vm_region *vm_region_alloc(struct arch_vm_region *head,
+ size_t size, int gfp)
+{
+   unsigned long addr = head->vm_start, end = head->vm_end - size;
+   unsigned long flags;
+   struct arch_vm_region *c, *new;
+
+   new = kmalloc(sizeof(struct arch_vm_region), gfp);
+   if (!new)
+   goto out;
+
+   raw_spin_lock_irqsave(_lock, flags);
+
+   list_for_each_entry(c, >vm_list, vm_list) {
+   if ((addr + size) < addr)
+   goto nospc;
+   if ((addr + size) <= c->vm_start)
+   goto found;
+   addr = c->vm_end;
+   if (addr > end)
+   goto nospc;
+   }
+
+found:
+   /*
+* Insert this entry _before_ the one we found.
+*/
+   list_add_tail(>vm_list, >vm_list);
+   new->vm_start = addr;
+   new->vm_end = addr + size;
+
+   raw_spin_unlock_irqrestore(_lock, flags);
+   return new;
+
+nospc:
+   raw_spin_unlock_irqrestore(_lock, flags);
+   kfree(new);
+out:
+   return NULL;
+}
+
+static struct arch_vm_region *vm_region_find(struct arch_vm_region *head,
+unsigned long addr)
+{
+   struct arch_vm_region *c;
+
+   list_for_each_entry(c, >vm_list, vm_list) {
+   if (c->vm_start == addr)
+   goto out;
+   }
+   c = NULL;
+out:
+   return c;
+}
+
+/* FIXME: attrs is not used. */
+static void *nds32_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t * handle, gfp_t gfp,
+ unsigned long attrs)
+{
+   struct page *page;
+   struct arch_vm_region *c;
+   unsigned long order;
+   u64 mask = ~0ULL, limit;
+   pgprot_t prot = 

[PATCH v7 20/37] nds32: VDSO support

[Greentime Hu]

This patch adds VDSO support. The VDSO code is currently used for
sys_rt_sigreturn() and optimised gettimeofday() (using the SoC timer counter).

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/vdso.h  |  24 +++
 arch/nds32/include/asm/vdso_datapage.h |  36 
 arch/nds32/include/asm/vdso_timer_info.h   |  14 ++
 arch/nds32/kernel/vdso.c   | 230 
 arch/nds32/kernel/vdso/Makefile|  82 +
 arch/nds32/kernel/vdso/datapage.S  |  21 +++
 arch/nds32/kernel/vdso/gen_vdso_offsets.sh |  15 ++
 arch/nds32/kernel/vdso/gettimeofday.c  | 270 +
 arch/nds32/kernel/vdso/note.S  |  11 ++
 arch/nds32/kernel/vdso/sigreturn.S |  19 ++
 arch/nds32/kernel/vdso/vdso.S  |  18 ++
 arch/nds32/kernel/vdso/vdso.lds.S  |  76 
 12 files changed, 816 insertions(+)
 create mode 100644 arch/nds32/include/asm/vdso.h
 create mode 100644 arch/nds32/include/asm/vdso_datapage.h
 create mode 100644 arch/nds32/include/asm/vdso_timer_info.h
 create mode 100644 arch/nds32/kernel/vdso.c
 create mode 100644 arch/nds32/kernel/vdso/Makefile
 create mode 100644 arch/nds32/kernel/vdso/datapage.S
 create mode 100755 arch/nds32/kernel/vdso/gen_vdso_offsets.sh
 create mode 100644 arch/nds32/kernel/vdso/gettimeofday.c
 create mode 100644 arch/nds32/kernel/vdso/note.S
 create mode 100644 arch/nds32/kernel/vdso/sigreturn.S
 create mode 100644 arch/nds32/kernel/vdso/vdso.S
 create mode 100644 arch/nds32/kernel/vdso/vdso.lds.S

diff --git a/arch/nds32/include/asm/vdso.h b/arch/nds32/include/asm/vdso.h
new file mode 100644
index ..af2c6afc2469
--- /dev/null
+++ b/arch/nds32/include/asm/vdso.h
@@ -0,0 +1,24 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ */
+
+#ifndef __ASM_VDSO_H
+#define __ASM_VDSO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#include 
+
+#define VDSO_SYMBOL(base, name)
   \
+({\
+   (unsigned long)(vdso_offset_##name + (unsigned long)(base)); \
+})
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_H */
diff --git a/arch/nds32/include/asm/vdso_datapage.h 
b/arch/nds32/include/asm/vdso_datapage.h
new file mode 100644
index ..79db5a12ca5e
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_datapage.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+#ifndef __ASM_VDSO_DATAPAGE_H
+#define __ASM_VDSO_DATAPAGE_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+struct vdso_data {
+   bool cycle_count_down;  /* timer cyclye counter is decrease with time */
+   u32 cycle_count_offset; /* offset of timer cycle counter register */
+   u32 seq_count;  /* sequence count - odd during updates */
+   u32 xtime_coarse_sec;   /* coarse time */
+   u32 xtime_coarse_nsec;
+
+   u32 wtm_clock_sec;  /* wall to monotonic offset */
+   u32 wtm_clock_nsec;
+   u32 xtime_clock_sec;/* CLOCK_REALTIME - seconds */
+   u32 cs_mult;/* clocksource multiplier */
+   u32 cs_shift;   /* Cycle to nanosecond divisor (power of two) */
+
+   u64 cs_cycle_last;  /* last cycle value */
+   u64 cs_mask;/* clocksource mask */
+
+   u64 xtime_clock_nsec;   /* CLOCK_REALTIME sub-ns base */
+   u32 tz_minuteswest; /* timezone info for gettimeofday(2) */
+   u32 tz_dsttime;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_DATAPAGE_H */
diff --git a/arch/nds32/include/asm/vdso_timer_info.h 
b/arch/nds32/include/asm/vdso_timer_info.h
new file mode 100644
index ..50ba117cff12
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_timer_info.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+extern struct timer_info_t timer_info;
+#define EMPTY_VALUE ~(0UL)
+#define EMPTY_TIMER_MAPPING EMPTY_VALUE
+#define EMPTY_REG_OFFSET EMPTY_VALUE
+
+struct timer_info_t
+{
+   bool cycle_count_down;
+   unsigned long mapping_base;
+   unsigned long cycle_count_reg_offset;
+};
diff --git a/arch/nds32/kernel/vdso.c b/arch/nds32/kernel/vdso.c
new file mode 100644
index ..f1198d7a5654
--- /dev/null
+++ b/arch/nds32/kernel/vdso.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#

[PATCH v7 19/37] nds32: System calls handling

[Greentime Hu]

This patch adds support for system calls.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/syscall.h | 188 +++
 arch/nds32/include/asm/syscalls.h|  13 +++
 arch/nds32/include/asm/unistd.h  |   6 ++
 arch/nds32/include/uapi/asm/unistd.h |  11 ++
 arch/nds32/kernel/ex-scall.S |  98 ++
 arch/nds32/kernel/sys_nds32.c|  50 ++
 arch/nds32/kernel/syscall_table.c|  17 
 7 files changed, 383 insertions(+)
 create mode 100644 arch/nds32/include/asm/syscall.h
 create mode 100644 arch/nds32/include/asm/syscalls.h
 create mode 100644 arch/nds32/include/asm/unistd.h
 create mode 100644 arch/nds32/include/uapi/asm/unistd.h
 create mode 100644 arch/nds32/kernel/ex-scall.S
 create mode 100644 arch/nds32/kernel/sys_nds32.c
 create mode 100644 arch/nds32/kernel/syscall_table.c

diff --git a/arch/nds32/include/asm/syscall.h b/arch/nds32/include/asm/syscall.h
new file mode 100644
index ..f7e5e86765fe
--- /dev/null
+++ b/arch/nds32/include/asm/syscall.h
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2008-2009 Red Hat, Inc.  All rights reserved.
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_SYSCALL_H
+#define _ASM_NDS32_SYSCALL_H   1
+
+#include 
+struct task_struct;
+struct pt_regs;
+
+/**
+ * syscall_get_nr - find what system call a task is executing
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * If @task is executing a system call or is at system call
+ * tracing about to attempt one, returns the system call number.
+ * If @task is not executing a system call, i.e. it's blocked
+ * inside the kernel for a fault or signal, returns -1.
+ *
+ * Note this returns int even on 64-bit machines.  Only 32 bits of
+ * system call number can be meaningful.  If the actual arch value
+ * is 64 bits, this truncates to 32 bits so 0x means -1.
+ *
+ * It's only valid to call this when @task is known to be blocked.
+ */
+int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->syscallno;
+}
+
+/**
+ * syscall_rollback - roll back registers after an aborted system call
+ * @task:  task of interest, must be in system call exit tracing
+ * @regs:  task_pt_regs() of @task
+ *
+ * It's only valid to call this when @task is stopped for system
+ * call exit tracing (due to TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT),
+ * after tracehook_report_syscall_entry() returned nonzero to prevent
+ * the system call from taking place.
+ *
+ * This rolls back the register state in @regs so it's as if the
+ * system call instruction was a no-op.  The registers containing
+ * the system call number and arguments are as they were before the
+ * system call instruction.  This may not be the same as what the
+ * register state looked like at system call entry tracing.
+ */
+void syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+   regs->uregs[0] = regs->orig_r0;
+}
+
+/**
+ * syscall_get_error - check result of traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns 0 if the system call succeeded, or -ERRORCODE if it failed.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+   unsigned long error = regs->uregs[0];
+   return IS_ERR_VALUE(error) ? error : 0;
+}
+
+/**
+ * syscall_get_return_value - get the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns the return value of the successful system call.
+ * This value is meaningless if syscall_get_error() returned nonzero.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->uregs[0];
+}
+
+/**
+ * syscall_set_return_value - change the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ * @error: negative error code, or zero to indicate success
+ * @val:   user return value if @error is zero
+ *
+ * This changes the results of the system call that user mode will see.
+ * If @error is zero, the user sees a successful system call with a
+ * return value of @val.  If @error is nonzero, it's a negated errno
+ * code; the user sees a failed system call with this errno code.
+ *
+ * It's only valid to call this when @task is stopped for tracing on

[PATCH v7 21/37] nds32: Signal handling support

[Greentime Hu]

This patch adds support for signal handling.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/uapi/asm/sigcontext.h |  60 ++
 arch/nds32/kernel/signal.c   | 324 +++
 2 files changed, 384 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h
 create mode 100644 arch/nds32/kernel/signal.c

diff --git a/arch/nds32/include/uapi/asm/sigcontext.h 
b/arch/nds32/include/uapi/asm/sigcontext.h
new file mode 100644
index ..00567b237b0c
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/sigcontext.h
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_SIGCONTEXT_H
+#define _ASMNDS32_SIGCONTEXT_H
+
+/*
+ * Signal context structure - contains all info to do with the state
+ * before the signal handler was invoked.  Note: only add new entries
+ * to the end of the structure.
+ */
+
+struct zol_struct {
+   unsigned long nds32_lc; /* $LC */
+   unsigned long nds32_le; /* $LE */
+   unsigned long nds32_lb; /* $LB */
+};
+
+struct sigcontext {
+   unsigned long trap_no;
+   unsigned long error_code;
+   unsigned long oldmask;
+   unsigned long nds32_r0;
+   unsigned long nds32_r1;
+   unsigned long nds32_r2;
+   unsigned long nds32_r3;
+   unsigned long nds32_r4;
+   unsigned long nds32_r5;
+   unsigned long nds32_r6;
+   unsigned long nds32_r7;
+   unsigned long nds32_r8;
+   unsigned long nds32_r9;
+   unsigned long nds32_r10;
+   unsigned long nds32_r11;
+   unsigned long nds32_r12;
+   unsigned long nds32_r13;
+   unsigned long nds32_r14;
+   unsigned long nds32_r15;
+   unsigned long nds32_r16;
+   unsigned long nds32_r17;
+   unsigned long nds32_r18;
+   unsigned long nds32_r19;
+   unsigned long nds32_r20;
+   unsigned long nds32_r21;
+   unsigned long nds32_r22;
+   unsigned long nds32_r23;
+   unsigned long nds32_r24;
+   unsigned long nds32_r25;
+   unsigned long nds32_fp; /* $r28 */
+   unsigned long nds32_gp; /* $r29 */
+   unsigned long nds32_lp; /* $r30 */
+   unsigned long nds32_sp; /* $r31 */
+   unsigned long nds32_ipc;
+   unsigned long fault_address;
+   unsigned long used_math_flag;
+   /* FPU Registers */
+   struct zol_struct zol;
+};
+
+#endif
diff --git a/arch/nds32/kernel/signal.c b/arch/nds32/kernel/signal.c
new file mode 100644
index ..5d01f6e33cb8
--- /dev/null
+++ b/arch/nds32/kernel/signal.c
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+struct rt_sigframe {
+   struct siginfo info;
+   struct ucontext uc;
+};
+
+static int restore_sigframe(struct pt_regs *regs,
+   struct rt_sigframe __user * sf)
+{
+   sigset_t set;
+   int err;
+
+   err = __copy_from_user(, >uc.uc_sigmask, sizeof(set));
+   if (err == 0) {
+   set_current_blocked();
+   }
+
+   __get_user_error(regs->uregs[0], >uc.uc_mcontext.nds32_r0, err);
+   __get_user_error(regs->uregs[1], >uc.uc_mcontext.nds32_r1, err);
+   __get_user_error(regs->uregs[2], >uc.uc_mcontext.nds32_r2, err);
+   __get_user_error(regs->uregs[3], >uc.uc_mcontext.nds32_r3, err);
+   __get_user_error(regs->uregs[4], >uc.uc_mcontext.nds32_r4, err);
+   __get_user_error(regs->uregs[5], >uc.uc_mcontext.nds32_r5, err);
+   __get_user_error(regs->uregs[6], >uc.uc_mcontext.nds32_r6, err);
+   __get_user_error(regs->uregs[7], >uc.uc_mcontext.nds32_r7, err);
+   __get_user_error(regs->uregs[8], >uc.uc_mcontext.nds32_r8, err);
+   __get_user_error(regs->uregs[9], >uc.uc_mcontext.nds32_r9, err);
+   __get_user_error(regs->uregs[10], >uc.uc_mcontext.nds32_r10, err);
+   __get_user_error(regs->uregs[11], >uc.uc_mcontext.nds32_r11, err);
+   __get_user_error(regs->uregs[12], >uc.uc_mcontext.nds32_r12, err);
+   __get_user_error(regs->uregs[13], >uc.uc_mcontext.nds32_r13, err);
+   __get_user_error(regs->uregs[14], >uc.uc_mcontext.nds32_r14, err);
+   __get_user_error(regs->uregs[15], >uc.uc_mcontext.nds32_r15, err);
+   __get_user_error(regs->uregs[16], >uc.uc_mcontext.nds32_r16, err);
+   __get_user_error(regs->uregs[17], >uc.uc_mcontext.nds32_r17, err);
+   __get_user_error(regs->uregs[18], >uc.uc_mcontext.nds32_r18, err);
+   __get_user_error(regs->uregs[19], >uc.uc_mcontext.nds32_r19, err);
+   __get_user_error(regs->uregs[20], >uc.uc_mcontext.nds32_r20, err);
+ 

[PATCH v7 24/37] nds32: L2 cache support

[Greentime Hu]

This patch adds L2 cache support.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/l2_cache.h | 137 ++
 arch/nds32/kernel/atl2c.c |  64 ++
 2 files changed, 201 insertions(+)
 create mode 100644 arch/nds32/include/asm/l2_cache.h
 create mode 100644 arch/nds32/kernel/atl2c.c

diff --git a/arch/nds32/include/asm/l2_cache.h 
b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index ..37dd5ef61de8
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#define L2_IF_CONF_OFF 0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF  0xC
+#define L2CC_CTRL_OFF  0x10
+#define L2_INT_EN_OFF   0x20
+#define L2_STA_OFF  0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF  0x30
+#define IMPL3ERR_ADDR_OFF  0x34
+#define L2_CNT0_CTRL_OFF0x40
+#define L2_EVNT_CNT0_OFF0x44
+#define L2_CNT1_CTRL_OFF0x48
+#define L2_EVNT_CNT1_OFF0x4c
+#define L2_CCTL_CMD_OFF0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF0x68
+#define L2_LINE_DPT_OFF0x70
+
+#define CCTL_CMD_L2_IX_INVAL0x0
+#define CCTL_CMD_L2_PA_INVAL0x1
+#define CCTL_CMD_L2_IX_WB   0x2
+#define CCTL_CMD_L2_PA_WB   0x3
+#define CCTL_CMD_L2_PA_WBINVAL  0x5
+#define CCTL_CMD_L2_SYNC0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD  0x10
+#define CCTL_ALL_CMD   0x10
+
+/**
+ * L2_CA_CONF (Cache architecture configuration)
+ */
+#define L2_CA_CONF_offL2SET0
+#define L2_CA_CONF_offL2WAY4
+#define L2_CA_CONF_offL2CLSZ8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER16
+
+#define L2_CA_CONF_mskL2SET(0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY(0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ(0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER(0xUL << L2_CA_CONF_offL2VER)
+
+/**
+ * L2CC_SETUP (L2CC Setup register)
+ */
+#define L2CC_SETUP_offPART  0
+#define L2CC_SETUP_mskPART  (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC4
+#define L2CC_SETUP_mskDDLATC(0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC8
+#define L2CC_SETUP_mskTDLATC(0x3UL << L2CC_SETUP_offTDLATC)
+
+/**
+ * L2CC_PROT (L2CC Protect register)
+ */
+#define L2CC_PROT_offMRWEN  31
+#define L2CC_PROT_mskMRWEN  (0x1UL << L2CC_PROT_offMRWEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2_CCTL_STATUS_offCMD_COMP  31
+#define L2_CCTL_STATUS_mskCMD_COMP  (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+
+extern void __iomem *atl2c_base;
+#include 
+#include 
+#include 
+
+#define L2C_R_REG(offset)   readl(atl2c_base + offset)
+#define L2C_W_REG(offset, value)writel(value, atl2c_base + offset)
+
+#define L2_CMD_RDY()\
+do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & 
L2_CCTL_STATUS_mskCMD_COMP) == 0)
+
+static inline unsigned long L2_CACHE_SET(void)
+{
+   return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+}
+
+static inline unsign

[PATCH v7 23/37] nds32: Debugging support

[Greentime Hu]

This patch adds ptrace support.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/uapi/asm/ptrace.h |  25 
 arch/nds32/kernel/ptrace.c   | 119 +++
 2 files changed, 144 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ptrace.c

diff --git a/arch/nds32/include/uapi/asm/ptrace.h 
b/arch/nds32/include/uapi/asm/ptrace.h
new file mode 100644
index ..358c99e399d0
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/ptrace.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __UAPI_ASM_NDS32_PTRACE_H
+#define __UAPI_ASM_NDS32_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * User structures for general purpose register.
+ */
+struct user_pt_regs {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+   long lb;
+   long le;
+   long lc;
+   long syscallno;
+};
+#endif
+#endif
diff --git a/arch/nds32/kernel/ptrace.c b/arch/nds32/kernel/ptrace.c
new file mode 100644
index ..eaaf7a999b20
--- /dev/null
+++ b/arch/nds32/kernel/ptrace.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+enum nds32_regset {
+   REGSET_GPR,
+};
+
+static int gpr_get(struct task_struct *target,
+  const struct user_regset *regset,
+  unsigned int pos, unsigned int count,
+  void *kbuf, void __user * ubuf)
+{
+   struct user_pt_regs *uregs = _pt_regs(target)->user_regs;
+   return user_regset_copyout(, , , , uregs, 0, -1);
+}
+
+static int gpr_set(struct task_struct *target, const struct user_regset 
*regset,
+  unsigned int pos, unsigned int count,
+  const void *kbuf, const void __user * ubuf)
+{
+   int err;
+   struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
+
+   err = user_regset_copyin(, , , , , 0, -1);
+   if (err)
+   return err;
+
+   task_pt_regs(target)->user_regs = newregs;
+   return 0;
+}
+
+static const struct user_regset nds32_regsets[] = {
+   [REGSET_GPR] = {
+   .core_note_type = NT_PRSTATUS,
+   .n = sizeof(struct user_pt_regs) / sizeof(u32),
+   .size = sizeof(elf_greg_t),
+   .align = sizeof(elf_greg_t),
+   .get = gpr_get,
+   .set = gpr_set}
+};
+
+static const struct user_regset_view nds32_user_view = {
+   .name = "nds32",
+   .e_machine = EM_NDS32,
+   .regsets = nds32_regsets,
+   .n = ARRAY_SIZE(nds32_regsets)
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+   return _user_view;
+}
+
+void ptrace_disable(struct task_struct *child)
+{
+   user_disable_single_step(child);
+}
+
+/* do_ptrace()
+ *
+ * Provide ptrace defined service.
+ */
+long arch_ptrace(struct task_struct *child, long request, unsigned long addr,
+unsigned long data)
+{
+   int ret = -EIO;
+
+   switch (request) {
+   default:
+   ret = ptrace_request(child, request, addr, data);
+   break;
+   }
+
+   return ret;
+}
+
+void user_enable_single_step(struct task_struct *child)
+{
+   struct pt_regs *regs;
+   regs = task_pt_regs(child);
+   regs->ipsw |= PSW_mskHSS;
+   set_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+
+void user_disable_single_step(struct task_struct *child)
+{
+   struct pt_regs *regs;
+   regs = task_pt_regs(child);
+   regs->ipsw &= ~PSW_mskHSS;
+   clear_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+
+/* sys_trace()
+ *
+ * syscall trace handler.
+ */
+
+asmlinkage int syscall_trace_enter(struct pt_regs *regs)
+{
+   if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+   if (tracehook_report_syscall_entry(regs))
+   forget_syscall(regs);
+   }
+   return regs->syscallno;
+}
+
+asmlinkage void syscall_trace_leave(struct pt_regs *regs)
+{
+   int step = test_thread_flag(TIF_SINGLESTEP);
+   if (step || test_thread_flag(TIF_SYSCALL_TRACE))
+   tracehook_report_syscall_exit(regs, step);
+
+}
-- 
2.16.1

[PATCH v7 25/37] nds32: Loadable modules

[Greentime Hu]

This patch adds support for loadable modules.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by:  Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/module.h |  11 ++
 arch/nds32/kernel/module.c  | 278 
 2 files changed, 289 insertions(+)
 create mode 100644 arch/nds32/include/asm/module.h
 create mode 100644 arch/nds32/kernel/module.c

diff --git a/arch/nds32/include/asm/module.h b/arch/nds32/include/asm/module.h
new file mode 100644
index ..16cf9c7237ad
--- /dev/null
+++ b/arch/nds32/include/asm/module.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_MODULE_H
+#define _ASM_NDS32_MODULE_H
+
+#include 
+
+#define MODULE_ARCH_VERMAGIC   "NDS32v3"
+
+#endif /* _ASM_NDS32_MODULE_H */
diff --git a/arch/nds32/kernel/module.c b/arch/nds32/kernel/module.c
new file mode 100644
index ..4167283d8293
--- /dev/null
+++ b/arch/nds32/kernel/module.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void *module_alloc(unsigned long size)
+{
+   return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
+   GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,
+   __builtin_return_address(0));
+}
+
+void module_free(struct module *module, void *region)
+{
+   vfree(region);
+}
+
+int module_frob_arch_sections(Elf_Ehdr * hdr,
+ Elf_Shdr * sechdrs,
+ char *secstrings, struct module *mod)
+{
+   return 0;
+}
+
+void do_reloc16(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"2:\n"
+"\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+void do_reloc32(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlmw.bi\t%0, [%2], %0, 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"2:\n"
+"\tsmw.bi\t%0, [%2], %0, 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+static inline int exceed_limit(int offset, unsigned int val_mask,
+  struct module *module, Elf32_Rela * rel,
+  unsigned int relindex, unsigned int reloc_order)
+{
+   int abs_off = offset < 0 ? ~offset : offset;
+
+   if (abs_off & (~val_mask)) {
+   pr_err("\n%s: relocation type %d out of range.\n"
+  "please rebuild the kernel module with gcc option 
\"-Wa,-mno-small-text\".\n",
+   

[PATCH v7 22/37] nds32: Library functions

[Greentime Hu]

This patch add support for various library functions.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/string.h  |  17 +++
 arch/nds32/include/asm/swab.h|  35 +
 arch/nds32/include/asm/uaccess.h | 283 +++
 arch/nds32/kernel/nds32_ksyms.c  |  31 +
 arch/nds32/lib/Makefile  |   3 +
 arch/nds32/lib/clear_user.S  |  42 ++
 arch/nds32/lib/copy_from_user.S  |  45 +++
 arch/nds32/lib/copy_template.S   |  69 ++
 arch/nds32/lib/copy_to_user.S|  45 +++
 arch/nds32/lib/memcpy.S  |  30 +
 arch/nds32/lib/memmove.S |  70 ++
 arch/nds32/lib/memset.S  |  33 +
 arch/nds32/lib/memzero.S |  18 +++
 13 files changed, 721 insertions(+)
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/swab.h
 create mode 100644 arch/nds32/include/asm/uaccess.h
 create mode 100644 arch/nds32/kernel/nds32_ksyms.c
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/clear_user.S
 create mode 100644 arch/nds32/lib/copy_from_user.S
 create mode 100644 arch/nds32/lib/copy_template.S
 create mode 100644 arch/nds32/lib/copy_to_user.S
 create mode 100644 arch/nds32/lib/memcpy.S
 create mode 100644 arch/nds32/lib/memmove.S
 create mode 100644 arch/nds32/lib/memset.S
 create mode 100644 arch/nds32/lib/memzero.S

diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index ..179272caa540
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_STRING_H
+#define __ASM_NDS32_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+extern void *memzero(void *ptr, __kernel_size_t n);
+#endif
diff --git a/arch/nds32/include/asm/swab.h b/arch/nds32/include/asm/swab.h
new file mode 100644
index ..e01a755a37d2
--- /dev/null
+++ b/arch/nds32/include/asm/swab.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_SWAB_H__
+#define __NDS32_SWAB_H__
+
+#include 
+#include 
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+   __asm__("wsbh   %0, %0\n\t" /* word swap byte within halfword */
+   "rotri  %0, %0, #16\n"
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+   __asm__("wsbh   %0, %0\n"   /* word swap byte within halfword */
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+#define __arch_swab32(x) ___arch__swab32(x)
+#define __arch_swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#define __BYTEORDER_HAS_U64__
+#define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __NDS32_SWAB_H__ */
diff --git a/arch/nds32/include/asm/uaccess.h b/arch/nds32/include/asm/uaccess.h
new file mode 100644
index ..18a009f3804d
--- /dev/null
+++ b/arch/nds32/include/asm/uaccess.h
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMANDES_UACCESS_H
+#define _ASMANDES_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define VERIFY_READ0
+#define VERIFY_WRITE   1
+
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+   unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+#define KERNEL_DS  ((mm_segment_t) { ~0UL })
+#define USER_DS((mm_segment_t) {TASK_SIZE - 1})
+
+#define get_ds()   (KERNEL_DS)
+#define get_fs()   (current_thread_info()->addr_limit)
+#define user_addr_max  get_fs
+
+static inline void set_fs(mm_segment_t fs)
+{

[PATCH v7 27/37] nds32: Device tree support

[Greentime Hu]

This patch adds support for device tree.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/boot/dts/Makefile  |  8 
 arch/nds32/boot/dts/ae3xx.dts | 85 +++
 arch/nds32/kernel/devtree.c   | 19 ++
 3 files changed, 112 insertions(+)
 create mode 100644 arch/nds32/boot/dts/Makefile
 create mode 100644 arch/nds32/boot/dts/ae3xx.dts
 create mode 100644 arch/nds32/kernel/devtree.c

diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
new file mode 100644
index ..d31faa8a1d50
--- /dev/null
+++ b/arch/nds32/boot/dts/Makefile
@@ -0,0 +1,8 @@
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
new file mode 100644
index ..bb39749a6673
--- /dev/null
+++ b/arch/nds32/boot/dts/ae3xx.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x 0x4000>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0>;
+   clock-frequency = <6000>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
+
+   clock: clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <3000>;
+   };
+
+   apb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   serial0: serial@f030 {
+   compatible = "andestech,uart16550", "ns16550a";
+   reg = <0xf030 0x1000>;
+   interrupts = <8>;
+   clock-frequency = <14745600>;
+   reg-shift = <2>;
+   reg-offset = <32>;
+   no-loopback-test = <1>;
+   };
+
+   timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <>;
+   clock-names = "PCLK";
+   };
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   L2: cache-controller@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
+   mac0: ethernet@e010 {
+   compatible = "andestech,atmac100";
+   reg = <0xe010 0x1000>;
+   interrupts = <18>;
+   };
+   };
+};
diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c
new file mode 100644
index ..bdce0fe5af9f
--- /dev/null
+++ b/arch/nds32/kernel/devtree.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+
+void __init early_init_devtree(void *params)
+{
+   if (!params || !early_init_dt_scan(params)) {
+   pr_crit("\n"
+   "Error: invalid device tree blob at (virtual address 
0x%p)\n"
+   "\nPlease check your bootloader.", params);
+
+   BUG_ON(1);
+   }
+
+   dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
+}
-- 
2.16.1

[PATCH v7 26/37] nds32: Generic timers support

[Greentime Hu]

This patch adds support for timer.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Linus Walleij <linus.wall...@linaro.org>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/kernel/time.c | 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/nds32/kernel/time.c

diff --git a/arch/nds32/kernel/time.c b/arch/nds32/kernel/time.c
new file mode 100644
index ..ac9d78ce3a81
--- /dev/null
+++ b/arch/nds32/kernel/time.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+void __init time_init(void)
+{
+   of_clk_init(NULL);
+   timer_probe();
+}
-- 
2.16.1

[PATCH v7 29/37] nds32: defconfig

[Greentime Hu]

This patch adds nds32 defconfig.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/configs/defconfig | 104 +++
 1 file changed, 104 insertions(+)
 create mode 100644 arch/nds32/configs/defconfig

diff --git a/arch/nds32/configs/defconfig b/arch/nds32/configs/defconfig
new file mode 100644
index ..2546d8770785
--- /dev/null
+++ b/arch/nds32/configs/defconfig
@@ -0,0 +1,104 @@
+CONFIG_CROSS_COMPILE="nds32le-linux-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CACHE_L2 is not set
+CONFIG_PREEMPT=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_FTMAC100=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_USE_LEGACY_DNS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_GDB_SCRIPTS=y
+CONFIG_READABLE_ASM=y
+CONFIG_HEADERS_CHECK=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_PANIC_ON_OOPS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=300
+# CONFIG_CRYPTO_HW is not set
-- 
2.16.1

[PATCH v7 28/37] nds32: Miscellaneous header files

[Greentime Hu]

This patch introduces some miscellaneous header files.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/delay.h  | 39 +
 arch/nds32/include/asm/linkage.h| 11 ++
 arch/nds32/include/uapi/asm/byteorder.h | 13 +++
 3 files changed, 63 insertions(+)
 create mode 100644 arch/nds32/include/asm/delay.h
 create mode 100644 arch/nds32/include/asm/linkage.h
 create mode 100644 arch/nds32/include/uapi/asm/byteorder.h

diff --git a/arch/nds32/include/asm/delay.h b/arch/nds32/include/asm/delay.h
new file mode 100644
index ..519ba97acb6e
--- /dev/null
+++ b/arch/nds32/include/asm/delay.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_DELAY_H__
+#define __NDS32_DELAY_H__
+
+#include 
+
+/* There is no clocksource cycle counter in the CPU. */
+static inline void __delay(unsigned long loops)
+{
+   __asm__ __volatile__(".align 2\n"
+"1:\n"
+"\taddi\t%0, %0, -1\n"
+"\tbgtz\t%0, 1b\n"
+:"=r"(loops)
+:"0"(loops));
+}
+
+static inline void __udelay(unsigned long usecs, unsigned long lpj)
+{
+   usecs *= (unsigned long)(((0x8000ULL / (50 / HZ)) +
+ 0x8000ULL) >> 32);
+   usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
+   __delay(usecs);
+}
+
+#define udelay(usecs) __udelay((usecs), loops_per_jiffy)
+
+/* make sure "usecs *= ..." in udelay do not overflow. */
+#if HZ >= 1000
+#define MAX_UDELAY_MS  1
+#elif HZ <= 200
+#define MAX_UDELAY_MS  5
+#else
+#define MAX_UDELAY_MS  (1000 / HZ)
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h
new file mode 100644
index ..e708c8bdb926
--- /dev/null
+++ b/arch/nds32/include/asm/linkage.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* This file is required by include/linux/linkage.h */
+#define __ALIGN .align 2
+#define __ALIGN_STR ".align 2"
+
+#endif
diff --git a/arch/nds32/include/uapi/asm/byteorder.h 
b/arch/nds32/include/uapi/asm/byteorder.h
new file mode 100644
index ..a23f6f3a2468
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/byteorder.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BYTEORDER_H__
+#define __NDS32_BYTEORDER_H__
+
+#ifdef __NDS32_EB__
+#include 
+#else
+#include 
+#endif
+
+#endif /* __NDS32_BYTEORDER_H__ */
-- 
2.16.1

[PATCH v7 31/37] MAINTAINERS: Add nds32

[Greentime Hu]

Add a maintainer information for the nds32(Andes) architecture.

Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 MAINTAINERS | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3bdc260e36b7..bf7c2ac6bb5a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -868,6 +868,17 @@ X: drivers/iio/*/adjd*
 F: drivers/staging/iio/*/ad*
 F: drivers/staging/iio/trigger/iio-trig-bfin-timer.c
 
+ANDES ARCHITECTURE
+M:     Greentime Hu <green...@gmail.com>
+M: Vincent Chen <deanbo...@gmail.com>
+T: git https://github.com/andestech/linux.git
+S: Supported
+F: arch/nds32
+F: 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
+F: Documentation/devicetree/bindings/nds32
+K: nds32
+N: nds32
+
 ANDROID CONFIG FRAGMENTS
 M: Rob Herring <r...@kernel.org>
 S: Supported
-- 
2.16.1

[PATCH v7 33/37] dt-bindings: nds32 L2 cache controller Bindings

[Greentime Hu]

This patch adds nds32 L2 cache controller binding documents.

Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 Documentation/devicetree/bindings/nds32/atl2c.txt | 28 +++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt

diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt 
b/Documentation/devicetree/bindings/nds32/atl2c.txt
new file mode 100644
index ..da8ab8e7ae9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
@@ -0,0 +1,28 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: "andestech,atl2c"
+   - reg : Physical base address and size of cache controller's memory 
mapped
+   - cache-unified : Specifies the cache is a unified cache.
+   - cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+   cache-controller@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
-- 
2.16.1

[PATCH v7 30/37] nds32: Build infrastructure

[Greentime Hu]

This patch adds Makefile, Kconfig and vmlinux.lds.S files required for building
an nds32 kernel.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/Kconfig | 103 ++
 arch/nds32/Kconfig.cpu | 174 +
 arch/nds32/Makefile|  66 ++
 arch/nds32/boot/Makefile   |  15 
 arch/nds32/include/asm/Kbuild  |  55 
 arch/nds32/include/uapi/asm/Kbuild |  29 +++
 arch/nds32/kernel/Makefile |  23 +
 arch/nds32/kernel/vmlinux.lds.S|  57 
 arch/nds32/mm/Makefile |   7 ++
 9 files changed, 529 insertions(+)
 create mode 100644 arch/nds32/Kconfig
 create mode 100644 arch/nds32/Kconfig.cpu
 create mode 100644 arch/nds32/Makefile
 create mode 100644 arch/nds32/boot/Makefile
 create mode 100644 arch/nds32/include/asm/Kbuild
 create mode 100644 arch/nds32/include/uapi/asm/Kbuild
 create mode 100644 arch/nds32/kernel/Makefile
 create mode 100644 arch/nds32/kernel/vmlinux.lds.S
 create mode 100644 arch/nds32/mm/Makefile

diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
new file mode 100644
index ..249f38d3388f
--- /dev/null
+++ b/arch/nds32/Kconfig
@@ -0,0 +1,103 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config NDS32
+def_bool y
+   select ARCH_WANT_FRAME_POINTERS if FTRACE
+   select CLKSRC_MMIO
+   select CLONE_BACKWARDS
+   select COMMON_CLK
+   select GENERIC_ATOMIC64
+   select GENERIC_CPU_DEVICES
+   select GENERIC_CLOCKEVENTS
+   select GENERIC_IRQ_CHIP
+   select GENERIC_IRQ_SHOW
+   select GENERIC_STRNCPY_FROM_USER
+   select GENERIC_STRNLEN_USER
+   select GENERIC_TIME_VSYSCALL
+   select HANDLE_DOMAIN_IRQ
+   select HAVE_ARCH_TRACEHOOK
+   select HAVE_DEBUG_KMEMLEAK
+   select HAVE_MEMBLOCK
+   select HAVE_REGS_AND_STACK_ACCESS_API
+   select IRQ_DOMAIN
+   select LOCKDEP_SUPPORT
+   select MODULES_USE_ELF_RELA
+   select OF
+   select OF_EARLY_FLATTREE
+   select NO_BOOTMEM
+   select NO_IOPORT_MAP
+   select RTC_LIB
+   select THREAD_INFO_IN_TASK
+   help
+ Andes(nds32) Linux support.
+
+config GENERIC_CALIBRATE_DELAY
+   def_bool y
+
+config GENERIC_CSUM
+def_bool y
+
+config GENERIC_HWEIGHT
+def_bool y
+
+config GENERIC_LOCKBREAK
+def_bool y
+   depends on PREEMPT
+
+config RWSEM_GENERIC_SPINLOCK
+   def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
+   def_bool y
+
+config STACKTRACE_SUPPORT
+def_bool y
+
+config FIX_EARLYCON_MEM
+   def_bool y
+
+config PGTABLE_LEVELS
+   default 2
+
+source "init/Kconfig"
+
+menu "System Type"
+source "arch/nds32/Kconfig.cpu"
+config NR_CPUS
+   int
+   default 1
+
+config MMU
+def_bool y
+
+config NDS32_BUILTIN_DTB
+string "Builtin DTB"
+default ""
+   help
+ User can use it to specify the dts of the SoC
+endmenu
+
+menu "Kernel Features"
+source "kernel/Kconfig.preempt"
+source "mm/Kconfig"
+source "kernel/Kconfig.hz"
+endmenu
+
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+endmenu
+
+source "net/Kconfig"
+source "drivers/Kconfig"
+source "fs/Kconfig"
+
+menu "Kernel hacking"
+source "lib/Kconfig.debug"
+endmenu
+
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
new file mode 100644
index ..ba44cc539da9
--- /dev/null
+++ b/arch/nds32/Kconfig.cpu
@@ -0,0 +1,174 @@
+comment "Processor Features"
+
+config CPU_BIG_ENDIAN
+   bool "Big endian"
+
+config CPU_LITTLE_ENDIAN
+def_bool !CPU_BIG_ENDIAN
+
+config HWZOL
+   bool "hardware zero overhead loop support"
+   depends on CPU_D10 || CPU_D15
+   default n
+   help
+ A set of Zero-Overhead Loop mechanism is provided to reduce the
+ instruction fetch and execution overhead of loop-control instructions.
+ It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
+ You don't need to save these registers if you can make sure your user
+ program doesn't use these registers.
+
+ If unsure, say N.
+
+config CPU_CACHE_ALIASING
+   bool "Aliasing cache"
+   depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
+   default y
+   help
+ If this CPU is using VIPT data cache and its cache way size is larger
+ than page size, say Y. If it is using PIPT data cache, say N.
+
+ If unsure, say Y.
+
+choice
+   prompt 

[PATCH v7 34/37] dt-bindings: nds32 SoC Bindings

[Greentime Hu]

This patch adds nds32 SoC(AE3XX and AG101P) binding documents.

Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 .../devicetree/bindings/nds32/andestech-boards | 40 ++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/andestech-boards

diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards 
b/Documentation/devicetree/bindings/nds32/andestech-boards
new file mode 100644
index ..f5d75693e3c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/andestech-boards
@@ -0,0 +1,40 @@
+Andestech(nds32) AE3XX Platform
+-
+The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It
+is composed of one Andestech(nds32) processor and AE3XX.
+
+Required properties (in root node):
+- compatible = "andestech,ae3xx";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+};
+
+Andestech(nds32) AG101P Platform
+-
+AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
+processors to provide a cost-effective and high performance solution for
+majority of embedded systems in variety of application domains. Users may
+simply attach their IP on one of the system buses together with certain glue
+logics to complete a SoC solution for a specific application. With
+comprehensive simulation and design environments, users may evaluate the
+system performance of their applications and track bugs of their designs
+efficiently. The optional hardware development platform further provides real
+system environment for early prototyping and software/hardware co-development.
+
+Required properties (in root node):
+   compatible = "andestech,ag101p";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ag101p";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+};
-- 
2.16.1

[PATCH v7 35/37] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller

[Greentime Hu]

This patch adds an irqchip driver document for the Andestech Internal Vector
Interrupt Controller.

Signed-off-by: Rick Chen <r...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 .../interrupt-controller/andestech,ativic32.txt   | 19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
new file mode 100644
index ..f4b4193d830e
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
@@ -0,0 +1,19 @@
+* Andestech Internal Vector Interrupt Controller
+
+The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
+suitable for a simpler SoC platform not requiring a more sophisticated and
+bigger External Vector Interrupt Controller.
+
+
+Main node required properties:
+
+- compatible : should at least contain  "andestech,ativic32".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
+
+Examples:
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
-- 
2.16.1

[PATCH v7 37/37] net: faraday add nds32 support.

[Greentime Hu]

This patch is used to support nds32 architecture to use these faraday
mac IP.

Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 drivers/net/ethernet/faraday/Kconfig | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/faraday/Kconfig 
b/drivers/net/ethernet/faraday/Kconfig
index 040c7f163325..0fb8df656677 100644
--- a/drivers/net/ethernet/faraday/Kconfig
+++ b/drivers/net/ethernet/faraday/Kconfig
@@ -5,7 +5,7 @@
 config NET_VENDOR_FARADAY
bool "Faraday devices"
default y
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
---help---
  If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -18,7 +18,8 @@ if NET_VENDOR_FARADAY
 
 config FTMAC100
tristate "Faraday FTMAC100 10/100 Ethernet support"
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
+   depends on !64BIT || BROKEN
select MII
---help---
  This driver supports the FTMAC100 10/100 Ethernet controller
@@ -27,7 +28,8 @@ config FTMAC100
 
 config FTGMAC100
tristate "Faraday FTGMAC100 Gigabit Ethernet support"
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
+   depends on !64BIT || BROKEN
select PHYLIB
---help---
  This driver supports the FTGMAC100 Gigabit Ethernet controller
-- 
2.16.1

[PATCH v7 0/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

[Greentime Hu]

Hi, all:

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Changes in v7:
 - Fix atcpit100_clkevt_next_event(), before set reload register,
   clock source timer shall disable. And re-enable it after the setting.
   Without this modification, the test case 'clock_nanosleep02' of ltp_20170929
   will fail.

Changes in v6:
 - To select TIMER_OF in drivers/clocksource/Kconfig instead of 
arch/nds32/Kconfig
 - Refine Kconfig
 - Update license format to SPDX-License-Identifier


Rick Chen (3):
  clocksource/drivers/atcpit100: Add andestech atcpit100 timer
  clocksource/drivers/atcpit100: VDSO support
  dt-bindings: timer: Add andestech atcpit100 timer binding doc

 .../bindings/timer/andestech,atcpit100-timer.txt   |  33 +++
 drivers/clocksource/Kconfig|   9 +
 drivers/clocksource/Makefile   |   1 +
 drivers/clocksource/timer-atcpit100.c  | 266 +
 4 files changed, 309 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
 create mode 100644 drivers/clocksource/timer-atcpit100.c

-- 
2.16.1

[PATCH v7 36/37] irqchip: Andestech Internal Vector Interrupt Controller driver

[Greentime Hu]

This patch adds the Andestech Internal Vector Interrupt Controller
driver. You can find the spec here. Ch4.9 of AndeStar SPA V3 Manual.
http://www.andestech.com/product.php?cls=9

Signed-off-by: Rick Chen <r...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
---
 drivers/irqchip/Makefile   |   1 +
 drivers/irqchip/irq-ativic32.c | 107 +
 2 files changed, 108 insertions(+)
 create mode 100644 drivers/irqchip/irq-ativic32.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d27e3e3619e0..de7cf483e1b7 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_IRQ_UNIPHIER_AIDET)  += irq-uniphier-aidet.o
 obj-$(CONFIG_ARCH_SYNQUACER)   += irq-sni-exiu.o
 obj-$(CONFIG_MESON_IRQ_GPIO)   += irq-meson-gpio.o
 obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
+obj-$(CONFIG_NDS32)+= irq-ativic32.o
diff --git a/drivers/irqchip/irq-ativic32.c b/drivers/irqchip/irq-ativic32.c
new file mode 100644
index ..f69a8588521c
--- /dev/null
+++ b/drivers/irqchip/irq-ativic32.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void ativic32_ack_irq(struct irq_data *data)
+{
+   __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
+}
+
+static void ativic32_mask_irq(struct irq_data *data)
+{
+   unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
+   __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), 
NDS32_SR_INT_MASK2);
+}
+
+static void ativic32_unmask_irq(struct irq_data *data)
+{
+   unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
+   __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
+}
+
+static struct irq_chip ativic32_chip = {
+   .name = "ativic32",
+   .irq_ack = ativic32_ack_irq,
+   .irq_mask = ativic32_mask_irq,
+   .irq_unmask = ativic32_unmask_irq,
+};
+
+static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
+
+static struct irq_domain *root_domain;
+static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
+ irq_hw_number_t hw)
+{
+
+   unsigned long int_trigger_type;
+   u32 type;
+   struct irq_data *irq_data;
+   int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER);
+   irq_data = irq_get_irq_data(virq);
+   if (!irq_data)
+   return -EINVAL;
+
+   if (int_trigger_type & (BIT(hw))) {
+   irq_set_chip_and_handler(virq, _chip, handle_edge_irq);
+   type = IRQ_TYPE_EDGE_RISING;
+   } else {
+   irq_set_chip_and_handler(virq, _chip, 
handle_level_irq);
+   type = IRQ_TYPE_LEVEL_HIGH;
+   }
+
+   irqd_set_trigger_type(irq_data, type);
+   return 0;
+}
+
+static struct irq_domain_ops ativic32_ops = {
+   .map = ativic32_irq_domain_map,
+   .xlate = irq_domain_xlate_onecell
+};
+
+static irq_hw_number_t get_intr_src(void)
+{
+   return ((__nds32__mfsr(NDS32_SR_ITYPE) & ITYPE_mskVECTOR) >> 
ITYPE_offVECTOR)
+   - NDS32_VECTOR_offINTERRUPT;
+}
+
+asmlinkage void asm_do_IRQ(struct pt_regs *regs)
+{
+   irq_hw_number_t hwirq = get_intr_src();
+   handle_domain_irq(root_domain, hwirq, regs);
+}
+
+int __init ativic32_init_irq(struct device_node *node, struct device_node 
*parent)
+{
+   unsigned long int_vec_base, nivic, nr_ints;
+
+   if (WARN(parent, "non-root ativic32 are not supported"))
+   return -EINVAL;
+
+   int_vec_base = __nds32__mfsr(NDS32_SR_IVB);
+
+   if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0)
+   panic("Unable to use atcivic32 for this cpu.\n");
+
+   nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC;
+   if (nivic >= ARRAY_SIZE(nivic_map))
+   panic("The number of input for ativic32 is not supported.\n");
+
+   nr_ints = nivic_map[nivic];
+
+   root_domain = irq_domain_add_linear(node, nr_ints,
+   _ops, NULL);
+
+   if (!root_domain)
+   panic("%s: unable to create IRQ domain\n", node->full_name);
+
+   return 0;
+}
+IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq);
-- 
2.16.1

[PATCH v7 2/3] clocksource/drivers/atcpit100: VDSO support

[Greentime Hu]

From: Rick Chen <rickche...@gmail.com>

VDSO needs real-time cycle count to ensure the time accuracy.
Unlike others, nds32 architecture does not define clock source,
hence VDSO needs atcpit100 offering real-time cycle count
to derive the correct time.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Rick Chen <rickche...@gmail.com>
Signed-off-by: Greentime Hu <green...@gmail.com>
---
 drivers/clocksource/timer-atcpit100.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
index 2190096cffa3..5e23d7b4a722 100644
--- a/drivers/clocksource/timer-atcpit100.c
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -18,6 +18,9 @@
 #include 
 #include 
 #include "timer-of.h"
+#ifdef CONFIG_NDS32
+#include 
+#endif
 
 /*
  * Definition of register offsets
@@ -204,6 +207,17 @@ static u64 notrace atcpit100_timer_sched_read(void)
return ~readl(timer_of_base() + CH1_CNT);
 }
 
+#ifdef CONFIG_NDS32
+static void fill_vdso_need_info(struct device_node *node)
+{
+   struct resource timer_res;
+   of_address_to_resource(node, 0, _res);
+   timer_info.mapping_base = (unsigned long)timer_res.start;
+   timer_info.cycle_count_down = true;
+   timer_info.cycle_count_reg_offset = CH1_CNT;
+}
+#endif
+
 static int __init atcpit100_timer_init(struct device_node *node)
 {
int ret;
@@ -242,6 +256,10 @@ static int __init atcpit100_timer_init(struct device_node 
*node)
val = readl(base + INT_EN);
writel(val | CH0INT0EN, base + INT_EN);
 
+#ifdef CONFIG_NDS32
+   fill_vdso_need_info(node);
+#endif
+
return ret;
 }
 
-- 
2.16.1

[PATCH v7 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

[Greentime Hu]

From: Rick Chen <rickche...@gmail.com>

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Signed-off-by: Rick Chen <rickche...@gmail.com>
Signed-off-by: Greentime Hu <green...@gmail.com>
Reviewed-by: Linus Walleij <linus.wall...@linaro.org>

Add andestech atcpit100 timer
---
 drivers/clocksource/Kconfig   |   9 ++
 drivers/clocksource/Makefile  |   1 +
 drivers/clocksource/timer-atcpit100.c | 248 ++
 3 files changed, 258 insertions(+)
 create mode 100644 drivers/clocksource/timer-atcpit100.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index b3b4ed9b6874..19d65fe0627e 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -591,4 +591,13 @@ config CLKSRC_ST_LPC
  Enable this option to use the Low Power controller timer
  as clocksource.
 
+config ATCPIT100_TIMER
+   bool "ATCPIT100 timer driver"
+   depends on NDS32 || COMPILE_TEST
+   depends on HAS_IOMEM
+   select TIMER_OF
+   default NDS32
+   help
+ This option enables support for the Andestech ATCPIT100 timers.
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index d6dec4489d66..a79523b22e52 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
 obj-$(CONFIG_H8300_TPU)+= h8300_tpu.o
 obj-$(CONFIG_CLKSRC_ST_LPC)+= clksrc_st_lpc.o
 obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+obj-$(CONFIG_ATCPIT100_TIMER)  += timer-atcpit100.o
diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
new file mode 100644
index ..2190096cffa3
--- /dev/null
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+/*
+ *  Andestech ATCPIT100 Timer Device Driver Implementation
+ * Rick Chen, Andes Technology Corporation <r...@andestech.com>
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "timer-of.h"
+
+/*
+ * Definition of register offsets
+ */
+
+/* ID and Revision Register */
+#define ID_REV 0x0
+
+/* Configuration Register */
+#define CFG0x10
+
+/* Interrupt Enable Register */
+#define INT_EN 0x14
+#define CH_INT_EN(c, i)((1<<i)<<(4*c))
+#define CH0INT0EN  0x01
+
+/* Interrupt Status Register */
+#define INT_STA0x18
+#define CH0INT00x01
+
+/* Channel Enable Register */
+#define CH_EN  0x1C
+#define CH0TMR0EN  0x1
+#define CH1TMR0EN  0x10
+
+/* Channel 0 , 1 Control Register */
+#define CH0_CTL(0x20)
+#define CH1_CTL(0x20 + 0x10)
+
+/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
+#define APB_CLKBIT(3)
+
+/* Channel mode , bit 0~2 */
+#define TMR_32 0x1
+#define TMR_16 0x2
+#define TMR_8  0x3
+
+/* Channel 0 , 1 Reload Register */
+#define CH0_REL(0x24)
+#define CH1_REL(0x24 + 0x10)
+
+/* Channel 0 , 1 Counter Register */
+#define CH0_CNT(0x28)
+#define CH1_CNT(0x28 + 0x10)
+
+#define TIMER_SYNC_TICKS   3
+
+static void atcpit100_ch1_tmr0_en(void __iomem *base)
+{
+   writel(~0, base + CH1_REL);
+   writel(APB_CLK|TMR_32, base + CH1_CTL);
+}
+
+static void atcpit100_ch0_tmr0_en(void __iomem *base)
+{
+   writel(APB_CLK|TMR_32, base + CH0_CTL);
+}
+
+static void atcpit100_clkevt_time_setup(void __iomem *base, unsigned long 
delay)
+{
+   writel(delay, base + CH0_CNT);
+   writel(delay, base + CH0_REL);
+}
+
+static void atcpit100_timer_clear_interrupt(void __iomem *base)
+{
+   u32 val;
+
+   val = readl(base + INT_STA);
+   writel(val | CH0INT0, base + INT_STA);
+}
+
+static void atcpit100_clocksource_start(void __iomem *base)
+{
+   u32 val;
+
+   val = readl(base + CH_EN);
+   writel(val | CH1TMR0EN, base + CH_EN);
+}
+
+static void atcpit100_clkevt_time_start(void __iomem *base)
+{
+   u32 val;
+
+   val = readl(base + CH_EN);
+   writel(val | CH0TMR0EN, base + CH_EN);
+}
+
+static void atcpit100_clkevt_time_stop(void __iomem *base)
+{
+   u32 val;
+
+   atcpit100_timer_clear_interrupt(base);
+   val = readl(base + CH_EN);
+ 

[PATCH v7 3/3] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[Greentime Hu]

From: Rick Chen <rickche...@gmail.com>

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: Rick Chen <rickche...@gmail.com>
Signed-off-by: Greentime Hu <green...@gmail.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 .../bindings/timer/andestech,atcpit100-timer.txt   | 33 ++
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt

diff --git 
a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt 
b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index ..4c9ea5989e35
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+--
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible   : Should be "andestech,atcpit100"
+- reg  : Address and length of the register set
+- interrupts   : Reference to the timer interrupt
+- clocks   : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names  : should be "PCLK" for the peripheral clock source.
+
+Examples:
+
+timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <>;
+   clock-names = "PCLK";
+};
-- 
2.16.1

[PATCH v7 32/37] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

This patch adds nds32 CPU binding documents.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Rick Chen <r...@andestech.com>
Signed-off-by: Zong Li <z...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/nds32/cpus.txt | 38 
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt

diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
b/Documentation/devicetree/bindings/nds32/cpus.txt
new file mode 100644
index ..6f9e311b6589
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/cpus.txt
@@ -0,0 +1,38 @@
+* Andestech Processor Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Andestech Processor Core, which is the root node in the
+tree.
+
+Required properties:
+
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: Should be "andestech,", 
"andestech,nds32v3" as fallback.
+   Must contain "andestech,nds32v3" as the most generic value, in 
addition to
+   one of the following identifiers for a particular CPU core:
+   "andestech,n13"
+   "andestech,n15"
+   "andestech,d15"
+   "andestech,n10"
+   "andestech,d10"
+   - device_type
+   Usage: required
+   Value type: 
+   Definition: must be "cpu"
+   - reg: Contains CPU index.
+   - clock-frequency: Contains the clock frequency for CPU, in Hz.
+
+* Examples
+
+/ {
+   cpus {
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0x0>;
+   clock-frequency = <6000>
+   };
+   };
+};
-- 
2.16.1

[PATCH v7 11/37] nds32: MMU fault handling and page table management

[Greentime Hu]

This patch includes page fault handler, mmap and fixup implementations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/lib/copy_page.S |  37 
 arch/nds32/mm/extable.c|  16 ++
 arch/nds32/mm/fault.c  | 410 +
 arch/nds32/mm/mmap.c   |  73 
 4 files changed, 536 insertions(+)
 create mode 100644 arch/nds32/lib/copy_page.S
 create mode 100644 arch/nds32/mm/extable.c
 create mode 100644 arch/nds32/mm/fault.c
 create mode 100644 arch/nds32/mm/mmap.c

diff --git a/arch/nds32/lib/copy_page.S b/arch/nds32/lib/copy_page.S
new file mode 100644
index ..4a2ff85f17ee
--- /dev/null
+++ b/arch/nds32/lib/copy_page.S
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+   .text
+ENTRY(copy_page)
+   pushm   $r2, $r10
+   movi$r2, PAGE_SIZE >> 5
+.Lcopy_loop:
+   lmw.bim $r3, [$r1], $r10
+   smw.bim $r3, [$r0], $r10
+   subi45  $r2, #1
+   bnez38  $r2, .Lcopy_loop
+   popm$r2, $r10
+   ret
+ENDPROC(copy_page)
+
+ENTRY(clear_page)
+   pushm   $r1, $r9
+   movi$r1, PAGE_SIZE >> 5
+   movi55  $r2, #0
+   movi55  $r3, #0
+   movi55  $r4, #0
+   movi55  $r5, #0
+   movi55  $r6, #0
+   movi55  $r7, #0
+   movi55  $r8, #0
+   movi55  $r9, #0
+.Lclear_loop:
+   smw.bim $r2, [$r0], $r9
+   subi45  $r1, #1
+   bnez38  $r1, .Lclear_loop
+   popm$r1, $r9
+ret
+ENDPROC(clear_page)
diff --git a/arch/nds32/mm/extable.c b/arch/nds32/mm/extable.c
new file mode 100644
index ..db7f0a7c8966
--- /dev/null
+++ b/arch/nds32/mm/extable.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+int fixup_exception(struct pt_regs *regs)
+{
+   const struct exception_table_entry *fixup;
+
+   fixup = search_exception_tables(instruction_pointer(regs));
+   if (fixup)
+   regs->ipc = fixup->fixup;
+
+   return fixup != NULL;
+}
diff --git a/arch/nds32/mm/fault.c b/arch/nds32/mm/fault.c
new file mode 100644
index ..3a246fb8098c
--- /dev/null
+++ b/arch/nds32/mm/fault.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+extern void die(const char *str, struct pt_regs *regs, long err);
+
+/*
+ * This is useful to dump out the page tables associated with
+ * 'addr' in mm 'mm'.
+ */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{
+   pgd_t *pgd;
+   if (!mm)
+   mm = _mm;
+
+   pr_alert("pgd = %p\n", mm->pgd);
+   pgd = pgd_offset(mm, addr);
+   pr_alert("[%08lx] *pgd=%08lx", addr, pgd_val(*pgd));
+
+   do {
+   pmd_t *pmd;
+
+   if (pgd_none(*pgd))
+   break;
+
+   if (pgd_bad(*pgd)) {
+   pr_alert("(bad)");
+   break;
+   }
+
+   pmd = pmd_offset(pgd, addr);
+#if PTRS_PER_PMD != 1
+   pr_alert(", *pmd=%08lx", pmd_val(*pmd));
+#endif
+
+   if (pmd_none(*pmd))
+   break;
+
+   if (pmd_bad(*pmd)) {
+   pr_alert("(bad)");
+   break;
+   }
+
+   if (IS_ENABLED(CONFIG_HIGHMEM))
+   {
+   pte_t *pte;
+   /* We must not map this if we have highmem enabled */
+   pte = pte_offset_map(pmd, addr);
+   pr_alert(", *pte=%08lx", pte_val(*pte));
+   pte_unmap(pte);
+   }
+   } while (0);
+
+   pr_alert("\n");
+}
+
+void do_page_fault(unsigned long entry, unsigned long addr,
+  unsigned int error_code, struct pt_regs *regs)
+{
+   struct task_struct *tsk;
+   struct mm_struct *mm;
+   struct vm_area_struct *vma;
+   siginfo_t info;
+   int fault;
+   unsigned int mask = VM_READ | VM_WRITE | VM_EXEC;
+   unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+
+   error_code = error_code & (ITYPE_mskINST | ITYPE_mskETYPE);
+   tsk = current;
+   mm = tsk->mm;
+   info.si_code = SEGV_MAPERR;
+   /*
+* We fault-in kernel-space virtual memory on-demand. The
+* 'reference' page table is init_mm.pgd.
+*
+* NOTE! We MUST NOT take any locks for this case. We may
+* be in an interrupt or a critical region, and should
+* only

[PATCH v7 07/37] nds32: Kernel booting and initialization

[Greentime Hu]

This patch includes the kernel startup code. It can get dtb pointer
passed from bootloader. It will create a temp mapping by tlb
instructions at beginning and goto start_kernel.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/kernel/head.S  | 188 
 arch/nds32/kernel/setup.c | 363 ++
 2 files changed, 551 insertions(+)
 create mode 100644 arch/nds32/kernel/head.S
 create mode 100644 arch/nds32/kernel/setup.c

diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
new file mode 100644
index ..71f57bd70f3b
--- /dev/null
+++ b/arch/nds32/kernel/head.S
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0
+#endif
+
+   .globl  swapper_pg_dir
+   .equswapper_pg_dir, TEXTADDR - 0x4000
+
+/*
+ * Kernel startup entry point.
+ */
+   .section ".head.text", "ax"
+   .type   _stext, %function
+ENTRY(_stext)
+   setgie.d! Disable interrupt
+   isb
+/*
+ * Disable I/D-cache and enable it at a proper time
+ */
+   mfsr$r0, $mr8
+   li  $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
+   and $r0, $r0, $r1
+   mtsr$r0, $mr8
+
+/*
+ * Process device tree blob
+ */
+   andi$r0,$r2,#0x3
+   li  $r10, 0
+   bne $r0, $r10, _nodtb
+   lwi $r0, [$r2]
+   li  $r1, OF_DT_MAGIC
+   bne $r0, $r1, _nodtb
+   move$r10, $r2
+_nodtb:
+
+/*
+ * Create a temporary mapping area for booting, before start_kernel
+ */
+   sethi   $r4, hi20(swapper_pg_dir)
+   li  $p0, (PAGE_OFFSET - PHYS_OFFSET)
+   sub $r4, $r4, $p0
+   tlbop   FlushAll! invalidate TLB\n"
+   isb
+   mtsr$r4, $L1_PPTB   ! load page table pointer\n"
+
+/* set NTC0 cacheable/writeback, mutliple page size in use */
+   mfsr$r3, $MMU_CTL
+   li  $r0, #~MMU_CTL_mskNTC0
+   and $r3, $r3, $r0
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0))
+#else
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0)|MMU_CTL_D8KB)
+#endif
+#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
+   li  $r0, #MMU_CTL_UNA
+   or  $r3, $r3, $r0
+#endif
+   mtsr$r3, $MMU_CTL
+   isb
+
+/* set page size and size of kernel image */
+mfsr$r0, $MMU_CFG
+srli$r3, $r0, MMU_CFG_offfEPSZ
+zeb $r3, $r3
+bnez$r3, _extra_page_size_support
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+li  $r5, #SZ_4K ! Use 4KB page size
+#else
+li  $r5, #SZ_8K ! Use 8KB page size
+li  $r3, #1
+#endif
+mtsr$r3, $TLB_MISC
+b   _image_size_check
+
+_extra_page_size_support:! Use epzs pages size
+clz $r6, $r3
+subri   $r2, $r6, #31
+li  $r3, #1
+sll $r3, $r3, $r2
+/* MMU_CFG.EPSZ value -> meaning */
+mul $r5, $r3, $r3
+slli$r5, $r5, #14
+/* MMU_CFG.EPSZ  -> TLB_MISC.ACC_PSZ */
+addi$r3, $r2, #0x2
+mtsr$r3, $TLB_MISC
+
+_image_size_check:
+/* calculate the image maximum size accepted by TLB config */
+andi$r6, $r0, MMU_CFG_mskTBW
+andi$r0, $r0, MMU_CFG_mskTBS
+srli$r6, $r6, MMU_CFG_offTBW
+srli$r0, $r0, MMU_CFG_offTBS
+/*
+ * we just map the kernel to the maximum way - 1 of tlb
+ * reserver one way for UART VA mapping
+ * it will cause page fault if UART mapping cover the kernel mapping
+ *
+ * direct mapping is not supported now.
+ */
+li  $r2, 't'
+beqz$r6, __error ! MMU_CFG.TBW = 0 is direct mappin
+addi$r0, $r0, #0x2   ! MMU_CFG.TBS value -> meaning
+sll $r0, $r6, $r0! entries = k-way * n-set
+mul $r6, $r0, $r5! max size = entries * page size
+/* check kernel image size */
+la  $r3, (_end - PAGE_OFFSET)
+li  $r2, 's'
+bgt $r3, $r6, __error
+
+   li  $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
+li  $r3, PAGE_OFFSET
+add $r6, $r6, $r3
+
+_tlb:
+   mtsr$r3, $TLB_VPN
+   dsb
+   tlbop   $r2, RWR
+   isb
+   add $r3, $r3, $r5
+   add $r2, $r2, $r5
+   bgt $r6, $r3, _tlb
+   mfsr$r3, $TLB_MISC  ! setup access pag

[PATCH v7 09/37] nds32: MMU definitions

[Greentime Hu]

This patch includes virtual memory layout, PHYS_OFFSET is defined as 0x0. It
also includes the 4KB/8KB page size configurations and pte operations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 arch/nds32/include/asm/fixmap.h   |  29 +++
 arch/nds32/include/asm/highmem.h  |  65 ++
 arch/nds32/include/asm/memory.h   | 105 ++
 arch/nds32/include/asm/mmu.h  |  12 ++
 arch/nds32/include/asm/page.h |  67 +++
 arch/nds32/include/asm/pgalloc.h  |  96 +
 arch/nds32/include/asm/pgtable.h  | 409 ++
 arch/nds32/include/asm/shmparam.h |  19 ++
 8 files changed, 802 insertions(+)
 create mode 100644 arch/nds32/include/asm/fixmap.h
 create mode 100644 arch/nds32/include/asm/highmem.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/mmu.h
 create mode 100644 arch/nds32/include/asm/page.h
 create mode 100644 arch/nds32/include/asm/pgalloc.h
 create mode 100644 arch/nds32/include/asm/pgtable.h
 create mode 100644 arch/nds32/include/asm/shmparam.h

diff --git a/arch/nds32/include/asm/fixmap.h b/arch/nds32/include/asm/fixmap.h
new file mode 100644
index ..0e60e153a71a
--- /dev/null
+++ b/arch/nds32/include/asm/fixmap.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_FIXMAP_H
+#define __ASM_NDS32_FIXMAP_H
+
+#ifdef CONFIG_HIGHMEM
+#include 
+#include 
+#endif
+
+enum fixed_addresses {
+   FIX_HOLE,
+   FIX_KMAP_RESERVED,
+   FIX_KMAP_BEGIN,
+#ifdef CONFIG_HIGHMEM
+   FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS),
+#endif
+   FIX_EARLYCON_MEM_BASE,
+   __end_of_fixed_addresses
+};
+#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE)))
+#define FIXADDR_SIZE   ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START  (FIXADDR_TOP - FIXADDR_SIZE)
+#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE)
+void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
+
+#include 
+#endif /* __ASM_NDS32_FIXMAP_H */
diff --git a/arch/nds32/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h
new file mode 100644
index ..425d546cb059
--- /dev/null
+++ b/arch/nds32/include/asm/highmem.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+/*
+ * Ordering is (from lower to higher memory addresses):
+ *
+ * high_memory
+ * Persistent kmap area
+ * PKMAP_BASE
+ * fixed_addresses
+ * FIXADDR_START
+ * FIXADDR_TOP
+ * Vmalloc area
+ * VMALLOC_START
+ * VMALLOC_END
+ */
+#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK))
+#define LAST_PKMAP PTRS_PER_PTE
+#define LAST_PKMAP_MASK(LAST_PKMAP - 1)
+#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+#define kmap_prot  PAGE_KERNEL
+
+static inline void flush_cache_kmaps(void)
+{
+   cpu_dcache_wbinval_all();
+}
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *pkmap_page_table;
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+extern void kmap_init(void);
+
+/*
+ * The following functions are already defined by 
+ * when CONFIG_HIGHMEM is not set.
+ */
+#ifdef CONFIG_HIGHMEM
+extern void *kmap(struct page *page);
+extern void kunmap(struct page *page);
+extern void *kmap_atomic(struct page *page);
+extern void __kunmap_atomic(void *kvaddr);
+extern void *kmap_atomic_pfn(unsigned long pfn);
+extern struct page *kmap_atomic_to_page(void *ptr);
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index ..60efc726b56e
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MEMORY_H
+#define __ASM_NDS32_MEMORY_H
+
+#include 
+#include 
+
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET (0x0)
+#endif
+
+#ifndef __virt_to_bus
+#define __virt_to_bus  __virt_to_phys
+#endif
+
+#ifndef __bus_to_virt
+#define __bus_to_virt  __phys_to_virt
+#endif
+
+/*
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of 

Re: [PATCH v6 07/36] nds32: Exception handling

[Greentime Hu]

Hi, Arnd:

2018-01-30 21:33 GMT+08:00 Arnd Bergmann :
> On Tue, Jan 30, 2018 at 11:01 AM, Vincent Chen  wrote:
>> 2018-01-24 19:10 GMT+08:00 Arnd Bergmann :
>>> On Wed, Jan 24, 2018 at 12:09 PM, Arnd Bergmann  wrote:
 On Wed, Jan 24, 2018 at 11:53 AM, Vincent Chen  wrote:
> 2018-01-18 18:14 GMT+08:00 Arnd Bergmann :
>>>
 Ok. I still wonder about the kernel part of this though: is it a good idea
 for user space to configure whether the kernel does unaligned
 accesses? I would think that the kernel should just be fixed in such
 a case.
>>>
>>> To clarify: I'm asking only about unaligned accesses from kernel code 
>>> itself,
>>> which is generally considered a bug when
>>> CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is disabled.
>>>
>>>   Arnd
>>
>> Thanks for your comments.
>>
>> For performance, we decide always disable
>> CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS even if hardware supports
>> unaligned accessing. Therefore, I will remove kernel unaligned accessing from
>> nds32/mm/alignment.c. In other words, alignment.c only addresses unaligned
>> accessing for user space.
>
> I'm not really following that logic, let's go through that again so I 
> understand
> the situation better.
>
> CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS should be set if and
> only if you have a CPU that does not need to trap on unaligned accesses.
>
> What are the hardware capabilities on nds32? Do you have all three
> categories:
>
> a) some CPUs that always trap on unaligned access
> b) some CPUs that never trap on unaligned access
> c) some CPUs that can be configured to either trap or not trap by
> the kernel?
>
We have type a and c.
We use CONFIG_ALIGNMENT_TRAP for a and
CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS for c.

Since unaligned access in kernel code itself should be considered as a
bug, we will remove the emulation code to handle the kernel code
unaligned accessed case.
We think CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS and
CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS have different purposes because
it will still be more efficient to access by byte even if hardware
support unaligned access.
CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS is used to prevent generating
unaligned access exception.

Thus, we will
1. treat unaligned access in kernel code itself as a bug
2. don't select CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
3. disable CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS as default

Re: [PATCH v6 16/36] nds32: DMA mapping API

[Greentime Hu]

Hi, Arnd:

2018-01-25 18:42 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Thu, Jan 25, 2018 at 4:45 AM, Greentime Hu <green...@gmail.com> wrote:
>> 2018-01-24 19:36 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>> On Tue, Jan 23, 2018 at 12:52 PM, Greentime Hu <green...@gmail.com> wrote:
>>>> 2018-01-23 16:23 GMT+08:00 Greentime Hu <green...@gmail.com>:
>>>>> 2018-01-18 18:26 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>>>>> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>>>
>>> That looks reasonable enough, but it does depend on a number of factors,
>>> and the dma-mapping.h implementation is not just about cache flushes.
>>>
>>> As I don't know the microarchitecture, can you answer these questions:
>>>
>>> - are caches always write-back, or could they be write-through?
>> Yes, we can config it to write-back or write-through.
>
> Ok. If a WT-cache is common enough, you could optimize for that
> case by skipping the explicit writeback here and just doing a synchronizing
> instruction. Usually if the cache is configurable, one would pick the
> writeback option though, so it's probably not important.

Thank you for this suggestion.
We have optimized in cpu_dcache_wb_range() and it will be called from
cpu_dma_wb_range().
It will do nothing if it is a write-through config cache.

>>> - is the CPU physical address always the same as the address visible to the
>>>   device?
>> Yes, it is always the same unless the CPU uses local memory. The
>> physical address of local memory will overlap the original bus
>> address.
>> I think the local memory case can be ignored because we don't use it for now.
>
> Ok, makes sense.
>
>>> - are there devices that can only see a subset of the physical memory?
>> All devices are able to see the whole physical memory in our current
>> SoC, but I think other SoC may support such kind of HW behavior.
>
> This is one area that might need a more complex implementation then,
> depending on what devices are used in other SoCs. For network or
> storage devices, it's usually sufficient to configure a DMA mask
> from the "dma-ranges" property of the parent bus in the device tree,
> the kernel code will then use bounce buffers.
>
> For other types of drivers, using the streaming DMA interfaces
> can require using the swiotlb helper that performs the bounce
> buffering at in place of the cache operations. With a bit of luck,
> you won't ever need to worry about it, just mentioning it here in
> case you run into that problem later.
>
> The consistent_sync() implementaiton you showed earlier should be
> good enough then.  With that change,
>
> Acked-by: Arnd Bergmann <a...@arndb.de>

Thank you. :)

Re: [PATCH v6 16/36] nds32: DMA mapping API

[Greentime Hu]

Hi, Arnd:

2018-01-24 19:36 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Tue, Jan 23, 2018 at 12:52 PM, Greentime Hu <green...@gmail.com> wrote:
>> Hi, Arnd:
>>
>> 2018-01-23 16:23 GMT+08:00 Greentime Hu <green...@gmail.com>:
>>> Hi, Arnd:
>>>
>>> 2018-01-18 18:26 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>>> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>>>>> From: Greentime Hu <greent...@andestech.com>
>>>>>
>>>>> This patch adds support for the DMA mapping API. It uses dma_map_ops for
>>>>> flexibility.
>>>>>
>>>>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>>>>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>>>>
>>>> I'm still unhappy about the way the cache flushes are done here as 
>>>> discussed
>>>> before. It's not a show-stopped, but no Ack from me.
>>>
>>> How about this implementation?
>
>> I am not sure if I understand it correctly.
>> I list all the combinations.
>>
>> RAM to DEVICE
>> before DMA => writeback cache
>> after DMA => nop
>>
>> DEVICE to RAM
>> before DMA => nop
>> after DMA => invalidate cache
>>
>> static void consistent_sync(void *vaddr, size_t size, int direction, int 
>> master)
>> {
>> unsigned long start = (unsigned long)vaddr;
>> unsigned long end = start + size;
>>
>> if (master == FOR_CPU) {
>> switch (direction) {
>> case DMA_TO_DEVICE:
>> break;
>> case DMA_FROM_DEVICE:
>> case DMA_BIDIRECTIONAL:
>> cpu_dma_inval_range(start, end);
>> break;
>> default:
>> BUG();
>> }
>> } else {
>> /* FOR_DEVICE */
>> switch (direction) {
>> case DMA_FROM_DEVICE:
>> break;
>> case DMA_TO_DEVICE:
>> case DMA_BIDIRECTIONAL:
>> cpu_dma_wb_range(start, end);
>> break;
>> default:
>> BUG();
>> }
>> }
>> }
>
> That looks reasonable enough, but it does depend on a number of factors,
> and the dma-mapping.h implementation is not just about cache flushes.
>
> As I don't know the microarchitecture, can you answer these questions:
>
> - are caches always write-back, or could they be write-through?
Yes, we can config it to write-back or write-through.

> - can the cache be shared with another CPU or a device?
No, we don't support it.

> - if the cache is shared, is it always coherent, never coherent, or
> either of them?
We don't support SMP and the device will access memory through bus. I
think the cache is not shared.

> - could the same memory be visible at different physical addresses
>   and have conflicting caches?
We currently don't have such kind of SoC memory map.

> - is the CPU physical address always the same as the address visible to the
>   device?
Yes, it is always the same unless the CPU uses local memory. The
physical address of local memory will overlap the original bus
address.
I think the local memory case can be ignored because we don't use it for now.

> - are there devices that can only see a subset of the physical memory?
All devices are able to see the whole physical memory in our current
SoC, but I think other SoC may support such kind of HW behavior.

> - can there be an IOMMU?
No.

> - are there write-buffers in the CPU that might need to get flushed before
>   flushing the cache?
Yes, there are write-buffers in front of CPU caches but it should be
transparent to SW. We don't need to flush it.

> - could cache lines be loaded speculatively or with read-ahead while
>   a buffer is owned by a device?
No.

Re: [PATCH v6 16/36] nds32: DMA mapping API

[Greentime Hu]

Hi, Arnd:

2018-01-23 16:23 GMT+08:00 Greentime Hu <green...@gmail.com>:
> Hi, Arnd:
>
> 2018-01-18 18:26 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>>> From: Greentime Hu <greent...@andestech.com>
>>>
>>> This patch adds support for the DMA mapping API. It uses dma_map_ops for
>>> flexibility.
>>>
>>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>>
>> I'm still unhappy about the way the cache flushes are done here as discussed
>> before. It's not a show-stopped, but no Ack from me.
>
> How about this implementation?
>
> static void
> nds32_dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
>   size_t size, enum dma_data_direction dir)
> {
> switch (direction) {
> case DMA_TO_DEVICE: /* writeback only */
> break;
> case DMA_FROM_DEVICE:   /* invalidate only */
> case DMA_BIDIRECTIONAL: /* writeback and invalidate */
> cpu_dma_inval_range(start, end);
> break;
> default:
> BUG();
> }
> }
>
> static void
> nds32_dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
>  size_t size, enum dma_data_direction dir)
> {
> switch (direction) {
> case DMA_FROM_DEVICE:   /* invalidate only */
> break;
> case DMA_TO_DEVICE: /* writeback only */
> case DMA_BIDIRECTIONAL: /* writeback and invalidate */
> cpu_dma_wb_range(start, end);
> break;
> default:
> BUG();
> }
> }

I am not sure if I understand it correctly.
I list all the combinations.

RAM to DEVICE
before DMA => writeback cache
after DMA => nop

DEVICE to RAM
before DMA => nop
after DMA => invalidate cache

static void consistent_sync(void *vaddr, size_t size, int direction, int master)
{
unsigned long start = (unsigned long)vaddr;
unsigned long end = start + size;

if (master == FOR_CPU) {
switch (direction) {
case DMA_TO_DEVICE:
break;
case DMA_FROM_DEVICE:
case DMA_BIDIRECTIONAL:
cpu_dma_inval_range(start, end);
break;
default:
BUG();
}
} else {
/* FOR_DEVICE */
switch (direction) {
case DMA_FROM_DEVICE:
break;
case DMA_TO_DEVICE:
case DMA_BIDIRECTIONAL:
cpu_dma_wb_range(start, end);
break;
default:
BUG();
}
}
}

static void
nds32_dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
  size_t size, enum dma_data_direction dir)
{
consistent_sync((void *)phys_to_virt(handle), size, dir, FOR_CPU);
}

static void
nds32_dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
 size_t size, enum dma_data_direction dir)
{
consistent_sync((void *)phys_to_virt(handle), size, dir, FOR_DEVICE);
}

static dma_addr_t nds32_dma_map_page(struct device *dev, struct page *page,
 unsigned long offset, size_t size,
 enum dma_data_direction dir,
 unsigned long attrs)
{
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
consistent_sync((void *)(page_address(page) + offset),
size, dir, FOR_DEVICE);
return page_to_phys(page) + offset;
}

static void nds32_dma_unmap_page(struct device *dev, dma_addr_t handle,
 size_t size, enum dma_data_direction dir,
 unsigned long attrs)
{
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
consistent_sync(phys_to_virt(handle), size, dir, FOR_CPU);
}

Re: [PATCH v6 16/36] nds32: DMA mapping API

[Greentime Hu]

Hi, Arnd:

2018-01-18 18:26 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>> From: Greentime Hu <greent...@andestech.com>
>>
>> This patch adds support for the DMA mapping API. It uses dma_map_ops for
>> flexibility.
>>
>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>
> I'm still unhappy about the way the cache flushes are done here as discussed
> before. It's not a show-stopped, but no Ack from me.

How about this implementation?

static void
nds32_dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
  size_t size, enum dma_data_direction dir)
{
switch (direction) {
case DMA_TO_DEVICE: /* writeback only */
break;
case DMA_FROM_DEVICE:   /* invalidate only */
case DMA_BIDIRECTIONAL: /* writeback and invalidate */
cpu_dma_inval_range(start, end);
break;
default:
BUG();
}
}

static void
nds32_dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
 size_t size, enum dma_data_direction dir)
{
switch (direction) {
case DMA_FROM_DEVICE:   /* invalidate only */
break;
case DMA_TO_DEVICE: /* writeback only */
case DMA_BIDIRECTIONAL: /* writeback and invalidate */
cpu_dma_wb_range(start, end);
break;
default:
BUG();
}
}

Re: [PATCH v6 29/36] nds32: Build infrastructure

[Greentime Hu]

Hi, Arnd:

2018-01-22 23:38 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 22, 2018 at 4:20 PM, Greentime Hu <green...@gmail.com> wrote:
> BE
>>>
>>> I think it's better to drop GENERIC_IRQ_PROBE here, no modern driver
>>> should rely on that.
>>
>> I will drop it.
>>
>>>> +choice
>>>> +   prompt "CPU type"
>>>> +   default CPU_V3
>>>> +config CPU_N15
>>>> +   bool "AndesCore N15"
>>>> +config CPU_N13
>>>> +   bool "AndesCore N13"
>>>> +   select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
>>>> +config CPU_N10
>>>> +   bool "AndesCore N10"
>>>> +   select CPU_CACHE_ALIASING
>>>> +config CPU_D15
>>>> +   bool "AndesCore D15"
>>>> +config CPU_D10
>>>> +   bool "AndesCore D10"
>>>> +   select CPU_CACHE_ALIASING
>>>> +config CPU_V3
>>>> +   bool "AndesCore v3 compatible"
>>>> +   select ANDES_PAGE_SIZE_8KB
>>>> +endchoice
>>>
>>> I forget what we discussed here earlier, but at the very least, there 
>>> should be
>>> some help text here to explain what the implications are. I assume that you
>>> generally want to be able to build one kernel to run on all of the above, 
>>> right?
>>>
>>> Will selecting 'CPU_V3' result in a kernel binary that can run on all of 
>>> them?
>>> If so, please explain it here as that is not obvious.
>>>
>>> For the other CPU types, can you list the what backwards-compatiblity
>>> you get? E.g. will a kernel built for N13 run on any of N15, D15 or N10?
>>>
>> Yes, we would like to build a kernel with CPU_V3 to run on all of the above.
>>
>> Not sure if these help texts clear enough?
>>
>> choice
>> prompt "CPU type"
>> default CPU_V3
>> help
>>   The data cache of N15/D15 is implemented as PIPT and it will
>> not cause the
>>   cache aliasing issue. The rest cpus(N13, N10 and D10) are
>> implemented as
>>   VIPT data cache. It may cause the cache aliasing issue if
>> its cache way
>>   size is larger than page size. You can specify the the CPU
>> type direcly or
>>   choose CPU_V3 if unsure.
>>
>>   A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
>>   A kernel built for N15 is able to run on N15 or D15.
>>   A kernel built for D10 is able to run on D10 or D15.
>>   A kernel built for D15 is able to run on D15.
>>   A kernel built for N13 with CPU_CACHE_ALIASING is able to
>> run on N15, D15, N13, N10 or D10
>>   A kernel built for N13 without CPU_CACHE_ALIASING is able to
>> run on N15, N13 or D15
>>
>> config CPU_N15
>> bool "AndesCore N15"
>> config CPU_N13
>> bool "AndesCore N13"
>> select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
>> config CPU_N10
>> bool "AndesCore N10"
>> select CPU_CACHE_ALIASING
>> config CPU_D15
>> bool "AndesCore D15"
>> config CPU_D10
>> bool "AndesCore D10"
>> select CPU_CACHE_ALIASING
>> config CPU_V3
>> bool "AndesCore v3 compatible"
>> select CPU_CACHE_ALIASING
>> endchoice
>
> I would drop the description about CPU_CACHE_ALIASING in the list
> of compatibilities text and simply say 'A kernel built for N13 is able to run
> on N15, N13 or D15', it's more logical that way, and it gives you the freedom
> to later change the rules about whether it can or cannot run.
>
> Maybe also change the initial prompt from "CPU type" to "minimum CPU type".
>

Thank you for your suggestion.
I will update it like this.

choice
prompt "minimum CPU type"
default CPU_V3
help
  The data cache of N15/D15 is implemented as PIPT and it will not cause
  the cache aliasing issue. The rest cpus(N13, N10 and D10) are
  implemented as VIPT data cache. It may cause the cache aliasing issue
  if its cache way size is larger than page size. You can specify the
  CPU type direcly or choose CPU_V3 if unsure.

  A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
  A kernel built for N15 is able to run on N15 or D15.
  A kernel built for D10 is able to run on D10 or D15.
  A kernel built for D15 is able to run on D15.
  A kernel built for N13 is able to run on N15, N13 or D15.

config CPU_N15
bool "AndesCore N15"
config CPU_N13
bool "AndesCore N13"
select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
config CPU_N10
bool "AndesCore N10"
select CPU_CACHE_ALIASING
config CPU_D15
bool "AndesCore D15"
config CPU_D10
bool "AndesCore D10"
select CPU_CACHE_ALIASING
config CPU_V3
bool "AndesCore v3 compatible"
select CPU_CACHE_ALIASING
endchoice

Re: [PATCH v6 29/36] nds32: Build infrastructure

[Greentime Hu]

Hi, Arnd:

2018-01-18 19:00 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>> From: Greentime Hu <greent...@andestech.com>
>>
>> This patch adds Makefile, Kconfig and vmlinux.lds.S files required for 
>> building
>> an nds32 kernel.
>>
>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>
> I find some new details every time I look here ;-)

Thank you for revewing so detailedly. :)

>> @@ -0,0 +1,107 @@
>> +#
>> +# For a description of the syntax of this configuration file,
>> +# see Documentation/kbuild/kconfig-language.txt.
>> +#
>> +
>> +config NDS32
>> +def_bool y
>> +   select ARCH_HAS_RAW_COPY_USER
>
> I don't think this symbol was ever merged. Do you remember why you added it?

I will drop it. It must be added in earlier kernel version.

>> +   select ARCH_WANT_FRAME_POINTERS if FTRACE
>> +   select ARCH_WANT_IPC_PARSE_VERSION
>
> You most certainly don't want IPC_PARSE_VERSION, please drop this
> and adapt your glibc.

ok. I will drop it.

>> +   select CLKSRC_MMIO
>> +   select CLONE_BACKWARDS
>> +   select COMMON_CLK
>> +   select FRAME_POINTER
>
> Do you need both ARCH_WANT_FRAME_POINTERS and FRAME_POINTER here?

I will drop FRAME_POINTER.

>> +   select GENERIC_ATOMIC64
>> +   select GENERIC_CPU_DEVICES
>> +   select GENERIC_CLOCKEVENTS
>> +   select GENERIC_IRQ_CHIP
>> +   select GENERIC_IRQ_PROBE
>
> I think it's better to drop GENERIC_IRQ_PROBE here, no modern driver
> should rely on that.

I will drop it.

>> +choice
>> +   prompt "CPU type"
>> +   default CPU_V3
>> +config CPU_N15
>> +   bool "AndesCore N15"
>> +config CPU_N13
>> +   bool "AndesCore N13"
>> +   select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
>> +config CPU_N10
>> +   bool "AndesCore N10"
>> +   select CPU_CACHE_ALIASING
>> +config CPU_D15
>> +   bool "AndesCore D15"
>> +config CPU_D10
>> +   bool "AndesCore D10"
>> +   select CPU_CACHE_ALIASING
>> +config CPU_V3
>> +   bool "AndesCore v3 compatible"
>> +   select ANDES_PAGE_SIZE_8KB
>> +endchoice
>
> I forget what we discussed here earlier, but at the very least, there should 
> be
> some help text here to explain what the implications are. I assume that you
> generally want to be able to build one kernel to run on all of the above, 
> right?
>
> Will selecting 'CPU_V3' result in a kernel binary that can run on all of them?
> If so, please explain it here as that is not obvious.
>
> For the other CPU types, can you list the what backwards-compatiblity
> you get? E.g. will a kernel built for N13 run on any of N15, D15 or N10?
>
Yes, we would like to build a kernel with CPU_V3 to run on all of the above.

Not sure if these help texts clear enough?

choice
prompt "CPU type"
default CPU_V3
help
  The data cache of N15/D15 is implemented as PIPT and it will
not cause the
  cache aliasing issue. The rest cpus(N13, N10 and D10) are
implemented as
  VIPT data cache. It may cause the cache aliasing issue if
its cache way
  size is larger than page size. You can specify the the CPU
type direcly or
  choose CPU_V3 if unsure.

  A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
  A kernel built for N15 is able to run on N15 or D15.
  A kernel built for D10 is able to run on D10 or D15.
  A kernel built for D15 is able to run on D15.
  A kernel built for N13 with CPU_CACHE_ALIASING is able to
run on N15, D15, N13, N10 or D10
  A kernel built for N13 without CPU_CACHE_ALIASING is able to
run on N15, N13 or D15

config CPU_N15
bool "AndesCore N15"
config CPU_N13
bool "AndesCore N13"
select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
config CPU_N10
bool "AndesCore N10"
select CPU_CACHE_ALIASING
config CPU_D15
bool "AndesCore D15"
config CPU_D10
bool "AndesCore D10"
select CPU_CACHE_ALIASING
config CPU_V3
bool "AndesCore v3 compatible"
select CPU_CACHE_ALIASING
endchoice

> I think the 'select ANDES_PAGE_SIZE_8KB' cannot work as expected,
> since ANDES_PAGE_SIZE_8KB is inside of a 'choice' statement. Since
> there are only two options (4K and 8K), you can address that by making
> it a simple bool option and f

Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

Hi, Arnd:

2018-01-22 19:15 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 22, 2018 at 10:53 AM, Greentime Hu <green...@gmail.com> wrote:
>> 2018-01-19 23:37 GMT+08:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
>>> On Fri, Jan 19, 2018 at 4:35 PM, Greentime Hu <green...@gmail.com> wrote:
>>>> 2018-01-19 23:29 GMT+08:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
>>>>> On Fri, Jan 19, 2018 at 4:18 PM, Greentime Hu <green...@gmail.com> wrote:
>
>>>> Thank you and your example.
>>>> I get it. I will update this document like this.
>>>> - compatible: Should be "andestech,", "andestech,nds32v3"
>>>> as fallback.
>>>
>>> And please keep a list of supported values of "andestech,"
>>> in the DT binding document, so checkpatch can validate compatible values.
>>>
>>
>> Thank you for reminding me this.
>> I will list it like this.
>>
>> - compatible:
>> Usage: required
>> Value type: 
>> Definition: Should be "andestech,",
>> "andestech,nds32v3" as fallback.
>> Examlpes with core_names are:
>> "andestech,n13"
>> "andestech,n15"
>> "andestech,d15"
>> "andestech,n10"
>> "andestech,d10"
>
> This is still not written as a proper specification, you should not
> give "examples"
> but give a complete list of the available options. You could write it like:
>
> Must contain "andestech,nds32v3" as the most generic value, in addition to
> one of the following identifiers for a particular CPU core:
>  "andestech,n13"
>  "andestech,n15"
>  "andestech,d15"
>  "andestech,n10"
>  "andestech,d10"
>
> It might be helpful to also list all other existing nds32v3 cores,
> even those that the
> current Linux port does not support them.
>

Thank you for the clear explanation.
I will update it just like you wrote.

Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

Hi, Geert:

2018-01-19 23:37 GMT+08:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi Greentime,
>
> On Fri, Jan 19, 2018 at 4:35 PM, Greentime Hu <green...@gmail.com> wrote:
>> 2018-01-19 23:29 GMT+08:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
>>> On Fri, Jan 19, 2018 at 4:18 PM, Greentime Hu <green...@gmail.com> wrote:
>>>> 2018-01-19 22:52 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>>>> On Fri, Jan 19, 2018 at 3:32 PM, Greentime Hu <green...@gmail.com> wrote:
>>>>>> 2018-01-18 19:02 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>>>>>> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> 
>>>>>>> wrote:
>>>>>>>> From: Greentime Hu <greent...@andestech.com>
>>>>>>>>
>>>>>>>> This patch adds nds32 CPU binding documents.
>>>>>>>>
>>>>>>>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>>>>>>>> Signed-off-by: Rick Chen <r...@andestech.com>
>>>>>>>> Signed-off-by: Zong Li <z...@andestech.com>
>>>>>>>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>>>>>>>> Reviewed-by: Rob Herring <r...@kernel.org>
>>>>>>>> ---
>>>>>>>>  Documentation/devicetree/bindings/nds32/cpus.txt |   37 
>>>>>>>> ++
>>>>>>>>  1 file changed, 37 insertions(+)
>>>>>>>>  create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
>>>>>>>>
>>>>>>>> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
>>>>>>>> b/Documentation/devicetree/bindings/nds32/cpus.txt
>>>>>>>> new file mode 100644
>>>>>>>> index 000..9a52937
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt
>>>>>>>> @@ -0,0 +1,37 @@
>>>>>>>> +* Andestech Processor Binding
>>>>>>>> +
>>>>>>>> +This binding specifies what properties must be available in the 
>>>>>>>> device tree
>>>>>>>> +representation of a Andestech Processor Core, which is the root node 
>>>>>>>> in the
>>>>>>>> +tree.
>>>>>>>> +
>>>>>>>> +Required properties:
>>>>>>>> +
>>>>>>>> +   - compatible:
>>>>>>>> +   Usage: required
>>>>>>>> +   Value type: 
>>>>>>>> +   Definition: should be one of:
>>>>>>>> +   "andestech,n13"
>>>>>>>> +   "andestech,n15"
>>>>>>>> +   "andestech,d15"
>>>>>>>> +   "andestech,n10"
>>>>>>>> +   "andestech,d10"
>>>>>>>> +   "andestech,nds32v3"
>>>>>>>
>>>>>>> Based on https://lkml.org/lkml/2017/11/27/1290, this should say that
>>>>>>> the device tree should always list 'andestech,nds32v3' as the most
>>>>>>> generic 'compatible' value and list exactly one of the others in
>>>>>>> addition.
>>>>>
>>>>>> I will remove the others and just left "andestech,nds32v3" in here.
>>>>>
>>>>> No, is not what we want here, the CPU node should list exactly which core
>>>>> is used, what we need in the description is a clarification that
>>>>> andestech,nds32v3 must be used in addition to the more specific
>>>>> string.
>>>>
>>>> Hi, Arnd:
>>>>
>>>> Sorry I still don't get your point. Do you mean we should always use
>>>> compatible = "andestech,n13", "andestech,nds32v3";
>>>> instead of
>>>> compatible = "andestech,n13";
>>>
>>> Exactly. The first value is a device-specific compatible value, the second 
>>> is
>>> a generic fallback.
>>>
>>>> And I need to add the description in this document.
>>>
>>> Indeed. See for example
>>> Documentation/devicetree/bindings/power/renesas,apmu.txt
>>>
>>> Thanks!
>>
>> Hi, Geert:
>>
>> Thank you and your example.
>> I get it. I will update this document like this.
>> - compatible: Should be "andestech,", "andestech,nds32v3"
>> as fallback.
>
> And please keep a list of supported values of "andestech,"
> in the DT binding document, so checkpatch can validate compatible values.
>

Thank you for reminding me this.
I will list it like this.

- compatible:
Usage: required
Value type: 
Definition: Should be "andestech,",
"andestech,nds32v3" as fallback.
Examlpes with core_names are:
"andestech,n13"
"andestech,n15"
"andestech,d15"
"andestech,n10"
"andestech,d10"

Re: [PATCH v6 06/36] nds32: Kernel booting and initialization

[Greentime Hu]

2018-01-20 0:41 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Fri, Jan 19, 2018 at 5:34 PM, Greentime Hu <green...@gmail.com> wrote:
>> Hi, Arnd:
>>
>> 2018-01-18 18:11 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>>>
>>> I had not looked at this patch in enough detail earlier, sorry about
>>> that. It should be
>>> easy enough to fix though.
>>>
>>>> +#ifdef CONFIG_VGA_CONSOLE
>>>> +struct screen_info screen_info;
>>>> +#endif
>>>
>>> I would assume that you can't ever have a VGA console. Just drop all
>>> the references
>>> here and instead send a patch to the fbdev maintainer to add the dependency
>>> at CONFIG_VGA_CONSOLE to prevent selecting it with nds32.
>>
>> I found it can be built pass for now because we disable it in defconfig.
>> Should I send the patch in v7 series?
>
> yes, I think that would be best.
>
>>>> +
>>>> +extern void __init early_init_devtree(void *params);
>>>> +extern void __init early_trap_init(void);
>>>
>>> similarly, these are declared in include/linux/of_fdt.h
>>>
>>
>> early_trap_init is a nds32 function. I will move it to nds32.h
>
> Right, makes sense.
>
>>>> +void calibrate_delay(void)
>>>> +{
>>>> +   const int *val;
>>>> +   struct device_node *cpu = NULL;
>>>> +   cpu = of_find_compatible_node(NULL, NULL, "andestech,nds32v3");
>>>> +   val = of_get_property(cpu, "clock-frequency", NULL);
>>>> +   if (!val || !*val)
>>>> +   panic("no cpu 'clock-frequency' parameter in device tree");
>>>> +   loops_per_jiffy = be32_to_cpup(val) / HZ;
>>>> +   pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
>>>> +   loops_per_jiffy / (50 / HZ),
>>>> +   (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
>>>> +}
>>>
>>> This seems very odd to me: The 'clock-frequency' property in the
>>> cpu node should refer to the actual frequency it is running at, but that
>>> tends to be different from the bogomips as needed by the ndelay()
>>> function. Can you explain what is going on here?
>>>
>>
>> This implementation is referenced from openrisc.
>> https://lkml.org/lkml/2017/11/17/228
>
> It's correct on openrisc, because that has a reliable cycle counter,
> and that gets used in its delay function:
>
> void __delay(unsigned long cycles)
> {
> cycles_t start = get_cycles();
> while ((get_cycles() - start) < cycles)
> cpu_relax();
> }
>
> In my review comment that you cited, I assumed that nds32 had similar
> hardware.
>
> However, as you explained earlier, the nds32 architecture does not provide
> a cycle counter and the clocksource resolution is not high enough to
> be a good replacement, so you have to use the traditional delay
> calibration.
>

Hi, Arnd:

Thank you for your explanation.
Will it be ok if I code it like this?

config GENERIC_CALIBRATE_DELAY
   def_bool y

Re: [PATCH v6 06/36] nds32: Kernel booting and initialization

[Greentime Hu]

Hi, Arnd:

2018-01-18 18:11 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>
> I had not looked at this patch in enough detail earlier, sorry about
> that. It should be
> easy enough to fix though.
>
>> +#ifdef CONFIG_VGA_CONSOLE
>> +struct screen_info screen_info;
>> +#endif
>
> I would assume that you can't ever have a VGA console. Just drop all
> the references
> here and instead send a patch to the fbdev maintainer to add the dependency
> at CONFIG_VGA_CONSOLE to prevent selecting it with nds32.

I found it can be built pass for now because we disable it in defconfig.
Should I send the patch in v7 series?

>> +
>> +extern void __init early_init_devtree(void *params);
>> +extern void __init early_trap_init(void);
>
> similarly, these are declared in include/linux/of_fdt.h
>

early_trap_init is a nds32 function. I will move it to nds32.h

>> +void __init setup_arch(char **cmdline_p)
>> +{
>> +   early_init_devtree(__atags_pointer ?
>> +  phys_to_virt(__atags_pointer) : __dtb_start);
>
> The reference to '__atags_pointer' appears to be a leftover from pre-DT
> days. Can you just remove that?

Yes, I will remove it.

>> +void calibrate_delay(void)
>> +{
>> +   const int *val;
>> +   struct device_node *cpu = NULL;
>> +   cpu = of_find_compatible_node(NULL, NULL, "andestech,nds32v3");
>> +   val = of_get_property(cpu, "clock-frequency", NULL);
>> +   if (!val || !*val)
>> +   panic("no cpu 'clock-frequency' parameter in device tree");
>> +   loops_per_jiffy = be32_to_cpup(val) / HZ;
>> +   pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
>> +   loops_per_jiffy / (50 / HZ),
>> +   (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
>> +}
>
> This seems very odd to me: The 'clock-frequency' property in the
> cpu node should refer to the actual frequency it is running at, but that
> tends to be different from the bogomips as needed by the ndelay()
> function. Can you explain what is going on here?
>

This implementation is referenced from openrisc.
https://lkml.org/lkml/2017/11/17/228



Thank you.

Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

2018-01-19 23:29 GMT+08:00 Geert Uytterhoeven <ge...@linux-m68k.org>:
> Hi Greentime,
>
> On Fri, Jan 19, 2018 at 4:18 PM, Greentime Hu <green...@gmail.com> wrote:
>> 2018-01-19 22:52 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>> On Fri, Jan 19, 2018 at 3:32 PM, Greentime Hu <green...@gmail.com> wrote:
>>>> 2018-01-18 19:02 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>>>> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>>>>>> From: Greentime Hu <greent...@andestech.com>
>>>>>>
>>>>>> This patch adds nds32 CPU binding documents.
>>>>>>
>>>>>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>>>>>> Signed-off-by: Rick Chen <r...@andestech.com>
>>>>>> Signed-off-by: Zong Li <z...@andestech.com>
>>>>>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>>>>>> Reviewed-by: Rob Herring <r...@kernel.org>
>>>>>> ---
>>>>>>  Documentation/devicetree/bindings/nds32/cpus.txt |   37 
>>>>>> ++
>>>>>>  1 file changed, 37 insertions(+)
>>>>>>  create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
>>>>>> b/Documentation/devicetree/bindings/nds32/cpus.txt
>>>>>> new file mode 100644
>>>>>> index 000..9a52937
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt
>>>>>> @@ -0,0 +1,37 @@
>>>>>> +* Andestech Processor Binding
>>>>>> +
>>>>>> +This binding specifies what properties must be available in the device 
>>>>>> tree
>>>>>> +representation of a Andestech Processor Core, which is the root node in 
>>>>>> the
>>>>>> +tree.
>>>>>> +
>>>>>> +Required properties:
>>>>>> +
>>>>>> +   - compatible:
>>>>>> +   Usage: required
>>>>>> +   Value type: 
>>>>>> +   Definition: should be one of:
>>>>>> +   "andestech,n13"
>>>>>> +   "andestech,n15"
>>>>>> +   "andestech,d15"
>>>>>> +   "andestech,n10"
>>>>>> +   "andestech,d10"
>>>>>> +   "andestech,nds32v3"
>>>>>
>>>>> Based on https://lkml.org/lkml/2017/11/27/1290, this should say that
>>>>> the device tree should always list 'andestech,nds32v3' as the most
>>>>> generic 'compatible' value and list exactly one of the others in
>>>>> addition.
>>>
>>>> I will remove the others and just left "andestech,nds32v3" in here.
>>>
>>> No, is not what we want here, the CPU node should list exactly which core
>>> is used, what we need in the description is a clarification that
>>> andestech,nds32v3 must be used in addition to the more specific
>>> string.
>>
>> Hi, Arnd:
>>
>> Sorry I still don't get your point. Do you mean we should always use
>> compatible = "andestech,n13", "andestech,nds32v3";
>> instead of
>> compatible = "andestech,n13";
>
> Exactly. The first value is a device-specific compatible value, the second is
> a generic fallback.
>
>> And I need to add the description in this document.
>
> Indeed. See for example
> Documentation/devicetree/bindings/power/renesas,apmu.txt
>
> Thanks!

Hi, Geert:

Thank you and your example.
I get it. I will update this document like this.
- compatible: Should be "andestech,", "andestech,nds32v3"
as fallback.

Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

2018-01-19 22:52 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Fri, Jan 19, 2018 at 3:32 PM, Greentime Hu <green...@gmail.com> wrote:
>> 2018-01-18 19:02 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
>>> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>>>> From: Greentime Hu <greent...@andestech.com>
>>>>
>>>> This patch adds nds32 CPU binding documents.
>>>>
>>>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>>>> Signed-off-by: Rick Chen <r...@andestech.com>
>>>> Signed-off-by: Zong Li <z...@andestech.com>
>>>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>>>> Reviewed-by: Rob Herring <r...@kernel.org>
>>>> ---
>>>>  Documentation/devicetree/bindings/nds32/cpus.txt |   37 
>>>> ++
>>>>  1 file changed, 37 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
>>>> b/Documentation/devicetree/bindings/nds32/cpus.txt
>>>> new file mode 100644
>>>> index 000..9a52937
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt
>>>> @@ -0,0 +1,37 @@
>>>> +* Andestech Processor Binding
>>>> +
>>>> +This binding specifies what properties must be available in the device 
>>>> tree
>>>> +representation of a Andestech Processor Core, which is the root node in 
>>>> the
>>>> +tree.
>>>> +
>>>> +Required properties:
>>>> +
>>>> +   - compatible:
>>>> +   Usage: required
>>>> +   Value type: 
>>>> +   Definition: should be one of:
>>>> +   "andestech,n13"
>>>> +   "andestech,n15"
>>>> +   "andestech,d15"
>>>> +   "andestech,n10"
>>>> +   "andestech,d10"
>>>> +   "andestech,nds32v3"
>>>
>>> Based on https://lkml.org/lkml/2017/11/27/1290, this should say that
>>> the device tree should always list 'andestech,nds32v3' as the most
>>> generic 'compatible' value and list exactly one of the others in
>>> addition.
>
>> I will remove the others and just left "andestech,nds32v3" in here.
>
> No, is not what we want here, the CPU node should list exactly which core
> is used, what we need in the description is a clarification that
> andestech,nds32v3 must be used in addition to the more specific
> string.

Hi, Arnd:

Sorry I still don't get your point. Do you mean we should always use
compatible = "andestech,n13", "andestech,nds32v3";
instead of
compatible = "andestech,n13";

And I need to add the description in this document.

Re: [PATCH v6 31/36] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

2018-01-18 19:02 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>> From: Greentime Hu <greent...@andestech.com>
>>
>> This patch adds nds32 CPU binding documents.
>>
>> Signed-off-by: Vincent Chen <vince...@andestech.com>
>> Signed-off-by: Rick Chen <r...@andestech.com>
>> Signed-off-by: Zong Li <z...@andestech.com>
>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>> Reviewed-by: Rob Herring <r...@kernel.org>
>> ---
>>  Documentation/devicetree/bindings/nds32/cpus.txt |   37 
>> ++
>>  1 file changed, 37 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
>>
>> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
>> b/Documentation/devicetree/bindings/nds32/cpus.txt
>> new file mode 100644
>> index 000..9a52937
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt
>> @@ -0,0 +1,37 @@
>> +* Andestech Processor Binding
>> +
>> +This binding specifies what properties must be available in the device tree
>> +representation of a Andestech Processor Core, which is the root node in the
>> +tree.
>> +
>> +Required properties:
>> +
>> +   - compatible:
>> +   Usage: required
>> +   Value type: 
>> +   Definition: should be one of:
>> +   "andestech,n13"
>> +   "andestech,n15"
>> +   "andestech,d15"
>> +   "andestech,n10"
>> +   "andestech,d10"
>> +   "andestech,nds32v3"
>
> Based on https://lkml.org/lkml/2017/11/27/1290, this should say that
> the device tree should always list 'andestech,nds32v3' as the most
> generic 'compatible' value and list exactly one of the others in
> addition.
>
>Arnd

Hi, Arnd:

I will remove the others and just left "andestech,nds32v3" in here.

Re: [PATCH v6 24/36] nds32: Loadable modules

[Greentime Hu]

2018-01-18 18:41 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>> From: Greentime Hu <greent...@andestech.com>
>>
>> This patch adds support for loadable modules.
>
> One detail:
>
> You still seem to have both the ELF_REL and ELF_RELA based functions
> implemented here, you should drop the unused ELF_REL version:
>
>> diff --git a/arch/nds32/kernel/module.c b/arch/nds32/kernel/module.c
>> new file mode 100644
>> index 000..714a6d6
>> --- /dev/null
>> +++ b/arch/nds32/kernel/module.c
>> @@ -0,0 +1,286 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (C) 2005-2017 Andes Technology Corporation
>> +
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>
> include  to catch this.
>
>> +int
>> +apply_relocate(Elf32_Shdr * sechdrs, const char *strtab,
>> +  unsigned int symindex, unsigned int relsec,
>> +  struct module *module)
>> +{
>> +   return 0;
>> +}
>
> and drop this.
>
> With that change,
>
> Acked-by:  Arnd Bergmann <a...@arndb.de>

Hi, Arnd:

Thank you. I will include moduleloader.h and drop apply_relocate().

Re: [PATCH v6 03/36] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

[Greentime Hu]

2018-01-18 17:56 GMT+08:00 Arnd Bergmann <a...@arndb.de>:
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu <green...@gmail.com> wrote:
>> From: Greentime Hu <greent...@andestech.com>
>>
>> It will be built failed if commit id: d25ea659 is selected. This patch
>> can fix this build error.
>>
>> Signed-off-by: Greentime Hu <greent...@andestech.com>
>
> The change is fine, but the reference to commit 'd25ea659' is not for
> two reasons:
>
> - when you rebase the tree, you will get a different ID
> - the recommended format for referring to another commit is to list it with
>   12 digits and the one-line summary like this:
>
>commit d25ea659bc37 ("asm-generic/io.h: move
>   ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_…")
>
> - Ideally you use a 'Fixes:' tag in the patch description.
>
> You can add these lines in your .gitconfig to help you here
>
> [alias]
> fixes = show --format='Fixes: %h (\"%s\")' -s
> [core]
> abbrev = 12
>
> That will give you a 'git fixes' command to output the Fixes: line
> in the correct format for future bug fixes. For this particular change,
> I would actually just merge the two patches into one patch that
> then doesn't break anything in the first place.
>

Hi, Arnd:

Thank you for your comments and teaching me how to add these messages.
I will update the commit messages and my .gitconfig.

Since the commit id will be changed after rebasing, I will update the
messages like this.

sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

A commit for the nds32 architecture bootstrap("asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU")
will move the ioremap_nocache out of the CONFIG_MMU ifdef. This means that
in order to suppress re-definition errors we need to remove the #define
in io_32.h.

Also, the change adds a prototype for ioremap where size is size_t and
offset is phys_addr_t so fix that as well.

Signed-off-by: Greentime Hu <greent...@andestech.com>

Re: [PATCH v6 02/36] openrisc: add ioremap_nocache declaration before include asm-generic/io.h and sync ioremap prototype with it.

[Greentime Hu]

2018-01-15 21:07 GMT+08:00 Stafford Horne <sho...@gmail.com>:
> On Mon, Jan 15, 2018 at 01:53:10PM +0800, Greentime Hu wrote:
>> From: Greentime Hu <greent...@andestech.com>
>>
>> It will be built failed if commit id: d25ea659 is selected. This patch can 
>> fix this
>> build error.
>
> Hello,
>
> As I mentioned last time, can you you change this to not mention the commit 
> id?
> The ID will probably change when this is actually committed.  You might want 
> to
> do something like:
>
>  1. Move this commit before the ioremap_nocache change.  This is because we 
> want
>  each commit to result in a buildable kernel.
>
>  2. The text here and other changes could read:
>
>  A future commit for the nds32 architecture bootstrap ("asm-generic/io.h: move
>  ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU")
>  will move the ioremap_nocache out of the CONFIG_MMU ifdef.  This means that
>  in order to suppress re-definition errors we need to setup #define's before
>  importing asm-generic/io.h.
>
>  Also, the change adds a prototype for ioremap where size is size_t so fix 
> that
>  as well.
>
> I hope that helps. But for the change:
>
> Acked-by: Stafford Horne <sho...@gmail.com>
>

Hi, Stafford:

Thanks for the feedback.
I will move this commit before the ioremap_nocache change and use
these commit messages.

[PATCH v6 00/36] Andes(nds32) Linux Kernel Port

[Greentime Hu]

 - Select COMMON_CLK
 - Add clk_pll in dts
 - Add of_clk_init() in arch/nds32/kernel/time.c

Changes in v2:
 - Set GENERIC_CALIBRATE_DELAY default n
 - Add earlycon support
 - Remove earlyprintk
 - Add CPU_BIG_ENDIAN, CPU_LITTLE_ENDIAN support
 - Refine unalignment access exception handler
 - Add VMSPLIT support
 - Use only one defconfig
 - Change interrupt-cells from 2 to 1
 - Refine andestech cpu names in bindings/nds32/cpus.txt
 - Get clock frequency in dts because fpga bitmap doesn't include this feature
 - Update MAINTAINERS for bindings
 - Remove unused configs in Kconfig
 - Refine device tree scripts
 - Refine coding style
 - Use generic ioremap_nocache
 - Remove L2CC_PA_BASE define and its codes in head.S. It will be moved to 
bootloader.
 - Set PHYS_OFFSET to 0x0 instead of CONFIG_MEMORY_START
 - Remove unused macros
 - Simplify cpu_cache_* API
 - Change __asm__ __volatile__ to asm volatile
 - Refine uaccess.h
 - Remove unused/deprecated syscall
 - Use generic posix_types.h
 - Remove arch_trace_hardirqs_on/arch_trace_hardirqs_off
 - Fix bug of restart syscall
 - Refine syscall implementations
 - Use IS_ENABLED to replace ifdef as possible
 - Remove device_initcall(nds32_device_probe)
 - Refine vdso implementations
 - Refine 
copy_from_user()/copy_to_user()/clear_user()/get_user()/memmove()/memcpy()
 - Refine ioremap.c
 - Refine irq-ativic32.c
 - Fix a bug of earlycon.c
 - Export ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt
 - Add atcpit100 driver

Greentime Hu (36):
  asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
CONFIG_MMU
  openrisc: add ioremap_nocache declaration before include
asm-generic/io.h and sync ioremap prototype with it.
  sparc: io: To use the define of ioremap_[nocache|wc|wb] in
asm-generic/io.h
  earlycon: add reg-offset to physical address before mapping
  nds32: Assembly macros and definitions
  nds32: Kernel booting and initialization
  nds32: Exception handling
  nds32: MMU definitions
  nds32: MMU initialization
  nds32: MMU fault handling and page table management
  nds32: Cache and TLB routines
  nds32: Process management
  nds32: IRQ handling
  nds32: Atomic operations
  nds32: Device specific operations
  nds32: DMA mapping API
  nds32: ELF definitions
  nds32: System calls handling
  nds32: VDSO support
  nds32: Signal handling support
  nds32: Library functions
  nds32: Debugging support
  nds32: L2 cache support
  nds32: Loadable modules
  nds32: Generic timers support
  nds32: Device tree support
  nds32: Miscellaneous header files
  nds32: defconfig
  nds32: Build infrastructure
  MAINTAINERS: Add nds32
  dt-bindings: nds32 CPU Bindings
  dt-bindings: nds32 L2 cache controller Bindings
  dt-bindings: nds32 SoC Bindings
  dt-bindings: interrupt-controller: Andestech Internal Vector
Interrupt Controller
  irqchip: Andestech Internal Vector Interrupt Controller driver
  net: faraday add nds32 support.

 .../interrupt-controller/andestech,ativic32.txt|   19 +
 .../devicetree/bindings/nds32/andestech-boards |   40 +
 Documentation/devicetree/bindings/nds32/atl2c.txt  |   29 +
 Documentation/devicetree/bindings/nds32/cpus.txt   |   37 +
 MAINTAINERS|   11 +
 arch/nds32/Kconfig |  107 +++
 arch/nds32/Kconfig.cpu |  161 
 arch/nds32/Makefile|   66 ++
 arch/nds32/boot/Makefile   |   15 +
 arch/nds32/boot/dts/Makefile   |8 +
 arch/nds32/boot/dts/ae3xx.dts  |   85 ++
 arch/nds32/configs/defconfig   |  107 +++
 arch/nds32/include/asm/Kbuild  |   54 ++
 arch/nds32/include/asm/assembler.h |   39 +
 arch/nds32/include/asm/barrier.h   |   15 +
 arch/nds32/include/asm/bitfield.h  |  963 
 arch/nds32/include/asm/cache.h |   12 +
 arch/nds32/include/asm/cache_info.h|   13 +
 arch/nds32/include/asm/cacheflush.h|   44 +
 arch/nds32/include/asm/current.h   |   12 +
 arch/nds32/include/asm/delay.h |   39 +
 arch/nds32/include/asm/dma-mapping.h   |   14 +
 arch/nds32/include/asm/elf.h   |  171 
 arch/nds32/include/asm/fixmap.h|   29 +
 arch/nds32/include/asm/futex.h |  103 +++
 arch/nds32/include/asm/highmem.h   |   65 ++
 arch/nds32/include/asm/io.h|   83 ++
 arch/nds32/include/asm/irqflags.h  |   36 +
 arch/nds32/include/asm/l2_cache.h  |  137 +++
 arch/nds32/include/asm/linkage.h   |   11 +
 arch/nds32/include/asm/memory.h|  105 +++
 arch/nds32/include/asm/mmu.h   |   12 +
 arch/nds32/include/asm/mmu_context.h  

[PATCH v6 03/36] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

It will be built failed if commit id: d25ea659 is selected. This patch
can fix this build error.

Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/sparc/include/asm/io_32.h |5 -
 arch/sparc/kernel/ioport.c |4 ++--
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index cd51a89..df2dc17 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -127,12 +127,7 @@ static inline void sbus_memcpy_toio(volatile void __iomem 
*dst,
  * Bus number may be embedded in the higher bits of the physical address.
  * This is why we have no bus number argument to ioremap().
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size);
-#define ioremap_nocache(X,Y)   ioremap((X),(Y))
-#define ioremap_wc(X,Y)ioremap((X),(Y))
-#define ioremap_wt(X,Y)ioremap((X),(Y))
 void iounmap(volatile void __iomem *addr);
-
 /* Create a virtual mapping cookie for an IO port range */
 void __iomem *ioport_map(unsigned long port, unsigned int nr);
 void ioport_unmap(void __iomem *);
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 7eeef80..3bcef9c 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -122,12 +122,12 @@ static void xres_free(struct xresource *xrp) {
  *
  * Bus type is always zero on IIep.
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size)
+void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
char name[14];
 
sprintf(name, "phys_%08x", (u32)offset);
-   return _sparc_alloc_io(0, offset, size, name);
+   return _sparc_alloc_io(0, (unsigned long)offset, size, name);
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
1.7.9.5

[PATCH v6 01/36] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

It allows some architectures to use this generic macro instead of
defining theirs.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Acked-by: Arnd Bergmann <a...@arndb.de>
---
 include/asm-generic/io.h |   18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b4531e3..7c6a39e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -852,7 +852,16 @@ static inline void __iomem *__ioremap(phys_addr_t offset, 
size_t size,
 }
 #endif
 
+#ifndef iounmap
+#define iounmap iounmap
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+#endif
+#endif /* CONFIG_MMU */
 #ifndef ioremap_nocache
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
 #define ioremap_nocache ioremap_nocache
 static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
 {
@@ -884,15 +893,6 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, 
size_t size)
 }
 #endif
 
-#ifndef iounmap
-#define iounmap iounmap
-
-static inline void iounmap(void __iomem *addr)
-{
-}
-#endif
-#endif /* CONFIG_MMU */
-
 #ifdef CONFIG_HAS_IOPORT_MAP
 #ifndef CONFIG_GENERIC_IOMAP
 #ifndef ioport_map
-- 
1.7.9.5

[PATCH v6 02/36] openrisc: add ioremap_nocache declaration before include asm-generic/io.h and sync ioremap prototype with it.

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

It will be built failed if commit id: d25ea659 is selected. This patch can fix 
this
build error.

Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/openrisc/include/asm/io.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index 7c69139..6709b28 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -29,13 +29,14 @@
 #define PIO_OFFSET 0
 #define PIO_MASK   0
 
+#define ioremap_nocache ioremap_nocache
 #include 
 #include 
 
 extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size,
pgprot_t prot);
 
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
return __ioremap(offset, size, PAGE_KERNEL);
 }
-- 
1.7.9.5

[PATCH v6 04/36] earlycon: add reg-offset to physical address before mapping

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

It will get the wrong virtual address because port->mapbase is not added
the correct reg-offset yet. We have to update it before earlycon_map()
is called

Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 drivers/tty/serial/earlycon.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index 98928f0..17dba0a 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -253,11 +253,12 @@ int __init of_setup_earlycon(const struct earlycon_id 
*match,
}
port->mapbase = addr;
port->uartclk = BASE_BAUD * 16;
-   port->membase = earlycon_map(port->mapbase, SZ_4K);
 
val = of_get_flat_dt_prop(node, "reg-offset", NULL);
if (val)
port->mapbase += be32_to_cpu(*val);
+   port->membase = earlycon_map(port->mapbase, SZ_4K);
+
val = of_get_flat_dt_prop(node, "reg-shift", NULL);
if (val)
port->regshift = be32_to_cpu(*val);
-- 
1.7.9.5

[PATCH v6 05/36] nds32: Assembly macros and definitions

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes assembly macros, bit field definitions used in .S
files across arch/nds32/.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/assembler.h |   39 ++
 arch/nds32/include/asm/bitfield.h  |  963 
 arch/nds32/include/asm/nds32.h |   83 
 arch/nds32/kernel/asm-offsets.c|   28 ++
 4 files changed, 1113 insertions(+)
 create mode 100644 arch/nds32/include/asm/assembler.h
 create mode 100644 arch/nds32/include/asm/bitfield.h
 create mode 100644 arch/nds32/include/asm/nds32.h
 create mode 100644 arch/nds32/kernel/asm-offsets.c

diff --git a/arch/nds32/include/asm/assembler.h 
b/arch/nds32/include/asm/assembler.h
new file mode 100644
index 000..c385578
--- /dev/null
+++ b/arch/nds32/include/asm/assembler.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASSEMBLER_H__
+#define __NDS32_ASSEMBLER_H__
+
+.macro gie_disable
+   setgie.d
+   dsb
+.endm
+
+.macro gie_enable
+   setgie.e
+   dsb
+.endm
+
+.macro gie_save oldpsw
+   mfsr \oldpsw, $ir0
+   setgie.d
+dsb
+.endm
+
+.macro gie_restore oldpsw
+   andi \oldpsw, \oldpsw, #0x1
+   beqz \oldpsw, 7001f
+   setgie.e
+   dsb
+7001:
+.endm
+
+
+#define USER(insn,  reg, addr, opr)\
+:  insn  reg, addr, opr;   \
+   .section __ex_table,"a";\
+   .align 3;   \
+   .long   b, 9001f;   \
+   .previous
+
+#endif /* __NDS32_ASSEMBLER_H__ */
diff --git a/arch/nds32/include/asm/bitfield.h 
b/arch/nds32/include/asm/bitfield.h
new file mode 100644
index 000..c73f71d
--- /dev/null
+++ b/arch/nds32/include/asm/bitfield.h
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BITFIELD_H__
+#define __NDS32_BITFIELD_H__
+/**
+ * cr0: CPU_VER (CPU Version Register)
+ */
+#define CPU_VER_offCFGID   0   /* Minor configuration */
+#define CPU_VER_offREV 16  /* Revision of the CPU version */
+#define CPU_VER_offCPUID   24  /* Major CPU versions */
+
+#define CPU_VER_mskCFGID   ( 0x  << CPU_VER_offCFGID )
+#define CPU_VER_mskREV ( 0xFF  << CPU_VER_offREV )
+#define CPU_VER_mskCPUID   ( 0xFF  << CPU_VER_offCPUID )
+
+/**
+ * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
+ */
+#define ICM_CFG_offISET0   /* I-cache sets (# of cache 
lines) per way */
+#define ICM_CFG_offIWAY3   /* I-cache ways */
+#define ICM_CFG_offISZ 6   /* I-cache line size */
+#define ICM_CFG_offILCK9   /* I-cache locking support */
+#define ICM_CFG_offILMB10  /* On-chip ILM banks */
+#define ICM_CFG_offBSAV13  /* ILM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define ICM_CFG_mskISET( 0x7  << ICM_CFG_offISET )
+#define ICM_CFG_mskIWAY( 0x7  << ICM_CFG_offIWAY )
+#define ICM_CFG_mskISZ ( 0x7  << ICM_CFG_offISZ )
+#define ICM_CFG_mskILCK( 0x1  << ICM_CFG_offILCK )
+#define ICM_CFG_mskILMB( 0x7  << ICM_CFG_offILMB )
+#define ICM_CFG_mskBSAV( 0x3  << ICM_CFG_offBSAV )
+
+/**
+ * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
+ */
+#define DCM_CFG_offDSET0   /* D-cache sets (# of cache 
lines) per way */
+#define DCM_CFG_offDWAY3   /* D-cache ways */
+#define DCM_CFG_offDSZ 6   /* D-cache line size */
+#define DCM_CFG_offDLCK9   /* D-cache locking support */
+#define DCM_CFG_offDLMB10  /* On-chip DLM banks */
+#define DCM_CFG_offBSAV13  /* DLM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define DCM_CFG_mskDSET( 0x7  << DCM_CFG_offDSET )
+#define DCM_CFG_mskDWAY( 0x7  << DCM_CFG_offDWAY )
+#define DCM_CFG_mskDSZ ( 0x7  << DCM_CFG_offDSZ )
+#define DCM_CFG_mskDLCK( 0x1  << DCM_CFG_offDLCK )
+#define DCM_CFG_mskDLMB( 0x7  << DCM_CFG_offDLMB )
+#define DCM_CFG_mskBSAV( 0x3  << DCM_

[PATCH v6 07/36] nds32: Exception handling

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes the exception/interrupt entries, pt_reg structure and
related accessors.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/ptrace.h |   66 +
 arch/nds32/kernel/ex-entry.S|  157 ++
 arch/nds32/kernel/ex-exit.S |  193 +
 arch/nds32/kernel/stacktrace.c  |   47 +++
 arch/nds32/kernel/traps.c   |  428 +++
 arch/nds32/mm/alignment.c   |  609 +++
 6 files changed, 1500 insertions(+)
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ex-entry.S
 create mode 100644 arch/nds32/kernel/ex-exit.S
 create mode 100644 arch/nds32/kernel/stacktrace.c
 create mode 100644 arch/nds32/kernel/traps.c
 create mode 100644 arch/nds32/mm/alignment.c

diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 000..db7856c
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PTRACE_H
+#define __ASM_NDS32_PTRACE_H
+
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS   14
+#define PTRACE_SETFPREGS   15
+
+#include 
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+   union {
+   struct user_pt_regs user_regs;
+   struct {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+#if defined(CONFIG_HWZOL)
+   long lb;
+   long le;
+   long lc;
+#else
+   long dummy[3];
+#endif
+   long syscallno;
+   };
+   };
+   long orig_r0;
+   long ir0;
+   long ipsw;
+   long pipsw;
+   long pipc;
+   long pp0;
+   long pp1;
+   long fucop_ctl;
+   long osp;
+};
+
+#include 
+extern void show_regs(struct pt_regs *);
+/* Avoid circular header include via sched.h */
+struct task_struct;
+extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
+int error_code, int si_code);
+
+#define arch_has_single_step() (1)
+#define user_mode(regs)(((regs)->ipsw & PSW_mskPOM) == 
0)
+#define interrupts_enabled(regs)   (!!((regs)->ipsw & PSW_mskGIE))
+#define valid_user_regs(regs)  (user_mode(regs) && 
interrupts_enabled(regs))
+#define regs_return_value(regs)((regs)->uregs[0])
+#define instruction_pointer(regs)  ((regs)->ipc)
+#define user_stack_pointer(regs)((regs)->sp)
+#define profile_pc(regs)   instruction_pointer(regs)
+
+#define ARCH_HAS_USER_SINGLE_STEP_INFO
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S
new file mode 100644
index 000..a72e83d
--- /dev/null
+++ b/arch/nds32/kernel/ex-entry.S
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_HWZOL
+   .macro push_zol
+   mfusr   $r14, $LB
+   mfusr   $r15, $LE
+   mfusr   $r16, $LC
+   .endm
+#endif
+
+   .macro  save_user_regs
+
+   smw.adm $sp, [$sp], $sp, #0x1
+   /* move $SP to the bottom of pt_regs */
+   addi$sp, $sp, -OSP_OFFSET
+
+   /* push $r0 ~ $r25 */
+   smw.bim $r0, [$sp], $r25
+   /* push $fp, $gp, $lp */
+   smw.bim $sp, [$sp], $sp, #0xe
+
+   mfsr$r12, $SP_USR
+   mfsr$r13, $IPC
+#ifdef CONFIG_HWZOL
+   push_zol
+#endif
+   movi$r17, -1
+   move$r18, $r0
+   mfsr$r19, $PSW
+   mfsr$r20, $IPSW
+   mfsr$r21, $P_IPSW
+   mfsr$r22, $P_IPC
+   mfsr$r23, $P_P0
+   mfsr$r24, $P_P1
+   smw.bim $r12, [$sp], $r24, #0
+   addi$sp, $sp, -FUCOP_CTL_OFFSET
+
+   /* Initialize kernel space $fp */
+   andi$p0, $r20, #PSW_mskPOM
+   movi$p1, #0x0
+   cmovz   $fp, $p1, $p0
+
+   andi$r16, $r19, #PSW_mskINTL
+   slti$r17, $r16, #4
+   bnez$r17, 1f
+   addi$r17, $r19, #-2
+   mtsr$r17, $PSW
+   isb
+1:
+   /* If it was superuser mode, we don't need to update $r25 */
+   bnez$p0, 2f
+   la  $p0, __entry_task
+   lw  $r25, [$p0]
+2:
+   .endm
+
+   .text
+
+/*
+ * Exception Vector
+ */
+exception_handlers:
+   .long   unhandled_exceptions!Reset/NMI
+   .long   unhandled_exceptions!TLB fill
+   .long   do_pa

[PATCH v6 08/36] nds32: MMU definitions

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes virtual memory layout, PHYS_OFFSET is defined as 0x0. It
also includes the 4KB/8KB page size configurations and pte operations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/fixmap.h   |   29 +++
 arch/nds32/include/asm/highmem.h  |   65 ++
 arch/nds32/include/asm/memory.h   |  105 ++
 arch/nds32/include/asm/mmu.h  |   12 ++
 arch/nds32/include/asm/page.h |   67 ++
 arch/nds32/include/asm/pgalloc.h  |   96 +
 arch/nds32/include/asm/pgtable.h  |  409 +
 arch/nds32/include/asm/shmparam.h |   19 ++
 8 files changed, 802 insertions(+)
 create mode 100644 arch/nds32/include/asm/fixmap.h
 create mode 100644 arch/nds32/include/asm/highmem.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/mmu.h
 create mode 100644 arch/nds32/include/asm/page.h
 create mode 100644 arch/nds32/include/asm/pgalloc.h
 create mode 100644 arch/nds32/include/asm/pgtable.h
 create mode 100644 arch/nds32/include/asm/shmparam.h

diff --git a/arch/nds32/include/asm/fixmap.h b/arch/nds32/include/asm/fixmap.h
new file mode 100644
index 000..0e60e15
--- /dev/null
+++ b/arch/nds32/include/asm/fixmap.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_FIXMAP_H
+#define __ASM_NDS32_FIXMAP_H
+
+#ifdef CONFIG_HIGHMEM
+#include 
+#include 
+#endif
+
+enum fixed_addresses {
+   FIX_HOLE,
+   FIX_KMAP_RESERVED,
+   FIX_KMAP_BEGIN,
+#ifdef CONFIG_HIGHMEM
+   FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS),
+#endif
+   FIX_EARLYCON_MEM_BASE,
+   __end_of_fixed_addresses
+};
+#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE)))
+#define FIXADDR_SIZE   ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START  (FIXADDR_TOP - FIXADDR_SIZE)
+#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE)
+void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
+
+#include 
+#endif /* __ASM_NDS32_FIXMAP_H */
diff --git a/arch/nds32/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h
new file mode 100644
index 000..425d546
--- /dev/null
+++ b/arch/nds32/include/asm/highmem.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+/*
+ * Ordering is (from lower to higher memory addresses):
+ *
+ * high_memory
+ * Persistent kmap area
+ * PKMAP_BASE
+ * fixed_addresses
+ * FIXADDR_START
+ * FIXADDR_TOP
+ * Vmalloc area
+ * VMALLOC_START
+ * VMALLOC_END
+ */
+#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK))
+#define LAST_PKMAP PTRS_PER_PTE
+#define LAST_PKMAP_MASK(LAST_PKMAP - 1)
+#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+#define kmap_prot  PAGE_KERNEL
+
+static inline void flush_cache_kmaps(void)
+{
+   cpu_dcache_wbinval_all();
+}
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *pkmap_page_table;
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+extern void kmap_init(void);
+
+/*
+ * The following functions are already defined by 
+ * when CONFIG_HIGHMEM is not set.
+ */
+#ifdef CONFIG_HIGHMEM
+extern void *kmap(struct page *page);
+extern void kunmap(struct page *page);
+extern void *kmap_atomic(struct page *page);
+extern void __kunmap_atomic(void *kvaddr);
+extern void *kmap_atomic_pfn(unsigned long pfn);
+extern struct page *kmap_atomic_to_page(void *ptr);
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 000..60efc72
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MEMORY_H
+#define __ASM_NDS32_MEMORY_H
+
+#include 
+#include 
+
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET (0x0)
+#endif
+
+#ifndef __virt_to_bus
+#define __virt_to_bus  __virt_to_phys
+#endif
+
+#ifndef __bus_to_virt
+#define __bus_to_virt  __phys_to_virt
+#endif
+
+/*
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
+ */
+#define TASK_SIZE 

[PATCH v6 06/36] nds32: Kernel booting and initialization

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes the kernel startup code. It can get dtb pointer
passed from bootloader. It will create a temp mapping by tlb
instructions at beginning and goto start_kernel.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/kernel/head.S  |  188 ++
 arch/nds32/kernel/setup.c |  387 +
 2 files changed, 575 insertions(+)
 create mode 100644 arch/nds32/kernel/head.S
 create mode 100644 arch/nds32/kernel/setup.c

diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
new file mode 100644
index 000..71f57bd
--- /dev/null
+++ b/arch/nds32/kernel/head.S
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0
+#endif
+
+   .globl  swapper_pg_dir
+   .equswapper_pg_dir, TEXTADDR - 0x4000
+
+/*
+ * Kernel startup entry point.
+ */
+   .section ".head.text", "ax"
+   .type   _stext, %function
+ENTRY(_stext)
+   setgie.d! Disable interrupt
+   isb
+/*
+ * Disable I/D-cache and enable it at a proper time
+ */
+   mfsr$r0, $mr8
+   li  $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
+   and $r0, $r0, $r1
+   mtsr$r0, $mr8
+
+/*
+ * Process device tree blob
+ */
+   andi$r0,$r2,#0x3
+   li  $r10, 0
+   bne $r0, $r10, _nodtb
+   lwi $r0, [$r2]
+   li  $r1, OF_DT_MAGIC
+   bne $r0, $r1, _nodtb
+   move$r10, $r2
+_nodtb:
+
+/*
+ * Create a temporary mapping area for booting, before start_kernel
+ */
+   sethi   $r4, hi20(swapper_pg_dir)
+   li  $p0, (PAGE_OFFSET - PHYS_OFFSET)
+   sub $r4, $r4, $p0
+   tlbop   FlushAll! invalidate TLB\n"
+   isb
+   mtsr$r4, $L1_PPTB   ! load page table pointer\n"
+
+/* set NTC0 cacheable/writeback, mutliple page size in use */
+   mfsr$r3, $MMU_CTL
+   li  $r0, #~MMU_CTL_mskNTC0
+   and $r3, $r3, $r0
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0))
+#else
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0)|MMU_CTL_D8KB)
+#endif
+#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
+   li  $r0, #MMU_CTL_UNA
+   or  $r3, $r3, $r0
+#endif
+   mtsr$r3, $MMU_CTL
+   isb
+
+/* set page size and size of kernel image */
+mfsr$r0, $MMU_CFG
+srli$r3, $r0, MMU_CFG_offfEPSZ
+zeb $r3, $r3
+bnez$r3, _extra_page_size_support
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+li  $r5, #SZ_4K ! Use 4KB page size
+#else
+li  $r5, #SZ_8K ! Use 8KB page size
+li  $r3, #1
+#endif
+mtsr$r3, $TLB_MISC
+b   _image_size_check
+
+_extra_page_size_support:! Use epzs pages size
+clz $r6, $r3
+subri   $r2, $r6, #31
+li  $r3, #1
+sll $r3, $r3, $r2
+/* MMU_CFG.EPSZ value -> meaning */
+mul $r5, $r3, $r3
+slli$r5, $r5, #14
+/* MMU_CFG.EPSZ  -> TLB_MISC.ACC_PSZ */
+addi$r3, $r2, #0x2
+mtsr$r3, $TLB_MISC
+
+_image_size_check:
+/* calculate the image maximum size accepted by TLB config */
+andi$r6, $r0, MMU_CFG_mskTBW
+andi$r0, $r0, MMU_CFG_mskTBS
+srli$r6, $r6, MMU_CFG_offTBW
+srli$r0, $r0, MMU_CFG_offTBS
+/*
+ * we just map the kernel to the maximum way - 1 of tlb
+ * reserver one way for UART VA mapping
+ * it will cause page fault if UART mapping cover the kernel mapping
+ *
+ * direct mapping is not supported now.
+ */
+li  $r2, 't'
+beqz$r6, __error ! MMU_CFG.TBW = 0 is direct mappin
+addi$r0, $r0, #0x2   ! MMU_CFG.TBS value -> meaning
+sll $r0, $r6, $r0! entries = k-way * n-set
+mul $r6, $r0, $r5! max size = entries * page size
+/* check kernel image size */
+la  $r3, (_end - PAGE_OFFSET)
+li  $r2, 's'
+bgt $r3, $r6, __error
+
+   li  $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
+li  $r3, PAGE_OFFSET
+add $r6, $r6, $r3
+
+_tlb:
+   mtsr$r3, $TLB_VPN
+   dsb
+   tlbop   $r2, RWR
+   isb
+   add $r3, $r3, $r5
+   add $r2, $r2, $r5
+   bgt $r6, $r3, _tlb
+   mfs

[PATCH v6 10/36] nds32: MMU fault handling and page table management

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes page fault handler, mmap and fixup implementations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/lib/copy_page.S |   37 
 arch/nds32/mm/extable.c|   16 ++
 arch/nds32/mm/fault.c  |  410 
 arch/nds32/mm/mmap.c   |   73 
 4 files changed, 536 insertions(+)
 create mode 100644 arch/nds32/lib/copy_page.S
 create mode 100644 arch/nds32/mm/extable.c
 create mode 100644 arch/nds32/mm/fault.c
 create mode 100644 arch/nds32/mm/mmap.c

diff --git a/arch/nds32/lib/copy_page.S b/arch/nds32/lib/copy_page.S
new file mode 100644
index 000..4a2ff85
--- /dev/null
+++ b/arch/nds32/lib/copy_page.S
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+   .text
+ENTRY(copy_page)
+   pushm   $r2, $r10
+   movi$r2, PAGE_SIZE >> 5
+.Lcopy_loop:
+   lmw.bim $r3, [$r1], $r10
+   smw.bim $r3, [$r0], $r10
+   subi45  $r2, #1
+   bnez38  $r2, .Lcopy_loop
+   popm$r2, $r10
+   ret
+ENDPROC(copy_page)
+
+ENTRY(clear_page)
+   pushm   $r1, $r9
+   movi$r1, PAGE_SIZE >> 5
+   movi55  $r2, #0
+   movi55  $r3, #0
+   movi55  $r4, #0
+   movi55  $r5, #0
+   movi55  $r6, #0
+   movi55  $r7, #0
+   movi55  $r8, #0
+   movi55  $r9, #0
+.Lclear_loop:
+   smw.bim $r2, [$r0], $r9
+   subi45  $r1, #1
+   bnez38  $r1, .Lclear_loop
+   popm$r1, $r9
+ret
+ENDPROC(clear_page)
diff --git a/arch/nds32/mm/extable.c b/arch/nds32/mm/extable.c
new file mode 100644
index 000..db7f0a7
--- /dev/null
+++ b/arch/nds32/mm/extable.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+int fixup_exception(struct pt_regs *regs)
+{
+   const struct exception_table_entry *fixup;
+
+   fixup = search_exception_tables(instruction_pointer(regs));
+   if (fixup)
+   regs->ipc = fixup->fixup;
+
+   return fixup != NULL;
+}
diff --git a/arch/nds32/mm/fault.c b/arch/nds32/mm/fault.c
new file mode 100644
index 000..3a246fb
--- /dev/null
+++ b/arch/nds32/mm/fault.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+extern void die(const char *str, struct pt_regs *regs, long err);
+
+/*
+ * This is useful to dump out the page tables associated with
+ * 'addr' in mm 'mm'.
+ */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{
+   pgd_t *pgd;
+   if (!mm)
+   mm = _mm;
+
+   pr_alert("pgd = %p\n", mm->pgd);
+   pgd = pgd_offset(mm, addr);
+   pr_alert("[%08lx] *pgd=%08lx", addr, pgd_val(*pgd));
+
+   do {
+   pmd_t *pmd;
+
+   if (pgd_none(*pgd))
+   break;
+
+   if (pgd_bad(*pgd)) {
+   pr_alert("(bad)");
+   break;
+   }
+
+   pmd = pmd_offset(pgd, addr);
+#if PTRS_PER_PMD != 1
+   pr_alert(", *pmd=%08lx", pmd_val(*pmd));
+#endif
+
+   if (pmd_none(*pmd))
+   break;
+
+   if (pmd_bad(*pmd)) {
+   pr_alert("(bad)");
+   break;
+   }
+
+   if (IS_ENABLED(CONFIG_HIGHMEM))
+   {
+   pte_t *pte;
+   /* We must not map this if we have highmem enabled */
+   pte = pte_offset_map(pmd, addr);
+   pr_alert(", *pte=%08lx", pte_val(*pte));
+   pte_unmap(pte);
+   }
+   } while (0);
+
+   pr_alert("\n");
+}
+
+void do_page_fault(unsigned long entry, unsigned long addr,
+  unsigned int error_code, struct pt_regs *regs)
+{
+   struct task_struct *tsk;
+   struct mm_struct *mm;
+   struct vm_area_struct *vma;
+   siginfo_t info;
+   int fault;
+   unsigned int mask = VM_READ | VM_WRITE | VM_EXEC;
+   unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+
+   error_code = error_code & (ITYPE_mskINST | ITYPE_mskETYPE);
+   tsk = current;
+   mm = tsk->mm;
+   info.si_code = SEGV_MAPERR;
+   /*
+* We fault-in kernel-space virtual memory on-demand. The
+* 'reference' page table is init_mm.pgd.
+*
+* NOTE! We MUST NOT take any locks for this case. We may
+* be in an interrupt or a critical region, and should
+* only copy the information from the ma

[PATCH v6 12/36] nds32: Process management

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes copy_thread(), start_thread() implementation and cpu_context
structure definition. nds32 uses $r25 to get current task_struct.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/current.h |   12 ++
 arch/nds32/include/asm/processor.h   |  102 +
 arch/nds32/include/asm/thread_info.h |   78 +
 arch/nds32/kernel/process.c  |  204 ++
 4 files changed, 396 insertions(+)
 create mode 100644 arch/nds32/include/asm/current.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/thread_info.h
 create mode 100644 arch/nds32/kernel/process.c

diff --git a/arch/nds32/include/asm/current.h b/arch/nds32/include/asm/current.h
new file mode 100644
index 000..b4dcd22
--- /dev/null
+++ b/arch/nds32/include/asm/current.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_CURRENT_H
+#define _ASM_NDS32_CURRENT_H
+
+#ifndef __ASSEMBLY__
+register struct task_struct *current asm("$r25");
+#endif /* __ASSEMBLY__ */
+#define tsk $r25
+
+#endif /* _ASM_NDS32_CURRENT_H */
diff --git a/arch/nds32/include/asm/processor.h 
b/arch/nds32/include/asm/processor.h
new file mode 100644
index 000..cad9b8c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PROCESSOR_H
+#define __ASM_NDS32_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#ifdef __KERNEL__
+
+#include 
+#include 
+#include 
+
+#define KERNEL_STACK_SIZE  PAGE_SIZE
+#define STACK_TOP  TASK_SIZE
+#define STACK_TOP_MAX   TASK_SIZE
+
+struct cpu_context {
+   unsigned long r6;
+   unsigned long r7;
+   unsigned long r8;
+   unsigned long r9;
+   unsigned long r10;
+   unsigned long r11;
+   unsigned long r12;
+   unsigned long r13;
+   unsigned long r14;
+   unsigned long fp;
+   unsigned long pc;
+   unsigned long sp;
+};
+
+struct thread_struct {
+   struct cpu_context cpu_context; /* cpu context */
+   /* fault info */
+   unsigned long address;
+   unsigned long trap_no;
+   unsigned long error_code;
+};
+
+#define INIT_THREAD  { }
+
+#ifdef __NDS32_EB__
+#define PSW_DE PSW_mskBE
+#else
+#define PSW_DE 0x0
+#endif
+
+#ifdef CONFIG_WBNA
+#define PSW_valWBNAPSW_mskWBNA
+#else
+#define PSW_valWBNA0x0
+#endif
+
+#ifdef CONFIG_HWZOL
+#definePSW_valINIT (PSW_CPL_ANY | PSW_mskAEN | PSW_valWBNA | PSW_mskDT 
| PSW_mskIT | PSW_DE | PSW_mskGIE)
+#else
+#definePSW_valINIT (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT 
| PSW_DE | PSW_mskGIE)
+#endif
+
+#define start_thread(regs,pc,stack)\
+({ \
+   memzero(regs, sizeof(struct pt_regs));  \
+   regs->ipsw = PSW_valINIT;   \
+   regs->ir0 = (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE 
| PSW_SYSTEM | PSW_INTL_1); \
+   regs->ipc = pc; \
+   regs->sp = stack;   \
+})
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)   do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define cpu_relax()barrier()
+
+#define task_pt_regs(task) \
+   ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+   - 8) - 1)
+
+/*
+ * Create a new kernel thread
+ */
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
+
+#define KSTK_EIP(tsk)  instruction_pointer(task_pt_regs(tsk))
+#define KSTK_ESP(tsk)  user_stack_pointer(task_pt_regs(tsk))
+
+#endif
+
+#endif /* __ASM_NDS32_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/thread_info.h 
b/arch/nds32/include/asm/thread_info.h
new file mode 100644
index 000..818e769
--- /dev/null
+++ b/arch/nds32/include/asm/thread_info.h
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_THREAD_INFO_H
+#define __ASM_NDS32_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#define THREAD_SIZE_ORDER  (1)
+#define THREAD_SIZE(PAGE_SIZE << THREAD_SIZE_ORDER)
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+
+#include 
+#include 
+
+typedef unsigned long mm_segment_t;
+

[PATCH v6 14/36] nds32: Atomic operations

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes the atomic and futex operations. Many atomic operations use
the load-lock word(llw) and store-condition word(scw) operations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/barrier.h |   15 ++
 arch/nds32/include/asm/futex.h   |  103 ++
 2 files changed, 118 insertions(+)
 create mode 100644 arch/nds32/include/asm/barrier.h
 create mode 100644 arch/nds32/include/asm/futex.h

diff --git a/arch/nds32/include/asm/barrier.h b/arch/nds32/include/asm/barrier.h
new file mode 100644
index 000..faafc37
--- /dev/null
+++ b/arch/nds32/include/asm/barrier.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASM_BARRIER_H
+#define __NDS32_ASM_BARRIER_H
+
+#ifndef __ASSEMBLY__
+#define mb()   asm volatile("msync all":::"memory")
+#define rmb()  asm volatile("msync all":::"memory")
+#define wmb()  asm volatile("msync store":::"memory")
+#include 
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __NDS32_ASM_BARRIER_H */
diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h
new file mode 100644
index 000..eab5e84
--- /dev/null
+++ b/arch/nds32/include/asm/futex.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_FUTEX_H__
+#define __NDS32_FUTEX_H__
+
+#include 
+#include 
+#include 
+
+#define __futex_atomic_ex_table(err_reg)   \
+   "   .pushsection __ex_table,\"a\"\n"\
+   "   .align  3\n"\
+   "   .long   1b, 4f\n"   \
+   "   .long   2b, 4f\n"   \
+   "   .popsection\n"  \
+   "   .pushsection .fixup,\"ax\"\n"   \
+   "4: move%0, " err_reg "\n"  \
+   "   j   3b\n"   \
+   "   .popsection"
+
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)\
+   smp_mb();   \
+   asm volatile(   \
+   "   movi$ta, #0\n"  \
+   "1: llw %1, [%2+$ta]\n" \
+   "   " insn "\n" \
+   "2: scw %0, [%2+$ta]\n" \
+   "   beqz%0, 1b\n"   \
+   "   movi%0, #0\n"   \
+   "3:\n"  \
+   __futex_atomic_ex_table("%4")   \
+   : "=" (ret), "=" (oldval)   \
+   : "r" (uaddr), "r" (oparg), "i" (-EFAULT)   \
+   : "cc", "memory")
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr,
+ u32 oldval, u32 newval)
+{
+   int ret = 0;
+   u32 val, tmp, flags;
+
+   if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+   return -EFAULT;
+
+   smp_mb();
+   asm volatile ("   movi$ta, #0\n"
+ "1: llw %1, [%6 + $ta]\n"
+ "   sub %3, %1, %4\n"
+ "   cmovz   %2, %5, %3\n"
+ "   cmovn   %2, %1, %3\n"
+ "2: scw %2, [%6 + $ta]\n"
+ "   beqz%2, 1b\n"
+ "3:\n   " __futex_atomic_ex_table("%7")
+ :"+"(ret), "="(val), "="(tmp), "="(flags)
+ :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT)
+ :"$ta", "memory");
+   smp_mb();
+
+   *uval = val;
+   return ret;
+}
+
+static inline int
+arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
+{
+   int oldval = 0, ret;
+
+
+   pagefault_disable();
+   switch (op) {
+   case FUTEX_OP_SET:
+   __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr,
+ oparg);
+

[PATCH v6 11/36] nds32: Cache and TLB routines

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch contains cache and TLB maintenance functions.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/cache.h |   12 +
 arch/nds32/include/asm/cache_info.h|   13 +
 arch/nds32/include/asm/cacheflush.h|   44 +++
 arch/nds32/include/asm/mmu_context.h   |   68 
 arch/nds32/include/asm/proc-fns.h  |   44 +++
 arch/nds32/include/asm/tlb.h   |   28 ++
 arch/nds32/include/asm/tlbflush.h  |   47 +++
 arch/nds32/include/uapi/asm/cachectl.h |   14 +
 arch/nds32/kernel/cacheinfo.c  |   49 +++
 arch/nds32/mm/cacheflush.c |  322 +++
 arch/nds32/mm/proc.c   |  533 
 arch/nds32/mm/tlb.c|   50 +++
 12 files changed, 1224 insertions(+)
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/cache_info.h
 create mode 100644 arch/nds32/include/asm/cacheflush.h
 create mode 100644 arch/nds32/include/asm/mmu_context.h
 create mode 100644 arch/nds32/include/asm/proc-fns.h
 create mode 100644 arch/nds32/include/asm/tlb.h
 create mode 100644 arch/nds32/include/asm/tlbflush.h
 create mode 100644 arch/nds32/include/uapi/asm/cachectl.h
 create mode 100644 arch/nds32/kernel/cacheinfo.c
 create mode 100644 arch/nds32/mm/cacheflush.c
 create mode 100644 arch/nds32/mm/proc.c
 create mode 100644 arch/nds32/mm/tlb.c

diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 000..347db48
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHE_H__
+#define __NDS32_CACHE_H__
+
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
+
+#define ARCH_DMA_MINALIGN   L1_CACHE_BYTES
+
+#endif /* __NDS32_CACHE_H__ */
diff --git a/arch/nds32/include/asm/cache_info.h 
b/arch/nds32/include/asm/cache_info.h
new file mode 100644
index 000..38ec458
--- /dev/null
+++ b/arch/nds32/include/asm/cache_info.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+struct cache_info {
+   unsigned char ways;
+   unsigned char line_size;
+   unsigned short sets;
+   unsigned short size;
+#if defined(CONFIG_CPU_CACHE_ALIASING)
+   unsigned short aliasing_num;
+   unsigned int aliasing_mask;
+#endif
+};
diff --git a/arch/nds32/include/asm/cacheflush.h 
b/arch/nds32/include/asm/cacheflush.h
new file mode 100644
index 000..7b9b20a
--- /dev/null
+++ b/arch/nds32/include/asm/cacheflush.h
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHEFLUSH_H__
+#define __NDS32_CACHEFLUSH_H__
+
+#include 
+
+#define PG_dcache_dirty PG_arch_1
+
+#ifdef CONFIG_CPU_CACHE_ALIASING
+void flush_cache_mm(struct mm_struct *mm);
+void flush_cache_dup_mm(struct mm_struct *mm);
+void flush_cache_range(struct vm_area_struct *vma,
+  unsigned long start, unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long pfn);
+void flush_cache_kmaps(void);
+void flush_cache_vmap(unsigned long start, unsigned long end);
+void flush_cache_vunmap(unsigned long start, unsigned long end);
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+void flush_dcache_page(struct page *page);
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+  unsigned long vaddr, void *dst, void *src, int len);
+void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+unsigned long vaddr, void *dst, void *src, int len);
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+void flush_anon_page(struct vm_area_struct *vma,
+struct page *page, unsigned long vaddr);
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+void flush_kernel_dcache_page(struct page *page);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#define flush_dcache_mmap_lock(mapping)   spin_lock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_unlock(mapping) 
spin_unlock_irq(&(mapping)->tree_lock)
+
+#else
+#include 
+#endif
+
+#endif /* __NDS32_CACHEFLUSH_H__ */
diff --git a/arch/nds32/include/asm/mmu_context.h 
b/arch/nds32/include/asm/mmu_context.h
new file mode 100644
index 000..fd7d13c
--- /dev/null
+++ b/arch/nds32/include/asm/mmu_context.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MMU_CONTEXT_H
+#define __ASM_NDS32_MMU_CONTEXT_H
+
+#include 
+#include 
+#include 
+#include 
+
+static inline int
+init_new_context(struct task_s

[PATCH v6 16/36] nds32: DMA mapping API

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds support for the DMA mapping API. It uses dma_map_ops for
flexibility.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/dma-mapping.h |   14 ++
 arch/nds32/kernel/dma.c  |  459 ++
 2 files changed, 473 insertions(+)
 create mode 100644 arch/nds32/include/asm/dma-mapping.h
 create mode 100644 arch/nds32/kernel/dma.c

diff --git a/arch/nds32/include/asm/dma-mapping.h 
b/arch/nds32/include/asm/dma-mapping.h
new file mode 100644
index 000..2dd47d24
--- /dev/null
+++ b/arch/nds32/include/asm/dma-mapping.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef ASMNDS32_DMA_MAPPING_H
+#define ASMNDS32_DMA_MAPPING_H
+
+extern struct dma_map_ops nds32_dma_ops;
+
+static inline struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+{
+   return _dma_ops;
+}
+
+#endif
diff --git a/arch/nds32/kernel/dma.c b/arch/nds32/kernel/dma.c
new file mode 100644
index 000..9bd1dc7
--- /dev/null
+++ b/arch/nds32/kernel/dma.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * This is the page table (2MB) covering uncached, DMA consistent allocations
+ */
+static pte_t *consistent_pte;
+static DEFINE_RAW_SPINLOCK(consistent_lock);
+
+/*
+ * VM region handling support.
+ *
+ * This should become something generic, handling VM region allocations for
+ * vmalloc and similar (ioremap, module space, etc).
+ *
+ * I envisage vmalloc()'s supporting vm_struct becoming:
+ *
+ *  struct vm_struct {
+ *struct vm_region region;
+ *unsigned longflags;
+ *struct page  **pages;
+ *unsigned int nr_pages;
+ *unsigned longphys_addr;
+ *  };
+ *
+ * get_vm_area() would then call vm_region_alloc with an appropriate
+ * struct vm_region head (eg):
+ *
+ *  struct vm_region vmalloc_head = {
+ * .vm_list= LIST_HEAD_INIT(vmalloc_head.vm_list),
+ * .vm_start   = VMALLOC_START,
+ * .vm_end = VMALLOC_END,
+ *  };
+ *
+ * However, vmalloc_head.vm_start is variable (typically, it is dependent on
+ * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
+ * would have to initialise this each time prior to calling vm_region_alloc().
+ */
+struct arch_vm_region {
+   struct list_head vm_list;
+   unsigned long vm_start;
+   unsigned long vm_end;
+   struct page *vm_pages;
+};
+
+static struct arch_vm_region consistent_head = {
+   .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
+   .vm_start = CONSISTENT_BASE,
+   .vm_end = CONSISTENT_END,
+};
+
+static struct arch_vm_region *vm_region_alloc(struct arch_vm_region *head,
+ size_t size, int gfp)
+{
+   unsigned long addr = head->vm_start, end = head->vm_end - size;
+   unsigned long flags;
+   struct arch_vm_region *c, *new;
+
+   new = kmalloc(sizeof(struct arch_vm_region), gfp);
+   if (!new)
+   goto out;
+
+   raw_spin_lock_irqsave(_lock, flags);
+
+   list_for_each_entry(c, >vm_list, vm_list) {
+   if ((addr + size) < addr)
+   goto nospc;
+   if ((addr + size) <= c->vm_start)
+   goto found;
+   addr = c->vm_end;
+   if (addr > end)
+   goto nospc;
+   }
+
+found:
+   /*
+* Insert this entry _before_ the one we found.
+*/
+   list_add_tail(>vm_list, >vm_list);
+   new->vm_start = addr;
+   new->vm_end = addr + size;
+
+   raw_spin_unlock_irqrestore(_lock, flags);
+   return new;
+
+nospc:
+   raw_spin_unlock_irqrestore(_lock, flags);
+   kfree(new);
+out:
+   return NULL;
+}
+
+static struct arch_vm_region *vm_region_find(struct arch_vm_region *head,
+unsigned long addr)
+{
+   struct arch_vm_region *c;
+
+   list_for_each_entry(c, >vm_list, vm_list) {
+   if (c->vm_start == addr)
+   goto out;
+   }
+   c = NULL;
+out:
+   return c;
+}
+
+/* FIXME: attrs is not used. */
+static void *nds32_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t * handle, gfp_t gfp,
+ unsigned long attrs)
+{
+   struct page *page;
+   struct arch_vm_region *c;
+   unsigned long order;
+   u64 mask = ~0ULL, limit;
+   pgprot_t prot = pgprot_noncached(PAGE_KERNEL);
+
+   if (!consistent_pte

[PATCH v6 13/36] nds32: IRQ handling

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch includes irq related functions and irqchip_init().

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/irqflags.h |   36 
 arch/nds32/kernel/irq.c   |9 +
 2 files changed, 45 insertions(+)
 create mode 100644 arch/nds32/include/asm/irqflags.h
 create mode 100644 arch/nds32/kernel/irq.c

diff --git a/arch/nds32/include/asm/irqflags.h 
b/arch/nds32/include/asm/irqflags.h
new file mode 100644
index 000..2bfd00f
--- /dev/null
+++ b/arch/nds32/include/asm/irqflags.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+#define arch_local_irq_disable()   \
+   GIE_DISABLE();
+
+#define arch_local_irq_enable()\
+   GIE_ENABLE();
+static inline unsigned long arch_local_irq_save(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   GIE_DISABLE();
+   return flags;
+}
+
+static inline unsigned long arch_local_save_flags(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+   if(flags)
+   GIE_ENABLE();
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+   return !flags;
+}
diff --git a/arch/nds32/kernel/irq.c b/arch/nds32/kernel/irq.c
new file mode 100644
index 000..6ff5a67
--- /dev/null
+++ b/arch/nds32/kernel/irq.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+
+void __init init_IRQ(void)
+{
+   irqchip_init();
+}
-- 
1.7.9.5

[PATCH v6 15/36] nds32: Device specific operations

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch introduces ioremap implementations.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/io.h |   83 +++
 arch/nds32/mm/ioremap.c |   62 
 2 files changed, 145 insertions(+)
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/mm/ioremap.c

diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 000..966e71b
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_IO_H
+#define __ASM_NDS32_IO_H
+
+extern void iounmap(volatile void __iomem *addr);
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+   asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+   asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+   asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+   u8 val;
+
+   asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+   u16 val;
+
+   asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+   u32 val;
+
+   asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __iormb()   rmb()
+#define __iowmb()   wmb()
+
+#define mmiowb()__asm__ __volatile__ ("msync all" : : : "memory");
+
+/*
+ * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
+ * are not guaranteed to provide ordering against spinlocks or memory
+ * accesses.
+ */
+
+#define readb_relaxed(c)   ({ u8  __v = __raw_readb(c); __v; })
+#define readw_relaxed(c)   ({ u16 __v = le16_to_cpu((__force 
__le16)__raw_readw(c)); __v; })
+#define readl_relaxed(c)   ({ u32 __v = le32_to_cpu((__force 
__le32)__raw_readl(c)); __v; })
+#define writeb_relaxed(v,c)((void)__raw_writeb((v),(c)))
+#define writew_relaxed(v,c)((void)__raw_writew((__force 
u16)cpu_to_le16(v),(c)))
+#define writel_relaxed(v,c)((void)__raw_writel((__force 
u32)cpu_to_le32(v),(c)))
+
+/*
+ * {read,write}{b,w,l,q}() access little endian memory and return result in
+ * native endianness.
+ */
+#define readb(c)   ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)   ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)   ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)({ __iowmb(); writeb_relaxed((v),(c)); })
+#define writew(v,c)({ __iowmb(); writew_relaxed((v),(c)); })
+#define writel(v,c)({ __iowmb(); writel_relaxed((v),(c)); })
+#include 
+#endif /* __ASM_NDS32_IO_H */
diff --git a/arch/nds32/mm/ioremap.c b/arch/nds32/mm/ioremap.c
new file mode 100644
index 000..690140b
--- /dev/null
+++ b/arch/nds32/mm/ioremap.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
+
+static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size,
+ void *caller)
+{
+   struct vm_struct *area;
+   unsigned long addr, offset, last_addr;
+   pgprot_t prot;
+
+   /* Don't allow wraparound or zero size */
+   last_addr = phys_addr + size - 1;
+   if (!size || last_addr < phys_addr)
+   return NULL;
+
+   /*
+* Mappings have to be page-aligned
+*/
+   offset = phys_addr & ~PAGE_MASK;
+   phys_addr &= PAGE_MASK;
+   size = PAGE_ALIGN(last_addr + 1) - phys_addr;
+
+   /*
+* Ok, go for it..
+*/
+   area = get_vm_area_caller(size, VM_IOREMAP, caller);
+   if (!area)
+   return NULL;
+
+   area->phys_addr = phys_addr;
+   addr = (unsigned long)area->addr;
+   prot = __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D |
+   _PAGE_G | _PAGE_C_DEV);
+   if (iorem

[PATCH v6 17/36] nds32: ELF definitions

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds definitions for the ELF format, relocation types, vdso
locations and EXEC_PAGESIZE.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/elf.h |  171 ++
 arch/nds32/include/uapi/asm/auxvec.h |   12 +++
 arch/nds32/include/uapi/asm/param.h  |   11 +++
 3 files changed, 194 insertions(+)
 create mode 100644 arch/nds32/include/asm/elf.h
 create mode 100644 arch/nds32/include/uapi/asm/auxvec.h
 create mode 100644 arch/nds32/include/uapi/asm/param.h

diff --git a/arch/nds32/include/asm/elf.h b/arch/nds32/include/asm/elf.h
new file mode 100644
index 000..56c4790
--- /dev/null
+++ b/arch/nds32/include/asm/elf.h
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASMNDS32_ELF_H
+#define __ASMNDS32_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include 
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_freg_t[3];
+
+extern unsigned int elf_hwcap;
+
+#define EM_NDS32   167
+
+#define R_NDS32_NONE   0
+#define R_NDS32_16_RELA19
+#define R_NDS32_32_RELA20
+#define R_NDS32_9_PCREL_RELA   22
+#define R_NDS32_15_PCREL_RELA  23
+#define R_NDS32_17_PCREL_RELA  24
+#define R_NDS32_25_PCREL_RELA  25
+#define R_NDS32_HI20_RELA  26
+#define R_NDS32_LO12S3_RELA27
+#define R_NDS32_LO12S2_RELA28
+#define R_NDS32_LO12S1_RELA29
+#define R_NDS32_LO12S0_RELA30
+#define R_NDS32_SDA15S3_RELA   31
+#define R_NDS32_SDA15S2_RELA   32
+#define R_NDS32_SDA15S1_RELA   33
+#define R_NDS32_SDA15S0_RELA   34
+#define R_NDS32_GOT20  37
+#define R_NDS32_25_PLTREL  38
+#define R_NDS32_COPY   39
+#define R_NDS32_GLOB_DAT   40
+#define R_NDS32_JMP_SLOT   41
+#define R_NDS32_RELATIVE   42
+#define R_NDS32_GOTOFF 43
+#define R_NDS32_GOTPC2044
+#define R_NDS32_GOT_HI20   45
+#define R_NDS32_GOT_LO12   46
+#define R_NDS32_GOTPC_HI20 47
+#define R_NDS32_GOTPC_LO12 48
+#define R_NDS32_GOTOFF_HI2049
+#define R_NDS32_GOTOFF_LO1250
+#define R_NDS32_INSN16 51
+#define R_NDS32_LABEL  52
+#define R_NDS32_LONGCALL1  53
+#define R_NDS32_LONGCALL2  54
+#define R_NDS32_LONGCALL3  55
+#define R_NDS32_LONGJUMP1  56
+#define R_NDS32_LONGJUMP2  57
+#define R_NDS32_LONGJUMP3  58
+#define R_NDS32_LOADSTORE  59
+#define R_NDS32_9_FIXED_RELA   60
+#define R_NDS32_15_FIXED_RELA  61
+#define R_NDS32_17_FIXED_RELA  62
+#define R_NDS32_25_FIXED_RELA  63
+#define R_NDS32_PLTREL_HI2064
+#define R_NDS32_PLTREL_LO1265
+#define R_NDS32_PLT_GOTREL_HI2066
+#define R_NDS32_PLT_GOTREL_LO1267
+#define R_NDS32_LO12S0_ORI_RELA72
+#define R_NDS32_DWARF2_OP1_RELA77
+#define R_NDS32_DWARF2_OP2_RELA78
+#define R_NDS32_DWARF2_LEB_RELA79
+#define R_NDS32_WORD_9_PCREL_RELA  94
+#define R_NDS32_LONGCALL4  107
+#define R_NDS32_RELA_NOP_MIX   192
+#define R_NDS32_RELA_NOP_MAX   255
+
+#define ELF_NGREG (sizeof (struct user_pt_regs) / sizeof(elf_greg_t))
+#define ELF_CORE_COPY_REGS(dest, regs) \
+   *(struct user_pt_regs *)&(dest) = (regs)->user_regs;
+
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* Core file format: The core file is written in such a way that gdb
+   can understand it and provide useful information to the user (under
+   linux we use the 'trad-core' bfd).  There are quite a number of
+   obstacles to being able to view the contents of the floating point
+   registers, and until these are solved you will not be able to view the
+   contents of them.  Actually, you can read in the core file and look at
+   the contents of the user struct to find out what the floating point
+   registers contain.
+   The actual file contents are as follows:
+   UPAGE: 1 page consisting of a user struct that tells gdb what is present
+   in the file.  Directly after this is a copy of the task_struct, which
+   is currently not used by gdb, but it may come in useful at some point.
+   All of the registers are stored as part of the upage.  The upage should
+   always be only one page.
+   DATA: The data area is stored.  We use current->end_text to
+   current->brk to pick up all of the user variables, plus any memory
+   that may have been malloced.  No attempt is made to determine if a page
+   is demand-zero or if a page i

[PATCH v6 20/36] nds32: Signal handling support

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds support for signal handling.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/uapi/asm/sigcontext.h |   60 ++
 arch/nds32/kernel/signal.c   |  337 ++
 2 files changed, 397 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h
 create mode 100644 arch/nds32/kernel/signal.c

diff --git a/arch/nds32/include/uapi/asm/sigcontext.h 
b/arch/nds32/include/uapi/asm/sigcontext.h
new file mode 100644
index 000..00567b2
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/sigcontext.h
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_SIGCONTEXT_H
+#define _ASMNDS32_SIGCONTEXT_H
+
+/*
+ * Signal context structure - contains all info to do with the state
+ * before the signal handler was invoked.  Note: only add new entries
+ * to the end of the structure.
+ */
+
+struct zol_struct {
+   unsigned long nds32_lc; /* $LC */
+   unsigned long nds32_le; /* $LE */
+   unsigned long nds32_lb; /* $LB */
+};
+
+struct sigcontext {
+   unsigned long trap_no;
+   unsigned long error_code;
+   unsigned long oldmask;
+   unsigned long nds32_r0;
+   unsigned long nds32_r1;
+   unsigned long nds32_r2;
+   unsigned long nds32_r3;
+   unsigned long nds32_r4;
+   unsigned long nds32_r5;
+   unsigned long nds32_r6;
+   unsigned long nds32_r7;
+   unsigned long nds32_r8;
+   unsigned long nds32_r9;
+   unsigned long nds32_r10;
+   unsigned long nds32_r11;
+   unsigned long nds32_r12;
+   unsigned long nds32_r13;
+   unsigned long nds32_r14;
+   unsigned long nds32_r15;
+   unsigned long nds32_r16;
+   unsigned long nds32_r17;
+   unsigned long nds32_r18;
+   unsigned long nds32_r19;
+   unsigned long nds32_r20;
+   unsigned long nds32_r21;
+   unsigned long nds32_r22;
+   unsigned long nds32_r23;
+   unsigned long nds32_r24;
+   unsigned long nds32_r25;
+   unsigned long nds32_fp; /* $r28 */
+   unsigned long nds32_gp; /* $r29 */
+   unsigned long nds32_lp; /* $r30 */
+   unsigned long nds32_sp; /* $r31 */
+   unsigned long nds32_ipc;
+   unsigned long fault_address;
+   unsigned long used_math_flag;
+   /* FPU Registers */
+   struct zol_struct zol;
+};
+
+#endif
diff --git a/arch/nds32/kernel/signal.c b/arch/nds32/kernel/signal.c
new file mode 100644
index 000..b6313dd
--- /dev/null
+++ b/arch/nds32/kernel/signal.c
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+struct rt_sigframe {
+   struct siginfo info;
+   struct ucontext uc;
+};
+
+static int restore_sigframe(struct pt_regs *regs,
+   struct rt_sigframe __user * sf)
+{
+   sigset_t set;
+   int err;
+
+   err = __copy_from_user(, >uc.uc_sigmask, sizeof(set));
+   if (err == 0) {
+   set_current_blocked();
+   }
+
+   __get_user_error(regs->uregs[0], >uc.uc_mcontext.nds32_r0, err);
+   __get_user_error(regs->uregs[1], >uc.uc_mcontext.nds32_r1, err);
+   __get_user_error(regs->uregs[2], >uc.uc_mcontext.nds32_r2, err);
+   __get_user_error(regs->uregs[3], >uc.uc_mcontext.nds32_r3, err);
+   __get_user_error(regs->uregs[4], >uc.uc_mcontext.nds32_r4, err);
+   __get_user_error(regs->uregs[5], >uc.uc_mcontext.nds32_r5, err);
+   __get_user_error(regs->uregs[6], >uc.uc_mcontext.nds32_r6, err);
+   __get_user_error(regs->uregs[7], >uc.uc_mcontext.nds32_r7, err);
+   __get_user_error(regs->uregs[8], >uc.uc_mcontext.nds32_r8, err);
+   __get_user_error(regs->uregs[9], >uc.uc_mcontext.nds32_r9, err);
+   __get_user_error(regs->uregs[10], >uc.uc_mcontext.nds32_r10, err);
+   __get_user_error(regs->uregs[11], >uc.uc_mcontext.nds32_r11, err);
+   __get_user_error(regs->uregs[12], >uc.uc_mcontext.nds32_r12, err);
+   __get_user_error(regs->uregs[13], >uc.uc_mcontext.nds32_r13, err);
+   __get_user_error(regs->uregs[14], >uc.uc_mcontext.nds32_r14, err);
+   __get_user_error(regs->uregs[15], >uc.uc_mcontext.nds32_r15, err);
+   __get_user_error(regs->uregs[16], >uc.uc_mcontext.nds32_r16, err);
+   __get_user_error(regs->uregs[17], >uc.uc_mcontext.nds32_r17, err);
+   __get_user_error(regs->uregs[18], >uc.uc_mcontext.nds32_r18, err);
+   __get_user_error(regs->uregs[19], >uc.uc_mcontext.nds32_r19, err);
+   __get_user_error(regs->uregs[20], >

[PATCH v6 18/36] nds32: System calls handling

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds support for system calls.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/syscall.h |  188 ++
 arch/nds32/include/asm/syscalls.h|   13 +++
 arch/nds32/include/asm/unistd.h  |6 ++
 arch/nds32/include/uapi/asm/unistd.h |   11 ++
 arch/nds32/kernel/ex-scall.S |  106 +++
 arch/nds32/kernel/sys_nds32.c|   50 +
 arch/nds32/kernel/syscall_table.c|   17 +++
 7 files changed, 391 insertions(+)
 create mode 100644 arch/nds32/include/asm/syscall.h
 create mode 100644 arch/nds32/include/asm/syscalls.h
 create mode 100644 arch/nds32/include/asm/unistd.h
 create mode 100644 arch/nds32/include/uapi/asm/unistd.h
 create mode 100644 arch/nds32/kernel/ex-scall.S
 create mode 100644 arch/nds32/kernel/sys_nds32.c
 create mode 100644 arch/nds32/kernel/syscall_table.c

diff --git a/arch/nds32/include/asm/syscall.h b/arch/nds32/include/asm/syscall.h
new file mode 100644
index 000..f7e5e86
--- /dev/null
+++ b/arch/nds32/include/asm/syscall.h
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2008-2009 Red Hat, Inc.  All rights reserved.
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_SYSCALL_H
+#define _ASM_NDS32_SYSCALL_H   1
+
+#include 
+struct task_struct;
+struct pt_regs;
+
+/**
+ * syscall_get_nr - find what system call a task is executing
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * If @task is executing a system call or is at system call
+ * tracing about to attempt one, returns the system call number.
+ * If @task is not executing a system call, i.e. it's blocked
+ * inside the kernel for a fault or signal, returns -1.
+ *
+ * Note this returns int even on 64-bit machines.  Only 32 bits of
+ * system call number can be meaningful.  If the actual arch value
+ * is 64 bits, this truncates to 32 bits so 0x means -1.
+ *
+ * It's only valid to call this when @task is known to be blocked.
+ */
+int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->syscallno;
+}
+
+/**
+ * syscall_rollback - roll back registers after an aborted system call
+ * @task:  task of interest, must be in system call exit tracing
+ * @regs:  task_pt_regs() of @task
+ *
+ * It's only valid to call this when @task is stopped for system
+ * call exit tracing (due to TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT),
+ * after tracehook_report_syscall_entry() returned nonzero to prevent
+ * the system call from taking place.
+ *
+ * This rolls back the register state in @regs so it's as if the
+ * system call instruction was a no-op.  The registers containing
+ * the system call number and arguments are as they were before the
+ * system call instruction.  This may not be the same as what the
+ * register state looked like at system call entry tracing.
+ */
+void syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+   regs->uregs[0] = regs->orig_r0;
+}
+
+/**
+ * syscall_get_error - check result of traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns 0 if the system call succeeded, or -ERRORCODE if it failed.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+   unsigned long error = regs->uregs[0];
+   return IS_ERR_VALUE(error) ? error : 0;
+}
+
+/**
+ * syscall_get_return_value - get the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns the return value of the successful system call.
+ * This value is meaningless if syscall_get_error() returned nonzero.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->uregs[0];
+}
+
+/**
+ * syscall_set_return_value - change the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ * @error: negative error code, or zero to indicate success
+ * @val:   user return value if @error is zero
+ *
+ * This changes the results of the system call that user mode will see.
+ * If @error is zero, the user sees a successful system call with a
+ * return value of @val.  If @error is nonzero, it's a negated errno
+ * code; the user sees a failed system call with this errno code.
+ *
+ * It's only valid to call this when @task is stopped for tracing on

[PATCH v6 21/36] nds32: Library functions

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch add support for various library functions.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/string.h  |   17 +++
 arch/nds32/include/asm/swab.h|   35 +
 arch/nds32/include/asm/uaccess.h |  283 ++
 arch/nds32/kernel/nds32_ksyms.c  |   31 +
 arch/nds32/lib/Makefile  |3 +
 arch/nds32/lib/clear_user.S  |   42 ++
 arch/nds32/lib/copy_from_user.S  |   45 ++
 arch/nds32/lib/copy_template.S   |   70 ++
 arch/nds32/lib/copy_to_user.S|   45 ++
 arch/nds32/lib/memcpy.S  |   30 
 arch/nds32/lib/memmove.S |   70 ++
 arch/nds32/lib/memset.S  |   33 +
 arch/nds32/lib/memzero.S |   18 +++
 13 files changed, 722 insertions(+)
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/swab.h
 create mode 100644 arch/nds32/include/asm/uaccess.h
 create mode 100644 arch/nds32/kernel/nds32_ksyms.c
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/clear_user.S
 create mode 100644 arch/nds32/lib/copy_from_user.S
 create mode 100644 arch/nds32/lib/copy_template.S
 create mode 100644 arch/nds32/lib/copy_to_user.S
 create mode 100644 arch/nds32/lib/memcpy.S
 create mode 100644 arch/nds32/lib/memmove.S
 create mode 100644 arch/nds32/lib/memset.S
 create mode 100644 arch/nds32/lib/memzero.S

diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 000..179272c
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_STRING_H
+#define __ASM_NDS32_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+extern void *memzero(void *ptr, __kernel_size_t n);
+#endif
diff --git a/arch/nds32/include/asm/swab.h b/arch/nds32/include/asm/swab.h
new file mode 100644
index 000..e01a755
--- /dev/null
+++ b/arch/nds32/include/asm/swab.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_SWAB_H__
+#define __NDS32_SWAB_H__
+
+#include 
+#include 
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+   __asm__("wsbh   %0, %0\n\t" /* word swap byte within halfword */
+   "rotri  %0, %0, #16\n"
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+   __asm__("wsbh   %0, %0\n"   /* word swap byte within halfword */
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+#define __arch_swab32(x) ___arch__swab32(x)
+#define __arch_swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#define __BYTEORDER_HAS_U64__
+#define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __NDS32_SWAB_H__ */
diff --git a/arch/nds32/include/asm/uaccess.h b/arch/nds32/include/asm/uaccess.h
new file mode 100644
index 000..18a009f
--- /dev/null
+++ b/arch/nds32/include/asm/uaccess.h
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMANDES_UACCESS_H
+#define _ASMANDES_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define VERIFY_READ0
+#define VERIFY_WRITE   1
+
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+   unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+#define KERNEL_DS  ((mm_segment_t) { ~0UL })
+#define USER_DS((mm_segment_t) {TASK_SIZE - 1})
+
+#define get_ds()   (KERNEL_DS)
+#define get_fs()   (current_thread_info()->addr_limit)
+#define user_addr_max  get_fs
+
+static inline void set_fs(mm_segment_t fs)
+{
+   curre

[PATCH v6 22/36] nds32: Debugging support

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds ptrace support.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/uapi/asm/ptrace.h |   25 +++
 arch/nds32/kernel/ptrace.c   |  311 ++
 2 files changed, 336 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ptrace.c

diff --git a/arch/nds32/include/uapi/asm/ptrace.h 
b/arch/nds32/include/uapi/asm/ptrace.h
new file mode 100644
index 000..358c99e
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/ptrace.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __UAPI_ASM_NDS32_PTRACE_H
+#define __UAPI_ASM_NDS32_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * User structures for general purpose register.
+ */
+struct user_pt_regs {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+   long lb;
+   long le;
+   long lc;
+   long syscallno;
+};
+#endif
+#endif
diff --git a/arch/nds32/kernel/ptrace.c b/arch/nds32/kernel/ptrace.c
new file mode 100644
index 000..0e18564
--- /dev/null
+++ b/arch/nds32/kernel/ptrace.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+enum nds32_regset {
+   REGSET_GPR,
+};
+
+static int gpr_get(struct task_struct *target,
+  const struct user_regset *regset,
+  unsigned int pos, unsigned int count,
+  void *kbuf, void __user * ubuf)
+{
+   struct user_pt_regs *uregs = _pt_regs(target)->user_regs;
+   return user_regset_copyout(, , , , uregs, 0, -1);
+}
+
+static int gpr_set(struct task_struct *target, const struct user_regset 
*regset,
+  unsigned int pos, unsigned int count,
+  const void *kbuf, const void __user * ubuf)
+{
+   int err;
+   struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
+
+   err = user_regset_copyin(, , , , , 0, -1);
+   if (err)
+   return err;
+
+   task_pt_regs(target)->user_regs = newregs;
+   return 0;
+}
+
+static const struct user_regset nds32_regsets[] = {
+   [REGSET_GPR] = {
+   .core_note_type = NT_PRSTATUS,
+   .n = sizeof(struct user_pt_regs) / sizeof(u32),
+   .size = sizeof(u32),
+   .align = sizeof(u32),
+   .get = gpr_get,
+   .set = gpr_set}
+};
+
+static const struct user_regset_view nds32_user_view = {
+   .name = "nds32",.e_machine = EM_NDS32,
+   .regsets = nds32_regsets,.n = ARRAY_SIZE(nds32_regsets)
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+   return _user_view;
+}
+
+/* get_user_reg()
+ *
+ * This routine will get a word off of the processes privileged stack.
+ * the offset is how far from the base addr as stored in the THREAD.
+ * this routine assumes that all the privileged stacks are in our
+ * data space.
+ */
+static inline unsigned int get_user_reg(struct task_struct *task, int offset)
+{
+   return task_pt_regs(task)->uregs[offset];
+}
+
+/* put_user_reg()
+ *
+ * this routine will put a word on the processes privileged stack.
+ * the offset is how far from the base addr as stored in the THREAD.
+ * this routine assumes that all the privileged stacks are in our
+ * data space.
+ */
+static inline int put_user_reg(struct task_struct *task, int offset, long data)
+{
+   struct pt_regs newregs, *regs = task_pt_regs(task);
+   int ret = -EINVAL;
+
+   newregs = *regs;
+   newregs.uregs[offset] = data;
+
+   if (valid_user_regs()) {
+   regs->uregs[offset] = data;
+   ret = 0;
+   }
+
+   return ret;
+}
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ *
+ * Make sure the single step bit is not set.
+ */
+void ptrace_disable(struct task_struct *child)
+{
+   user_disable_single_step(child);
+}
+
+static void fill_sigtrap_info(struct task_struct *tsk,
+ struct pt_regs *regs,
+ int error_code, int si_code, struct siginfo *info)
+{
+   tsk->thread.trap_no = ENTRY_DEBUG_RELATED;
+   tsk->thread.error_code = error_code;
+
+   memset(info, 0, sizeof(*info));
+   info->si_signo = SIGTRAP;
+   info->si_code = si_code;
+   info->si_addr = (void __user *)instruction_pointer(regs);
+}
+
+void user_single_step_siginfo(struct task_struct *tsk,
+ struct pt_regs *regs, struct siginfo *info)
+

[PATCH v6 23/36] nds32: L2 cache support

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds L2 cache support.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/l2_cache.h |  137 +
 arch/nds32/kernel/atl2c.c |   64 +
 2 files changed, 201 insertions(+)
 create mode 100644 arch/nds32/include/asm/l2_cache.h
 create mode 100644 arch/nds32/kernel/atl2c.c

diff --git a/arch/nds32/include/asm/l2_cache.h 
b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index 000..37dd5ef
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#define L2_IF_CONF_OFF 0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF  0xC
+#define L2CC_CTRL_OFF  0x10
+#define L2_INT_EN_OFF   0x20
+#define L2_STA_OFF  0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF  0x30
+#define IMPL3ERR_ADDR_OFF  0x34
+#define L2_CNT0_CTRL_OFF0x40
+#define L2_EVNT_CNT0_OFF0x44
+#define L2_CNT1_CTRL_OFF0x48
+#define L2_EVNT_CNT1_OFF0x4c
+#define L2_CCTL_CMD_OFF0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF0x68
+#define L2_LINE_DPT_OFF0x70
+
+#define CCTL_CMD_L2_IX_INVAL0x0
+#define CCTL_CMD_L2_PA_INVAL0x1
+#define CCTL_CMD_L2_IX_WB   0x2
+#define CCTL_CMD_L2_PA_WB   0x3
+#define CCTL_CMD_L2_PA_WBINVAL  0x5
+#define CCTL_CMD_L2_SYNC0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD  0x10
+#define CCTL_ALL_CMD   0x10
+
+/**
+ * L2_CA_CONF (Cache architecture configuration)
+ */
+#define L2_CA_CONF_offL2SET0
+#define L2_CA_CONF_offL2WAY4
+#define L2_CA_CONF_offL2CLSZ8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER16
+
+#define L2_CA_CONF_mskL2SET(0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY(0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ(0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER(0xUL << L2_CA_CONF_offL2VER)
+
+/**
+ * L2CC_SETUP (L2CC Setup register)
+ */
+#define L2CC_SETUP_offPART  0
+#define L2CC_SETUP_mskPART  (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC4
+#define L2CC_SETUP_mskDDLATC(0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC8
+#define L2CC_SETUP_mskTDLATC(0x3UL << L2CC_SETUP_offTDLATC)
+
+/**
+ * L2CC_PROT (L2CC Protect register)
+ */
+#define L2CC_PROT_offMRWEN  31
+#define L2CC_PROT_mskMRWEN  (0x1UL << L2CC_PROT_offMRWEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2_CCTL_STATUS_offCMD_COMP  31
+#define L2_CCTL_STATUS_mskCMD_COMP  (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+
+extern void __iomem *atl2c_base;
+#include 
+#include 
+#include 
+
+#define L2C_R_REG(offset)   readl(atl2c_base + offset)
+#define L2C_W_REG(offset, value)writel(value, atl2c_base + offset)
+
+#define L2_CMD_RDY()\
+do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & 
L2_CCTL_STATUS_mskCMD_COMP) == 0)
+
+static inline unsigned long L2_CACHE_SET(void)
+{
+   return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+}
+
+static inline unsign

[PATCH v6 25/36] nds32: Generic timers support

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds support for timer.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Linus Walleij <linus.wall...@linaro.org>
---
 arch/nds32/kernel/time.c |   11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/nds32/kernel/time.c

diff --git a/arch/nds32/kernel/time.c b/arch/nds32/kernel/time.c
new file mode 100644
index 000..ac9d78c
--- /dev/null
+++ b/arch/nds32/kernel/time.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+void __init time_init(void)
+{
+   of_clk_init(NULL);
+   timer_probe();
+}
-- 
1.7.9.5

[PATCH v6 26/36] nds32: Device tree support

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds support for device tree.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/boot/dts/Makefile  |8 
 arch/nds32/boot/dts/ae3xx.dts |   85 +
 arch/nds32/kernel/devtree.c   |   19 +
 3 files changed, 112 insertions(+)
 create mode 100644 arch/nds32/boot/dts/Makefile
 create mode 100644 arch/nds32/boot/dts/ae3xx.dts
 create mode 100644 arch/nds32/kernel/devtree.c

diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
new file mode 100644
index 000..d31faa8
--- /dev/null
+++ b/arch/nds32/boot/dts/Makefile
@@ -0,0 +1,8 @@
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
new file mode 100644
index 000..bb39749
--- /dev/null
+++ b/arch/nds32/boot/dts/ae3xx.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x 0x4000>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0>;
+   clock-frequency = <6000>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
+
+   clock: clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <3000>;
+   };
+
+   apb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   serial0: serial@f030 {
+   compatible = "andestech,uart16550", "ns16550a";
+   reg = <0xf030 0x1000>;
+   interrupts = <8>;
+   clock-frequency = <14745600>;
+   reg-shift = <2>;
+   reg-offset = <32>;
+   no-loopback-test = <1>;
+   };
+
+   timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <>;
+   clock-names = "PCLK";
+   };
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   L2: cache-controller@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
+   mac0: ethernet@e010 {
+   compatible = "andestech,atmac100";
+   reg = <0xe010 0x1000>;
+   interrupts = <18>;
+   };
+   };
+};
diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c
new file mode 100644
index 000..bdce0fe
--- /dev/null
+++ b/arch/nds32/kernel/devtree.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+
+void __init early_init_devtree(void *params)
+{
+   if (!params || !early_init_dt_scan(params)) {
+   pr_crit("\n"
+   "Error: invalid device tree blob at (virtual address 
0x%p)\n"
+   "\nPlease check your bootloader.", params);
+
+   BUG_ON(1);
+   }
+
+   dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
+}
-- 
1.7.9.5

[PATCH v6 24/36] nds32: Loadable modules

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds support for loadable modules.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/module.h |   11 ++
 arch/nds32/kernel/module.c  |  286 +++
 2 files changed, 297 insertions(+)
 create mode 100644 arch/nds32/include/asm/module.h
 create mode 100644 arch/nds32/kernel/module.c

diff --git a/arch/nds32/include/asm/module.h b/arch/nds32/include/asm/module.h
new file mode 100644
index 000..16cf9c7
--- /dev/null
+++ b/arch/nds32/include/asm/module.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_MODULE_H
+#define _ASM_NDS32_MODULE_H
+
+#include 
+
+#define MODULE_ARCH_VERMAGIC   "NDS32v3"
+
+#endif /* _ASM_NDS32_MODULE_H */
diff --git a/arch/nds32/kernel/module.c b/arch/nds32/kernel/module.c
new file mode 100644
index 000..714a6d6
--- /dev/null
+++ b/arch/nds32/kernel/module.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+
+#include 
+
+void *module_alloc(unsigned long size)
+{
+   return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
+   GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,
+   __builtin_return_address(0));
+}
+
+void module_free(struct module *module, void *region)
+{
+   vfree(region);
+}
+
+int module_frob_arch_sections(Elf_Ehdr * hdr,
+ Elf_Shdr * sechdrs,
+ char *secstrings, struct module *mod)
+{
+   return 0;
+}
+
+void do_reloc16(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"2:\n"
+"\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+void do_reloc32(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlmw.bi\t%0, [%2], %0, 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"2:\n"
+"\tsmw.bi\t%0, [%2], %0, 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+static inline int exceed_limit(int offset, unsigned int val_mask,
+  struct module *module, Elf32_Rela * rel,
+  unsigned int relindex, unsigned int reloc_order)
+{
+   int abs_off = offset < 0 ? ~offset : offset;
+
+   if (abs_off & (~val_mask)) {
+   pr_err("\n%s: relocation type %d out of range.\n"
+  "please rebuild the kernel module with gcc option 
\"-Wa,-mno-small-text\".\n",
+

[PATCH v6 30/36] MAINTAINERS: Add nds32

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 MAINTAINERS |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2f4e462..20284c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -857,6 +857,17 @@ X: drivers/iio/*/adjd*
 F: drivers/staging/iio/*/ad*
 F: drivers/staging/iio/trigger/iio-trig-bfin-timer.c
 
+ANDES ARCHITECTURE
+M:     Greentime Hu <green...@gmail.com>
+M: Vincent Chen <deanbo...@gmail.com>
+T: git https://github.com/andestech/linux.git
+S: Supported
+F: arch/nds32
+F: 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
+F: Documentation/devicetree/bindings/nds32
+K: nds32
+N: nds32
+
 ANDROID CONFIG FRAGMENTS
 M: Rob Herring <r...@kernel.org>
 S: Supported
-- 
1.7.9.5

[PATCH v6 28/36] nds32: defconfig

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds nds32 defconfig.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/configs/defconfig |  107 ++
 1 file changed, 107 insertions(+)
 create mode 100644 arch/nds32/configs/defconfig

diff --git a/arch/nds32/configs/defconfig b/arch/nds32/configs/defconfig
new file mode 100644
index 000..53d1778
--- /dev/null
+++ b/arch/nds32/configs/defconfig
@@ -0,0 +1,107 @@
+CONFIG_CROSS_COMPILE="nds32le-linux-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CACHE_L2 is not set
+CONFIG_VMSPLIT_3G_OPT=y
+CONFIG_PREEMPT=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_FTMAC100=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_USE_LEGACY_DNS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_GDB_SCRIPTS=y
+CONFIG_READABLE_ASM=y
+CONFIG_HEADERS_CHECK=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_PANIC_ON_OOPS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=300
+# CONFIG_CRYPTO_HW is not set
-- 
1.7.9.5

[PATCH v6 27/36] nds32: Miscellaneous header files

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch introduces some miscellaneous header files.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/include/asm/delay.h  |   39 +++
 arch/nds32/include/asm/linkage.h|   11 +
 arch/nds32/include/uapi/asm/byteorder.h |   13 +++
 3 files changed, 63 insertions(+)
 create mode 100644 arch/nds32/include/asm/delay.h
 create mode 100644 arch/nds32/include/asm/linkage.h
 create mode 100644 arch/nds32/include/uapi/asm/byteorder.h

diff --git a/arch/nds32/include/asm/delay.h b/arch/nds32/include/asm/delay.h
new file mode 100644
index 000..519ba97
--- /dev/null
+++ b/arch/nds32/include/asm/delay.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_DELAY_H__
+#define __NDS32_DELAY_H__
+
+#include 
+
+/* There is no clocksource cycle counter in the CPU. */
+static inline void __delay(unsigned long loops)
+{
+   __asm__ __volatile__(".align 2\n"
+"1:\n"
+"\taddi\t%0, %0, -1\n"
+"\tbgtz\t%0, 1b\n"
+:"=r"(loops)
+:"0"(loops));
+}
+
+static inline void __udelay(unsigned long usecs, unsigned long lpj)
+{
+   usecs *= (unsigned long)(((0x8000ULL / (50 / HZ)) +
+ 0x8000ULL) >> 32);
+   usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
+   __delay(usecs);
+}
+
+#define udelay(usecs) __udelay((usecs), loops_per_jiffy)
+
+/* make sure "usecs *= ..." in udelay do not overflow. */
+#if HZ >= 1000
+#define MAX_UDELAY_MS  1
+#elif HZ <= 200
+#define MAX_UDELAY_MS  5
+#else
+#define MAX_UDELAY_MS  (1000 / HZ)
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h
new file mode 100644
index 000..e708c8b
--- /dev/null
+++ b/arch/nds32/include/asm/linkage.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* This file is required by include/linux/linkage.h */
+#define __ALIGN .align 2
+#define __ALIGN_STR ".align 2"
+
+#endif
diff --git a/arch/nds32/include/uapi/asm/byteorder.h 
b/arch/nds32/include/uapi/asm/byteorder.h
new file mode 100644
index 000..a23f6f3a
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/byteorder.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BYTEORDER_H__
+#define __NDS32_BYTEORDER_H__
+
+#ifdef __NDS32_EB__
+#include 
+#else
+#include 
+#endif
+
+#endif /* __NDS32_BYTEORDER_H__ */
-- 
1.7.9.5

[PATCH v6 31/36] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds nds32 CPU binding documents.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Rick Chen <r...@andestech.com>
Signed-off-by: Zong Li <z...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/nds32/cpus.txt |   37 ++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt

diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
b/Documentation/devicetree/bindings/nds32/cpus.txt
new file mode 100644
index 000..9a52937
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/cpus.txt
@@ -0,0 +1,37 @@
+* Andestech Processor Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Andestech Processor Core, which is the root node in the
+tree.
+
+Required properties:
+
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: should be one of:
+   "andestech,n13"
+   "andestech,n15"
+   "andestech,d15"
+   "andestech,n10"
+   "andestech,d10"
+   "andestech,nds32v3"
+   - device_type
+   Usage: required
+   Value type: 
+   Definition: must be "cpu"
+   - reg: Contains CPU index.
+   - clock-frequency: Contains the clock frequency for CPU, in Hz.
+
+* Examples
+
+/ {
+   cpus {
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0x0>;
+   clock-frequency = <6000>
+   };
+   };
+};
-- 
1.7.9.5

[PATCH v6 32/36] dt-bindings: nds32 L2 cache controller Bindings

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds nds32 L2 cache controller binding documents.

Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/nds32/atl2c.txt |   29 +
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt

diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt 
b/Documentation/devicetree/bindings/nds32/atl2c.txt
new file mode 100644
index 000..6b34e04
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
@@ -0,0 +1,29 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: "andestech,atl2c"
+   - reg : Physical base address and size of cache controller's memory 
mapped
+   - cache-unified : Specifies the cache is a unified cache.
+   - cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+   cache-controller@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
-- 
1.7.9.5

[PATCH v6 29/36] nds32: Build infrastructure

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds Makefile, Kconfig and vmlinux.lds.S files required for building
an nds32 kernel.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
---
 arch/nds32/Kconfig |  107 
 arch/nds32/Kconfig.cpu |  161 
 arch/nds32/Makefile|   66 +++
 arch/nds32/boot/Makefile   |   15 
 arch/nds32/include/asm/Kbuild  |   54 
 arch/nds32/include/uapi/asm/Kbuild |   28 +++
 arch/nds32/kernel/Makefile |   23 ++
 arch/nds32/kernel/vmlinux.lds.S|   57 +
 arch/nds32/mm/Makefile |7 ++
 9 files changed, 518 insertions(+)
 create mode 100644 arch/nds32/Kconfig
 create mode 100644 arch/nds32/Kconfig.cpu
 create mode 100644 arch/nds32/Makefile
 create mode 100644 arch/nds32/boot/Makefile
 create mode 100644 arch/nds32/include/asm/Kbuild
 create mode 100644 arch/nds32/include/uapi/asm/Kbuild
 create mode 100644 arch/nds32/kernel/Makefile
 create mode 100644 arch/nds32/kernel/vmlinux.lds.S
 create mode 100644 arch/nds32/mm/Makefile

diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
new file mode 100644
index 000..56e1be1
--- /dev/null
+++ b/arch/nds32/Kconfig
@@ -0,0 +1,107 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config NDS32
+def_bool y
+   select ARCH_HAS_RAW_COPY_USER
+   select ARCH_WANT_FRAME_POINTERS if FTRACE
+   select ARCH_WANT_IPC_PARSE_VERSION
+   select CLKSRC_MMIO
+   select CLONE_BACKWARDS
+   select COMMON_CLK
+   select FRAME_POINTER
+   select GENERIC_ATOMIC64
+   select GENERIC_CPU_DEVICES
+   select GENERIC_CLOCKEVENTS
+   select GENERIC_IRQ_CHIP
+   select GENERIC_IRQ_PROBE
+   select GENERIC_IRQ_SHOW
+   select GENERIC_STRNCPY_FROM_USER
+   select GENERIC_STRNLEN_USER
+   select GENERIC_TIME_VSYSCALL
+   select HANDLE_DOMAIN_IRQ
+   select HAVE_ARCH_TRACEHOOK
+   select HAVE_DEBUG_KMEMLEAK
+   select HAVE_MEMBLOCK
+   select HAVE_REGS_AND_STACK_ACCESS_API
+   select IRQ_DOMAIN
+   select LOCKDEP_SUPPORT
+   select MODULES_USE_ELF_RELA
+   select OF
+   select OF_EARLY_FLATTREE
+   select NO_BOOTMEM
+   select NO_IOPORT_MAP
+   select RTC_LIB
+   select THREAD_INFO_IN_TASK
+   help
+ Andes(nds32) Linux support.
+
+config GENERIC_CALIBRATE_DELAY
+   def_bool n
+
+config GENERIC_CSUM
+def_bool y
+
+config GENERIC_HWEIGHT
+def_bool y
+
+config GENERIC_LOCKBREAK
+def_bool y
+   depends on PREEMPT
+
+config RWSEM_GENERIC_SPINLOCK
+   def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
+   def_bool y
+
+config STACKTRACE_SUPPORT
+def_bool y
+
+config FIX_EARLYCON_MEM
+   def_bool y
+
+config PGTABLE_LEVELS
+   default 2
+
+source "init/Kconfig"
+
+menu "System Type"
+source "arch/nds32/Kconfig.cpu"
+config NR_CPUS
+   int
+   default 1
+
+config MMU
+def_bool y
+
+config NDS32_BUILTIN_DTB
+string "Builtin DTB"
+default ""
+   help
+ User can use it to specify the dts of the SoC
+endmenu
+
+menu "Kernel Features"
+source "kernel/Kconfig.preempt"
+source "mm/Kconfig"
+source "kernel/Kconfig.hz"
+endmenu
+
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+endmenu
+
+source "net/Kconfig"
+source "drivers/Kconfig"
+source "fs/Kconfig"
+
+menu "Kernel hacking"
+source "lib/Kconfig.debug"
+endmenu
+
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
new file mode 100644
index 000..43e2f3f
--- /dev/null
+++ b/arch/nds32/Kconfig.cpu
@@ -0,0 +1,161 @@
+comment "Processor Features"
+
+config CPU_BIG_ENDIAN
+   bool "Big endian"
+
+config CPU_LITTLE_ENDIAN
+def_bool !CPU_BIG_ENDIAN
+
+config HWZOL
+   bool "hardware zero overhead loop support"
+   depends on CPU_D10 || CPU_D15
+   default n
+   help
+ A set of Zero-Overhead Loop mechanism is provided to reduce the
+ instruction fetch and execution overhead of loop-control instructions.
+ It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
+ You don't need to save these registers if you can make sure your user
+ program doesn't use these registers.
+
+ If unsure, say N.
+
+config CPU_CACHE_ALIASING
+   bool "Aliasing cache"
+   depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
+   default y
+   help
+   

[PATCH v6 33/36] dt-bindings: nds32 SoC Bindings

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds nds32 SoC(AE3XX and AG101P) binding documents.

Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/nds32/andestech-boards |   40 
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/andestech-boards

diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards 
b/Documentation/devicetree/bindings/nds32/andestech-boards
new file mode 100644
index 000..f5d7569
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/andestech-boards
@@ -0,0 +1,40 @@
+Andestech(nds32) AE3XX Platform
+-
+The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It
+is composed of one Andestech(nds32) processor and AE3XX.
+
+Required properties (in root node):
+- compatible = "andestech,ae3xx";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+};
+
+Andestech(nds32) AG101P Platform
+-
+AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
+processors to provide a cost-effective and high performance solution for
+majority of embedded systems in variety of application domains. Users may
+simply attach their IP on one of the system buses together with certain glue
+logics to complete a SoC solution for a specific application. With
+comprehensive simulation and design environments, users may evaluate the
+system performance of their applications and track bugs of their designs
+efficiently. The optional hardware development platform further provides real
+system environment for early prototyping and software/hardware co-development.
+
+Required properties (in root node):
+   compatible = "andestech,ag101p";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ag101p";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+};
-- 
1.7.9.5

[PATCH v6 34/36] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller

[Greentime Hu]

From: Greentime Hu <greent...@andestech.com>

This patch adds an irqchip driver document for the Andestech Internal Vector
Interrupt Controller.

Signed-off-by: Rick Chen <r...@andestech.com>
Signed-off-by: Greentime Hu <greent...@andestech.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 .../interrupt-controller/andestech,ativic32.txt|   19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
new file mode 100644
index 000..f4b4193
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
@@ -0,0 +1,19 @@
+* Andestech Internal Vector Interrupt Controller
+
+The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
+suitable for a simpler SoC platform not requiring a more sophisticated and
+bigger External Vector Interrupt Controller.
+
+
+Main node required properties:
+
+- compatible : should at least contain  "andestech,ativic32".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
+
+Examples:
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
-- 
1.7.9.5

[PATCH v6 0/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

[Greentime Hu]

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Changes in v6:
 - To select TIMER_OF in drivers/clocksource/Kconfig instead of 
arch/nds32/Kconfig
 - Refine Kconfig
 - Update license format to SPDX-License-Identifier

Rick Chen (3):
  clocksource/drivers/atcpit100: Add andestech atcpit100 timer
  clocksource/drivers/atcpit100: VDSO support
  dt-bindings: timer: Add andestech atcpit100 timer binding doc

 .../bindings/timer/andestech,atcpit100-timer.txt   |   33 +++
 drivers/clocksource/Kconfig|9 +
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-atcpit100.c  |  262 
 4 files changed, 305 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
 create mode 100644 drivers/clocksource/timer-atcpit100.c

-- 
1.7.9.5

[PATCH v6 2/3] clocksource/drivers/atcpit100: VDSO support

[Greentime Hu]

From: Rick Chen <rickche...@gmail.com>

VDSO needs real-time cycle count to ensure the time accuracy.
Unlike others, nds32 architecture does not define clock source,
hence VDSO needs atcpit100 offering real-time cycle count
to derive the correct time.

Signed-off-by: Vincent Chen <vince...@andestech.com>
Signed-off-by: Rick Chen <rickche...@gmail.com>
Signed-off-by: Greentime Hu <green...@gmail.com>
---
 drivers/clocksource/timer-atcpit100.c |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
index e34b2fe..4cf69e2 100644
--- a/drivers/clocksource/timer-atcpit100.c
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -18,6 +18,9 @@
 #include 
 #include 
 #include "timer-of.h"
+#ifdef CONFIG_NDS32
+#include 
+#endif
 
 /*
  * Definition of register offsets
@@ -200,6 +203,17 @@ static u64 notrace atcpit100_timer_sched_read(void)
return ~readl(timer_of_base() + CH1_CNT);
 }
 
+#ifdef CONFIG_NDS32
+static void fill_vdso_need_info(struct device_node *node)
+{
+   struct resource timer_res;
+   of_address_to_resource(node, 0, _res);
+   timer_info.mapping_base = (unsigned long)timer_res.start;
+   timer_info.cycle_count_down = true;
+   timer_info.cycle_count_reg_offset = CH1_CNT;
+}
+#endif
+
 static int __init atcpit100_timer_init(struct device_node *node)
 {
int ret;
@@ -238,6 +252,10 @@ static int __init atcpit100_timer_init(struct device_node 
*node)
val = readl(base + INT_EN);
writel(val | CH0INT0EN, base + INT_EN);
 
+#ifdef CONFIG_NDS32
+   fill_vdso_need_info(node);
+#endif
+
return ret;
 }
 
-- 
1.7.9.5

[PATCH v6 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

[Greentime Hu]

From: Rick Chen <rickche...@gmail.com>

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Signed-off-by: Rick Chen <rickche...@gmail.com>
Signed-off-by: Greentime Hu <green...@gmail.com>
Reviewed-by: Linus Walleij <linus.wall...@linaro.org>
---
 drivers/clocksource/Kconfig   |9 ++
 drivers/clocksource/Makefile  |1 +
 drivers/clocksource/timer-atcpit100.c |  244 +
 3 files changed, 254 insertions(+)
 create mode 100644 drivers/clocksource/timer-atcpit100.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cc60620..5014949 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -615,4 +615,13 @@ config CLKSRC_ST_LPC
  Enable this option to use the Low Power controller timer
  as clocksource.
 
+config ATCPIT100_TIMER
+   bool "ATCPIT100 timer driver"
+   depends on NDS32 || COMPILE_TEST
+   depends on HAS_IOMEM
+   select TIMER_OF
+   default NDS32
+   help
+ This option enables support for the Andestech ATCPIT100 timers.
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72711f1..7403a19 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
 obj-$(CONFIG_H8300_TPU)+= h8300_tpu.o
 obj-$(CONFIG_CLKSRC_ST_LPC)+= clksrc_st_lpc.o
 obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+obj-$(CONFIG_ATCPIT100_TIMER)  += timer-atcpit100.o
diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
new file mode 100644
index 000..e34b2fe
--- /dev/null
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+/*
+ *  Andestech ATCPIT100 Timer Device Driver Implementation
+ * Rick Chen, Andes Technology Corporation <r...@andestech.com>
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "timer-of.h"
+
+/*
+ * Definition of register offsets
+ */
+
+/* ID and Revision Register */
+#define ID_REV 0x0
+
+/* Configuration Register */
+#define CFG0x10
+
+/* Interrupt Enable Register */
+#define INT_EN 0x14
+#define CH_INT_EN(c, i)((1<<i)<<(4*c))
+#define CH0INT0EN  0x01
+
+/* Interrupt Status Register */
+#define INT_STA0x18
+#define CH0INT00x01
+
+/* Channel Enable Register */
+#define CH_EN  0x1C
+#define CH0TMR0EN  0x1
+#define CH1TMR0EN  0x10
+
+/* Channel 0 , 1 Control Register */
+#define CH0_CTL(0x20)
+#define CH1_CTL(0x20 + 0x10)
+
+/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
+#define APB_CLKBIT(3)
+
+/* Channel mode , bit 0~2 */
+#define TMR_32 0x1
+#define TMR_16 0x2
+#define TMR_8  0x3
+
+/* Channel 0 , 1 Reload Register */
+#define CH0_REL(0x24)
+#define CH1_REL(0x24 + 0x10)
+
+/* Channel 0 , 1 Counter Register */
+#define CH0_CNT(0x28)
+#define CH1_CNT(0x28 + 0x10)
+
+#define TIMER_SYNC_TICKS   3
+
+static void atcpit100_ch1_tmr0_en(void __iomem *base)
+{
+   writel(~0, base + CH1_REL);
+   writel(APB_CLK|TMR_32, base + CH1_CTL);
+}
+
+static void atcpit100_ch0_tmr0_en(void __iomem *base)
+{
+   writel(APB_CLK|TMR_32, base + CH0_CTL);
+}
+
+static void atcpit100_clkevt_time_setup(void __iomem *base, unsigned long 
delay)
+{
+   writel(delay, base + CH0_CNT);
+   writel(delay, base + CH0_REL);
+}
+
+static void atcpit100_timer_clear_interrupt(void __iomem *base)
+{
+   u32 val;
+
+   val = readl(base + INT_STA);
+   writel(val | CH0INT0, base + INT_STA);
+}
+
+static void atcpit100_clocksource_start(void __iomem *base)
+{
+   u32 val;
+
+   val = readl(base + CH_EN);
+   writel(val | CH1TMR0EN, base + CH_EN);
+}
+
+static void atcpit100_clkevt_time_start(void __iomem *base)
+{
+   u32 val;
+
+   val = readl(base + CH_EN);
+   writel(val | CH0TMR0EN, base + CH_EN);
+}
+
+static void atcpit100_clkevt_time_stop(void __iomem *base)
+{
+   u32 val;
+
+   atcpit100_timer_clear_interrupt(base);
+   val = readl(base + CH_EN);
+   writel(val & ~CH0TMR0EN, base + CH_EN);
+}
+
+static

[PATCH v6 3/3] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[Greentime Hu]

From: Rick Chen <rickche...@gmail.com>

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: Rick Chen <rickche...@gmail.com>
Signed-off-by: Greentime Hu <green...@gmail.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../bindings/timer/andestech,atcpit100-timer.txt   |   33 
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt

diff --git 
a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt 
b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 000..4c9ea59
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+--
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible   : Should be "andestech,atcpit100"
+- reg  : Address and length of the register set
+- interrupts   : Reference to the timer interrupt
+- clocks   : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names  : should be "PCLK" for the peripheral clock source.
+
+Examples:
+
+timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <>;
+   clock-names = "PCLK";
+};
-- 
1.7.9.5