于 2020年10月26日 GMT+08:00 上午1:28:48, Andrew Lunn 写到:
>> >> 1. As the PHY chip has hardware configuration for configuring
>delays,
>> >> we should at least have a mode that respects what's set on the
>> >hardware.
>> >
>> >Yes, that is PHY_INTERFACE_MODE_NA. In DT, set the phy-mode to "".
>Or
>> >
于 2020年10月25日 GMT+08:00 下午10:36:08, Andrew Lunn 写到:
>On Sun, Oct 25, 2020 at 10:27:05PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2020年10月25日 GMT+08:00 下午10:18:25, Andrew Lunn 写到:
>> >On Sun, Oct 25, 2020 at 04:55:56PM +0800, Icenowy Zheng wrote:
>> >>
于 2020年10月25日 GMT+08:00 下午10:18:25, Andrew Lunn 写到:
>On Sun, Oct 25, 2020 at 04:55:56PM +0800, Icenowy Zheng wrote:
>> Currently there are many boards that just set "rgmii" as phy-mode in
>the
>> device tree, and leave the hardware [TR]XDLY pins to set PHY delay
&g
y devices are
broken.
The definition of "rgmii" in the DT binding document is "RX and TX
delays are added by MAC when required", which at least literally do not
forbid the PHY to add delays.
Fixes: bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config")
于 2018年5月14日 GMT+08:00 下午12:59:22, Chen-Yu Tsai 写到:
>On Sun, May 13, 2018 at 1:29 PM, Andrew Lunn wrote:
>> On Sun, May 13, 2018 at 01:11:08PM -0700, Chen-Yu Tsai wrote:
>>> On Sun, May 13, 2018 at 1:05 PM, Andrew Lunn wrote:
>>> >> > Hi Chen-Yu
>>> >> >
>>> >> > Are these delays the MAC appli
于 2018年5月14日 GMT+08:00 上午4:05:29, Andrew Lunn 写到:
>> > Hi Chen-Yu
>> >
>> > Are these delays the MAC applies? Not the PHY. It would be good to
>> > make it clear here these are MAC imposed delays.
>>
>> Yes these are applied on the MAC side. Being described in the device
>> tree bindings for th
于 2018年5月2日 GMT+08:00 下午5:53:21, Chen-Yu Tsai 写到:
>On Wed, May 2, 2018 at 5:51 PM, Maxime Ripard
> wrote:
>> Hi,
>>
>> On Wed, May 02, 2018 at 12:12:27AM +0800, Chen-Yu Tsai wrote:
>>> From: Icenowy Zheng
>>>
>>> Allwinner A64 has a SRAM c
Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
>>> >> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng
>wrote:
>>> >> > 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard
> 写到:
>>> >> >>On Wed, Apr 11, 2018 at 10:16:39PM +0800, Icenowy
于 2018年4月17日 GMT+08:00 上午2:47:45, Rob Herring 写到:
>On Wed, Apr 11, 2018 at 10:16:37PM +0800, Icenowy Zheng wrote:
>> On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i
>is
>> in another device's memory space. In this situation dwmac-sun8i can
>use
&
于 2018年4月16日 GMT+08:00 下午10:31:30, Maxime Ripard 写到:
>On Thu, Apr 12, 2018 at 11:23:30PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Apr 12, 2018 at 11:11 PM, Icenowy Zheng
>wrote:
>> > 于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard
> 写到:
>> >>On Wed, Apr 1
于 2018年4月12日 GMT+08:00 下午10:56:28, Maxime Ripard 写到:
>On Wed, Apr 11, 2018 at 10:16:39PM +0800, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai
>>
>> On the Allwinner R40 SoC, the "GMAC clock" register is in the CCU
>> address space; on the A64 SoC th
to use regmaps with single register, change commit
message]
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 48 ++-
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/
The A64 SRAM controller memory zone has a EMAC clock register, which is
needed by the Ethernet MAC driver (dwmac-sun8i).
Export a regmap for this register on A64.
Signed-off-by: Icenowy Zheng
---
drivers/soc/sunxi/sunxi_sram.c | 48 --
1 file changed, 46
acquire its EMAC clock regmap.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64
hange commit message]
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 41 ---
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
ation.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 3d6d5fa
: stmmac: dwmac-sun8i: Use regmap_field for syscon register access
net: stmmac: dwmac-sun8i: Allow getting syscon regmap from device
Icenowy Zheng (3):
dt-bindings: allow dwmac-sun8i to use other devices' exported regmap
drivers: soc: sunxi: export a regmap for EMAC clock reg on A64
arm64:
Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote:
> > > > > From: Icenowy Zheng
> > > > >
> > > > > There's a GMAC configuration register, which exists on
> > > > > A64/A83T/H3/H5 in
> > > > > the syscon part, in
9, 2018 at 5:31 AM, Maxime Ripard
>>> > wrote:
>>> > > On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote:
>>> > >> From: Icenowy Zheng
>>> > >>
>>> > >> There's a GMAC configuration register, which exi
n Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote:
>> > >> From: Icenowy Zheng
>> > >>
>> > >> There's a GMAC configuration register, which exists on
>A64/A83T/H3/H5 in
>> > >> the syscon part, in the CCU of R40 SoC.
>
于 2018年2月3日 GMT+08:00 上午6:13:01, Maxime Ripard 写到:
>On Sat, Feb 03, 2018 at 02:04:54AM +0800, Icenowy Zheng wrote:
>> The V3s is just a differently packaged version of the V3 chip, which
>has
>> a MAC with the same capability with H3. The V3s just doesn't wire out
>>
于 2018年2月3日 GMT+08:00 下午2:00:33, Julian Calaby 写到:
>Hi Icenowy,
>
>On Sat, Feb 3, 2018 at 5:04 AM, Icenowy Zheng wrote:
>> The V3s is just a differently packaged version of the V3 chip, which
>has
>> a MAC with the same capability with H3. The V3s just doesn't wire
support for V3.
Icenowy Zheng (3):
net: stmmac: dwmac-sun8i: drop V3s compatible and add V3 one
ARM: sun8i: v3s: add V3s EMAC device tree node
ARM: sun8i: v3s: enable Ethernet port on the Lichee Pi Zero Dock
.../devicetree/bindings/net/dwmac-sun8i.txt| 10 ++--
arch/arm/boot/dts/sun8i
The V3/V3s EMAC is just similar to the one in H3 SoC, but as the package
of V3s is pin-limited, the external MII/MDIO bus is not wired out.
Add V3s EMAC device tree node. As V3s is only capable of using the
internal PHY, it's hardcoded in the V3s DTSI file.
Signed-off-by: Icenowy
h has all capabilities.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 10 +-
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 ++
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/binding
The Lichee Pi Zero Dock has an Ethernet port connected to the internal
PHY of the V3s SoC.
Enable it in the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s
于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
>> 写到:
>>>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>>>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
写到:
>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>> >
>> >
>> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo
>写到:
>> > >
于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to
>use
>> an out-of-band interrupt pin instead of SDIO in-band interrupt.
>>
>> Add the device tree binding
, then adds the interrupt to the device tree of
Orange Pi Zero.
Icenowy Zheng (1):
dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
Sergey Matyukevich (1):
ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero
.../bindings/net/wireless/allwinner,xr819.txt | 38
-by: Icenowy Zheng
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 +++
1 file changed, 3 insertions(+)
di
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
Acked-by: Rob
Some boards uses a PHY with internal delay with an Allwinner SoC.
Support these PHY modes in the driver.
As the driver has no configuration registers for these modes, just treat
them as ordinary RGMII.
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3
RGMII variants' support to the dwmac-sun8i driver.
The second patch renames some macros in RTL PHY driver, and the third
patch introduces the hack as the "RGMII-TXID" mode of the PHY.
The fourth patch enables the hack in the device tree.
Icenowy Zheng (4):
net: stmmac: dwmac-sun8i:
From: Icenowy Zheng
The page select register also exists on RTL8211E PHY (although it
behaves slightly differently).
Change the register macro name to remove the F.
Signed-off-by: Icenowy Zheng
---
drivers/net/phy/realtek.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions
From: Icenowy Zheng
Some RTL8211E chips have broken GbE function, which needs a hack to
fix. It's said that this fix will affect the performance on not-buggy
PHYs, so it should only be enabled on boards with the broken PHY.
Currently only some Pine64+ boards are known to have this issue.
Some Pine64+ boards have a broken RTL8211E PHY, which cannot work
reliably in 1000Base-T mode with default configuration.
A solution is passed to Pine64, which is said to be disabling the
internal RX delay of the PHY.
Enable the hack by set the PHY mode to RGMII-TXID.
Signed-off-by: Icenowy
于 2017年7月28日 GMT+08:00 下午5:44:51, Chen-Yu Tsai 写到:
>On Fri, Jul 28, 2017 at 5:28 PM, Corentin Labbe
> wrote:
>> This patch adds the sun8i-h3-ephy compatible to the internal PHY.
>>
>> Signed-off-by: Corentin Labbe
>> ---
>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 ++-
>
>To avoid repeating the p
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara 写到:
>Hi,
>
>On 27/06/17 10:41, Maxime Ripard wrote:
>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>> Hi,
>>>
>>> (CC:ing some people from that Rockchip dmwac series)
>>>
>>> On 27/06/17 09:21, Corentin Labbe wrote:
On Tu
于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai 写到:
>On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard
> wrote:
>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>> Hi,
>>>
>>> (CC:ing some people from that Rockchip dmwac series)
>>>
>>> On 27/06/17 09:21, Corentin Labbe wrote:
>>>
SoCs doesn't have extra xtal input for EPHY, and the
main xtal is 24MHz. The default value of H3 is set to 24MHz, but the V3s
default value is set to 25MHz).
First two patches are device tree binding patches, the third forces
the frequency to 24MHz and the fourth really add the V3s support.
Ic
Allwinner V3s SoC has a syscon like the one in H3.
Add its compatible string.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/misc/allwinner,syscon.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/misc/allwinner,syscon.txt
b
rly.
Force the EPHY clock frequency to 24MHz.
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
ind
-related register seems to have
changed from H3, but it seems to be a harmless change.
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers
Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but
have no external MII capability. That means that it can only use the
EPHY and cannot do Gbps transmission.
Add binding for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 10
hot-plugged in.
Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethe
于 2017年5月5日 GMT+08:00 上午2:21:29, Florian Fainelli 写到:
>On 05/04/2017 11:10 AM, icen...@aosc.io wrote:
>> 在 2017-04-22 08:22，Florian Fainelli 写道：
>>> On 04/21/2017 04:24 PM, Icenowy Zheng wrote:
>>>> From: Icenowy Zheng
>>>>
>>>> Some RTL82
From: Icenowy Zheng
Some Pine64+ boards are said to have broken RTL8211E PHY.
Enable the workaround in Pine64+ device tree file.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot
From: Icenowy Zheng
Some RTL8211E chips have broken GbE function, which needs a hack to
fix. It's said that this fix will affect the performance on not-buggy
PHYs, so it should only be enabled on boards with the broken PHY.
Currently only some Pine64+ boards are known to have this issue.
From: Icenowy Zheng
Some RTL8211E Ethernet PHY have an issue that needs a workaround
indicated with device tree.
Add the binding for a property that indicates this workaround.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/net/realtek,rtl8211e.txt | 22 ++
1
From: Icenowy Zheng
The page select register also exists on RTL8211E PHY (although it
behaves slightly differently).
Change the register macro name to remove the F.
Signed-off-by: Icenowy Zheng
---
drivers/net/phy/realtek.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions
the real driver part of this hack, which contains
some magic numbers from Pine64/Realtek.
The fourth patch is for reference only and should not be merged -- to
use it you will need sun8i-emac or dwmac-sun8i patchset applied.
Icenowy Zheng (4):
net: phy: realtek: change macro name for page selec
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