Re: [PATCH net-next] bpf: arm64: remove callee-save registers use for tmp registers

On 5/16/2016 4:45 PM, Z Lim wrote: Hi Yang, On Mon, May 16, 2016 at 4:09 PM, Yang Shi <yang@linaro.org> wrote: In the current implementation of ARM64 eBPF JIT, R23 and R24 are used for tmp registers, which are callee-saved registers. This leads to variable size of JIT prologue and ep

Re: [PATCH] arm64: bpf: jit JMP_JSET_{X,K}

20 PASS [3.212973] test_bpf: #250 JMP_JSET_X: if (0x3 & 0x) return 1 jited:1 89 PASS ... Fixes: e54bcde3d69d ("arm64: eBPF JIT compiler") Signed-off-by: Zi Shen Lim <zlim....@gmail.com> Acked-by: Yang Shi <yang@linaro.org> Thanks, Yang --- arch/arm64/net/b

Re: Warning triggered by lockdep checks for sock_owned_by_user on linux-next-20160420

On 4/22/2016 9:50 PM, Eric Dumazet wrote: On Fri, 2016-04-22 at 21:02 -0700, Shi, Yang wrote: Hi David, When I ran some test on a nfs mounted rootfs, I got the below warning with LOCKDEP enabled on linux-next-20160420: WARNING: CPU: 9 PID: 0 at include/net/sock.h:1408 udp_queue_rcv_skb+0x3d0

Warning triggered by lockdep checks for sock_owned_by_user on linux-next-20160420

Hi David, When I ran some test on a nfs mounted rootfs, I got the below warning with LOCKDEP enabled on linux-next-20160420: WARNING: CPU: 9 PID: 0 at include/net/sock.h:1408 udp_queue_rcv_skb+0x3d0/0x660 Modules linked in: CPU: 9 PID: 0 Comm: swapper/9 Tainted: G D

Re: [PATCH net-next 2/5] bpf: move clearing of A/X into classic to eBPF migration prologue

Holzheu <holz...@linux.vnet.ibm.com> Tested-by: Michael Holzheu <holz...@linux.vnet.ibm.com> Cc: Zi Shen Lim <zlim@gmail.com> Cc: Yang Shi <yang@linaro.org> Acked by me on the arm64 part. Acked-by: Yang Shi <yang@linaro.org> Thanks, Yang

Re: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction

On 11/30/2015 2:24 PM, Yang Shi wrote: aarch64 doesn't have native store immediate instruction, such operation has to be implemented by the below instruction sequence: Load immediate to register Store register Signed-off-by: Yang Shi <yang@linaro.org> CC: Zi Shen Lim <zlim@

Re: [PATCH 1/2] arm64: bpf: add 'store immediate' instruction

: On Thu, Nov 12, 2015 at 11:33 AM, Shi, Yang <yang@linaro.org> wrote: On 11/11/2015 4:39 AM, Will Deacon wrote: Wait a second, we're both talking rubbish here :) The STR (immediate) form is referring to the addressing mode, whereas this patch wants to store an immediate value to memory,

Re: [PATCH] arm64: bpf: fix buffer pointer

On 11/18/2015 1:41 PM, Z Lim wrote: On Wed, Nov 18, 2015 at 1:07 PM, Shi, Yang <yang@linaro.org> wrote: On 11/18/2015 12:56 AM, Zi Shen Lim wrote: emit_a64_mov_i64(r3, size, ctx); - emit(A64_ADD_I(1, r4, fp, MAX_BPF_STACK), ctx); +

Re: [PATCH] arm64: bpf: fix buffer pointer

On 11/18/2015 12:56 AM, Zi Shen Lim wrote: During code review, I noticed we were passing a bad buffer pointer to bpf_load_pointer helper function called by jitted code. Point to the buffer allocated by JIT, so we don't silently corrupt other parts of the stack. Signed-off-by: Zi Shen Lim

Re: [PATCH V3 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS

On 11/13/2015 6:39 PM, Z Lim wrote: Yang, I noticed another thing... On Fri, Nov 13, 2015 at 10:09 AM, Yang Shi <yang@linaro.org> wrote: Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JI

Re: [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS

On 11/16/2015 8:41 PM, Alexei Starovoitov wrote: On Mon, Nov 16, 2015 at 08:37:11PM -0800, Z Lim wrote: On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang@linaro.org> wrote: Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct

Re: [PATCH 2/2] arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS

On 11/12/2015 7:28 PM, Z Lim wrote: On Thu, Nov 12, 2015 at 1:57 PM, Yang Shi <yang@linaro.org> wrote: Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP in prologue in order to get the correct stack backtrace. However, ARM64 JIT used FP (x29) as eBPF fp regist

Re: [PATCH 1/2] arm64: bpf: add 'store immediate' instruction

On 11/11/2015 4:39 AM, Will Deacon wrote: On Wed, Nov 11, 2015 at 12:12:56PM +, Will Deacon wrote: On Tue, Nov 10, 2015 at 06:45:39PM -0800, Z Lim wrote: On Tue, Nov 10, 2015 at 2:41 PM, Yang Shi <yang@linaro.org> wrote: aarch64 doesn't have native store immediate instr

Re: [PATCH] arm64: bpf: fix JIT stack setup

On 11/9/2015 12:00 PM, Z Lim wrote: On Mon, Nov 9, 2015 at 10:08 AM, Shi, Yang <yang@linaro.org> wrote: I added it to stay align with ARMv8 AAPCS to maintain the correct FP during function call. It makes us get correct stack backtrace. I think we'd better to keep compliant with ARMv8

Re: [PATCH] arm64: bpf: fix JIT stack setup

tion call stack | | +-+ low Signed-off-by: Yang Shi <yang@linaro.org> CC: Zi Shen Lim <zlim@gmail.com> CC: Xi Wang <xi.w...@gmail.com> Thanks for tracking it down. That looks like fundamental bug in arm64

Re: [PATCH] arm64: bpf: fix JIT stack setup

all stack | | +-+ low Signed-off-by: Yang Shi <yang@linaro.org> CC: Zi Shen Lim <zlim@gmail.com> CC: Xi Wang <xi.w...@gmail.com> --- arch/arm64/net/bpf_jit_comp.c | 38 +++--- 1 file changed, 31 insertions(+), 7 dele

Re: [PATCH] bpf: convert hashtab lock to raw lock

On 10/31/2015 11:37 AM, Daniel Borkmann wrote: On 10/31/2015 02:47 PM, Steven Rostedt wrote: On Fri, 30 Oct 2015 17:03:58 -0700 Alexei Starovoitov wrote: On Fri, Oct 30, 2015 at 03:16:26PM -0700, Yang Shi wrote: When running bpf samples on rt kernel, it reports

Re: [PATCH] bpf: convert hashtab lock to raw lock

On 11/2/2015 12:59 AM, Thomas Gleixner wrote: On Sun, 1 Nov 2015, Alexei Starovoitov wrote: On Sat, Oct 31, 2015 at 09:47:36AM -0400, Steven Rostedt wrote: On Fri, 30 Oct 2015 17:03:58 -0700 Alexei Starovoitov wrote: On Fri, Oct 30, 2015 at 03:16:26PM -0700,

Re: [PATCH] bpf: convert hashtab lock to raw lock

On 11/2/2015 9:24 AM, Steven Rostedt wrote: On Mon, 02 Nov 2015 09:12:29 -0800 "Shi, Yang" <yang@linaro.org> wrote: Yes, it is common practice for converting sleepable spin lock to raw spin lock in -rt to avoid scheduling in atomic context bug. Note, in a lot of cas