Hi Dalon,
Just a few comments/questions.
On 11/14/18 6:50 PM, Dalon Westergreen wrote:
From: Dalon Westergreen
Add support for the mSGDMA prefetcher. The prefetcher adds support
for a linked list of descriptors in system memory. The prefetcher
feeds these to the mSGDMA dispatcher.
The
+ Rob Herring, Mark Rutland and the Device Tree mailing list.
On 11/14/18 6:50 PM, Dalon Westergreen wrote:
From: Dalon Westergreen
Update devicetree bindings documentation to include msgdma
prefetcher and ptp bindings.
Signed-off-by: Dalon Westergreen
---
size_t offs)
+{
+ void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+ writeb(val, paddr);
+}
#endif /* __ALTERA_UTILS_H__*/
Acked-by: Thor Thayer
{
@@ -1677,6 +1681,7 @@ static const struct altera_dmaops altera_dtype_msgdma = {
.init_dma = msgdma_initialize,
.uninit_dma = msgdma_uninitialize,
.start_rxdma = msgdma_start_rxdma,
+ .start_txdma = NULL,
};
static const struct of_device_id altera_tse_ids[] = {
Acked-by: Thor Thayer
)(struct altera_tse_private *priv);
+ void (*uninit_dma)(struct altera_tse_private *priv);
+ void (*start_rxdma)(struct altera_tse_private *priv);
};
/* This structure is private to each device.
Acked-by: Thor Thayer
x_ring_size = dma_tx_num;
ret = alloc_init_skbufs(priv);
if (ret) {
netdev_err(dev, "DMA descriptors initialization failed\n");
Acked-by: Thor Thayer
(ret)
+ goto out;
skb_tx_timestamp(skb);
Acked-by: Thor Thayer
From: Thor Thayer
Vince has moved to a different role. Replace him as Altera
TSE maintainer.
Signed-off-by: Thor Thayer
Acked-by: Vince Bridgers
Acked-by: Alan Tull
---
v2 Include netdev and David Miller
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Thor Thayer
Ping problems with packets > 8191 as shown:
PING 192.168.1.99 (192.168.1.99) 8150(8178) bytes of data.
8158 bytes from 192.168.1.99: icmp_seq=1 ttl=64 time=0.669 ms
wrong data byte 8144 should be 0xd0 but was 0x0
1610 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
Hi,
I'm running into a weird issue at the DMA boundary for large packets
(>8192) that I can't explain. I'm hoping someone here has an idea on
why I'm seeing this issue.
This is the Synopsys DesignWare Ethernet GMAC core (3.74) using the
stmmac driver found at
From: Thor Thayer <thor.tha...@linux.intel.com>
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
in the Linux kernel modified the register dump to store the DMA registers
at the DMA register offset (0x1000) but ethtool (stmmac.c) looks for the
DMA registe
From: Thor Thayer <thor.tha...@linux.intel.com>
This patch adds macros for the number of registers to
loop through to make the code easier to read.
Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
---
v2 New commit. Add macros for number of registers.
v3 Only add macros
From: Thor Thayer <thor.tha...@linux.intel.com>
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
Acked-by: Giuseppe Cavallaro <peppe.cavall...@st.com&
On 06/28/2017 10:13 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer <thor.tha...@linux.intel.com>
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
in the Linux kernel modified the register dump to store the DMA registers
at the DMA registe
From: Thor Thayer <thor.tha...@linux.intel.com>
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
Acked-by: Giuseppe Cavallaro <peppe.cavall...@st.com&
From: Thor Thayer <thor.tha...@linux.intel.com>
1. The DMA register dump structure changed which requires this
change to the indexing of the DMA registers.
2. Also dump the DMA HW Feature Register.
3. V2 also adds macros for the number of registers.
Thor Thayer (3):
ethtool: stmma
From: Thor Thayer <thor.tha...@linux.intel.com>
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
in the Linux kernel modified the register dump to store the DMA registers
at the DMA register offset (0x1000) but ethtool (stmmac.c) looks for the
DMA registe
From: Thor Thayer <thor.tha...@linux.intel.com>
This patch adds macros for the number of registers to
loop through to make the code easier to read.
Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
---
v2 New commit. Add macros for number of registers.
---
stmmac.c | 10 +
On 06/28/2017 04:03 AM, Giuseppe CAVALLARO wrote:
On 6/27/2017 11:51 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer <thor.tha...@linux.intel.com>
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Sign
From: Thor Thayer <thor.tha...@linux.intel.com>
Version 3.70a of the Designware has additional DMA registers so
add those to the ethtool DMA Register dump.
Offset 9 - Receive Interrupt Watchdog Timer Register
Offset 10 - AXI Bus Mode Register
Offset 11 - AHB or AXI Status Register
Offset 2
From: Thor Thayer <thor.tha...@linux.intel.com>
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
---
stmmac.c | 2 +-
1 file changed, 1 insertion(+)
From: Thor Thayer <thor.tha...@linux.intel.com>
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
modified the register dump to store the DMA registers at the DMA register
offset (0x1000) but ethtool (stmmac.c) looks for the DMA registers after
the MAC
From: Thor Thayer <thor.tha...@linux.intel.com>
The DMA register dump structure changed which requires this
change to the indexing of the DMA registers.
Also dump the DMA HW Feature Register.
Thor Thayer (2):
ethtool: stmmac: Fix Designware ethtool register dump
ethtool: stmmac: Add
From: Thor Thayer <thor.tha...@linux.intel.com>
Fix NETDEV WATCHDOG timeout on startup by adding missing register
writes that properly setup SGMII.
Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
---
drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c | 6 +-
1 fil
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