On Thu, Sep 15, 2016 at 01:58:15PM +0200, Richard Cochran wrote:
> Can the input clock be higher than 1 GHz? If not, I suggest using
> clocks_calc_mult_shift() with maxsec=4 and a setting the watchdog also
> to 4*HZ.
On second thought, with the new 12% timer batching, using 4*HZ for 32
bits of 1
On Wed, Sep 14, 2016 at 10:26:19PM +0200, Richard Cochran wrote:
> On Wed, Sep 14, 2016 at 04:02:29PM +0300, Grygorii Strashko wrote:
> > + clocks_calc_mult_shift(, , freq, NSEC_PER_SEC, maxsec);
> > +
> > + cpts->cc_mult = mult;
> > + cpts->cc.mult = mult;
>
> In order to get good
On 09/15/2016 12:03 AM, Richard Cochran wrote:
On Wed, Sep 14, 2016 at 11:47:46PM +0300, Grygorii Strashko wrote:
As I understand (and tested), clocks_calc_mult_shift() will
return max possible mult which can be used without overflow.
Yes, BUT the returned values depends on the @maxsec input.
On Wed, Sep 14, 2016 at 11:47:46PM +0300, Grygorii Strashko wrote:
> As I understand (and tested), clocks_calc_mult_shift() will
> return max possible mult which can be used without overflow.
Yes, BUT the returned values depends on the @maxsec input. As the
kerneldec says,
* Larger ranges may
On 09/14/2016 11:26 PM, Richard Cochran wrote:
> On Wed, Sep 14, 2016 at 04:02:29PM +0300, Grygorii Strashko wrote:
>> +static void cpts_calc_mult_shift(struct cpts *cpts)
>> +{
>> +u64 maxsec;
>> +u32 freq;
>> +u32 mult;
>> +u32 shift;
>> +u64 ns;
>> +u64 frac;
>> +
>> +
On Wed, Sep 14, 2016 at 04:02:29PM +0300, Grygorii Strashko wrote:
> +static void cpts_calc_mult_shift(struct cpts *cpts)
> +{
> + u64 maxsec;
> + u32 freq;
> + u32 mult;
> + u32 shift;
> + u64 ns;
> + u64 frac;
> +
> + if (cpts->cc_mult || cpts->cc.shift)
> +
On 09/14/2016 05:22 PM, Richard Cochran wrote:
On Wed, Sep 14, 2016 at 04:02:29PM +0300, Grygorii Strashko wrote:
@@ -35,6 +33,8 @@ Optional properties:
For example in dra72x-evm, pcf gpio has to be
driven low so that cpsw slave 0 and phy data
On Wed, Sep 14, 2016 at 04:02:29PM +0300, Grygorii Strashko wrote:
> @@ -35,6 +33,8 @@ Optional properties:
> For example in dra72x-evm, pcf gpio has to be
> driven low so that cpsw slave 0 and phy data
> lines are connected
The cyclecounter mult and shift values can be calculated based on the
CPTS rftclk frequency and timekeepnig framework provides required algos
and API's.
Hence, calc mult and shift basing on CPTS rftclk frequency if both
cpts_clock_shift and cpts_clock_mult properties are not provided in DT
(the
