From: Iyappan Subramanian
Date: Mon, 26 Oct 2015 15:25:14 -0700
> X-Gene RGMII ethernet controller has a RGMII bridge that performs the
> task of converting the RGMII signal {RX_CLK,RX_CTL, RX_DATA[3:0]} from
> PHY to GMII signal {RX_DV,RX_ER,RX_DATA[7:0]} and vice versa.
X-Gene RGMII ethernet controller has a RGMII bridge that performs the
task of converting the RGMII signal {RX_CLK,RX_CTL, RX_DATA[3:0]} from
PHY to GMII signal {RX_DV,RX_ER,RX_DATA[7:0]} and vice versa. This
RGMII bridge has a provision to internally delay the input RX_CLK and
the output TX_CLK