Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On Sat, Mar 17, 2018 at 02:30:10PM -0400, Sinan Kaya wrote: > Somebody also has to take a task and work very hard to get rid of > __raw_writeX() > APIs in drivers/net directory. It looked like a very common practice though > it clearly violates multiarch portability concerns Jason and Deve

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

+linuxppc-...@lists.ozlabs.org On 3/17/2018 11:05 AM, Jason Gunthorpe wrote: > On Sat, Mar 17, 2018 at 12:25:14AM -0400, Sinan Kaya wrote: >> On 3/17/2018 12:03 AM, Sinan Kaya wrote: >>> On 3/16/2018 11:40 PM, Sinan Kaya wrote: I'll change writel_relaxed() with __raw_writel() in the series

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On Sat, Mar 17, 2018 at 12:25:14AM -0400, Sinan Kaya wrote: > On 3/17/2018 12:03 AM, Sinan Kaya wrote: > > On 3/16/2018 11:40 PM, Sinan Kaya wrote: > >> I'll change writel_relaxed() with __raw_writel() in the series like you > >> suggested > >> and also look at your other comments. > > > > I

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

From: Sinan Kaya Date: Sat, 17 Mar 2018 00:25:14 -0400 > I think I finally got what you mean. > > Code seems to have > > wmb() > writel()/writeq() > wmb() > > this can be safely replaced with > > wmb() > __raw_writel()/__raw_writeq() > wmb() > > This will work on all

RE: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

> > On 3/17/2018 12:03 AM, Sinan Kaya wrote: > > On 3/16/2018 11:40 PM, Sinan Kaya wrote: > >> I'll change writel_relaxed() with __raw_writel() in the series like you > suggested > >> and also look at your other comments. > > > > I spoke too soon. > > > > Now that I realized, code needs to follow

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On Fri, Mar 16, 2018 at 11:25 PM, Sinan Kaya wrote: > @@ -477,15 +477,16 @@ static inline void t4_ring_sq_db(struct t4_wq *wq, u16 > inc, union t4_wr *wqe) > (u64 *)wqe); > } else { > pr_debug("DB

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On 3/17/2018 12:03 AM, Sinan Kaya wrote: > On 3/16/2018 11:40 PM, Sinan Kaya wrote: >> I'll change writel_relaxed() with __raw_writel() in the series like you >> suggested >> and also look at your other comments. > > I spoke too soon. > > Now that I realized, code needs to follow one of the

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On 3/16/18 6:04 PM, Steve Wise wrote: Anybody understand why the PPC implementation of writeX_relaxed() isn't relaxed? You probably should ask that on the linuxppc-...@lists.ozlabs.org mailing list. I've always wondered why PowerPC has non-standard I/O accessors. -- Qualcomm Datacenter

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On 3/16/2018 11:40 PM, Sinan Kaya wrote: > I'll change writel_relaxed() with __raw_writel() in the series like you > suggested > and also look at your other comments. I spoke too soon. Now that I realized, code needs to follow one of the following patterns for correctness 1) wmb()

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On 3/16/2018 7:05 PM, Steve Wise wrote: >> >> On 3/16/2018 5:05 PM, Steve Wise wrote: Code includes wmb() followed by writel(). writel() already has a barrier >>> on some architectures like arm64. This ends up CPU observing two barriers back to back before executing >> the

RE: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

> > On 3/16/2018 5:05 PM, Steve Wise wrote: > >> Code includes wmb() followed by writel(). writel() already has a barrier > > on > >> some architectures like arm64. > >> > >> This ends up CPU observing two barriers back to back before executing > the > >> register write. > >> > >> Since code

RE: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

> > On Fri, Mar 16, 2018 at 04:05:10PM -0500, Steve Wise wrote: > > > Code includes wmb() followed by writel(). writel() already has a barrier > > on > > > some architectures like arm64. > > > > > > This ends up CPU observing two barriers back to back before executing > the > > > register write.

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On Fri, Mar 16, 2018 at 04:05:10PM -0500, Steve Wise wrote: > > Code includes wmb() followed by writel(). writel() already has a barrier > on > > some architectures like arm64. > > > > This ends up CPU observing two barriers back to back before executing the > > register write. > > > > Since

Re: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

On 3/16/2018 5:05 PM, Steve Wise wrote: >> Code includes wmb() followed by writel(). writel() already has a barrier > on >> some architectures like arm64. >> >> This ends up CPU observing two barriers back to back before executing the >> register write. >> >> Since code already has an explicit

RE: [PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

> Code includes wmb() followed by writel(). writel() already has a barrier on > some architectures like arm64. > > This ends up CPU observing two barriers back to back before executing the > register write. > > Since code already has an explicit barrier call, changing writel() to >

[PATCH v3 18/18] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed().