subject:"\[PATCH v6 29\/36\] nds32\: Build infrastructure"

Re: [PATCH v6 29/36] nds32: Build infrastructure

2018-01-22 Thread Greentime Hu

Hi, Arnd:

2018-01-22 23:38 GMT+08:00 Arnd Bergmann :
> On Mon, Jan 22, 2018 at 4:20 PM, Greentime Hu  wrote:
> BE
>>>
>>> I think it's better to drop GENERIC_IRQ_PROBE here, no modern driver
>>> should rely on that.
>>
>> I will drop it.
>>
 +choice
 +   prompt "CPU type"
 +   default CPU_V3
 +config CPU_N15
 +   bool "AndesCore N15"
 +config CPU_N13
 +   bool "AndesCore N13"
 +   select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
 +config CPU_N10
 +   bool "AndesCore N10"
 +   select CPU_CACHE_ALIASING
 +config CPU_D15
 +   bool "AndesCore D15"
 +config CPU_D10
 +   bool "AndesCore D10"
 +   select CPU_CACHE_ALIASING
 +config CPU_V3
 +   bool "AndesCore v3 compatible"
 +   select ANDES_PAGE_SIZE_8KB
 +endchoice
>>>
>>> I forget what we discussed here earlier, but at the very least, there 
>>> should be
>>> some help text here to explain what the implications are. I assume that you
>>> generally want to be able to build one kernel to run on all of the above, 
>>> right?
>>>
>>> Will selecting 'CPU_V3' result in a kernel binary that can run on all of 
>>> them?
>>> If so, please explain it here as that is not obvious.
>>>
>>> For the other CPU types, can you list the what backwards-compatiblity
>>> you get? E.g. will a kernel built for N13 run on any of N15, D15 or N10?
>>>
>> Yes, we would like to build a kernel with CPU_V3 to run on all of the above.
>>
>> Not sure if these help texts clear enough?
>>
>> choice
>> prompt "CPU type"
>> default CPU_V3
>> help
>>   The data cache of N15/D15 is implemented as PIPT and it will
>> not cause the
>>   cache aliasing issue. The rest cpus(N13, N10 and D10) are
>> implemented as
>>   VIPT data cache. It may cause the cache aliasing issue if
>> its cache way
>>   size is larger than page size. You can specify the the CPU
>> type direcly or
>>   choose CPU_V3 if unsure.
>>
>>   A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
>>   A kernel built for N15 is able to run on N15 or D15.
>>   A kernel built for D10 is able to run on D10 or D15.
>>   A kernel built for D15 is able to run on D15.
>>   A kernel built for N13 with CPU_CACHE_ALIASING is able to
>> run on N15, D15, N13, N10 or D10
>>   A kernel built for N13 without CPU_CACHE_ALIASING is able to
>> run on N15, N13 or D15
>>
>> config CPU_N15
>> bool "AndesCore N15"
>> config CPU_N13
>> bool "AndesCore N13"
>> select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
>> config CPU_N10
>> bool "AndesCore N10"
>> select CPU_CACHE_ALIASING
>> config CPU_D15
>> bool "AndesCore D15"
>> config CPU_D10
>> bool "AndesCore D10"
>> select CPU_CACHE_ALIASING
>> config CPU_V3
>> bool "AndesCore v3 compatible"
>> select CPU_CACHE_ALIASING
>> endchoice
>
> I would drop the description about CPU_CACHE_ALIASING in the list
> of compatibilities text and simply say 'A kernel built for N13 is able to run
> on N15, N13 or D15', it's more logical that way, and it gives you the freedom
> to later change the rules about whether it can or cannot run.
>
> Maybe also change the initial prompt from "CPU type" to "minimum CPU type".
>

Thank you for your suggestion.
I will update it like this.

choice
prompt "minimum CPU type"
default CPU_V3
help
  The data cache of N15/D15 is implemented as PIPT and it will not cause
  the cache aliasing issue. The rest cpus(N13, N10 and D10) are
  implemented as VIPT data cache. It may cause the cache aliasing issue
  if its cache way size is larger than page size. You can specify the
  CPU type direcly or choose CPU_V3 if unsure.

  A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
  A kernel built for N15 is able to run on N15 or D15.
  A kernel built for D10 is able to run on D10 or D15.
  A kernel built for D15 is able to run on D15.
  A kernel built for N13 is able to run on N15, N13 or D15.

config CPU_N15
bool "AndesCore N15"
config CPU_N13
bool "AndesCore N13"
select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
config CPU_N10
bool "AndesCore N10"
select CPU_CACHE_ALIASING
config CPU_D15
bool "AndesCore D15"
config CPU_D10
bool "AndesCore D10"
select CPU_CACHE_ALIASING
config CPU_V3
bool "AndesCore v3 compatible"
select CPU_CACHE_ALIASING
endchoice

Re: [PATCH v6 29/36] nds32: Build infrastructure

2018-01-22 Thread Arnd Bergmann

On Mon, Jan 22, 2018 at 4:20 PM, Greentime Hu  wrote:
BE
>>
>> I think it's better to drop GENERIC_IRQ_PROBE here, no modern driver
>> should rely on that.
>
> I will drop it.
>
>>> +choice
>>> +   prompt "CPU type"
>>> +   default CPU_V3
>>> +config CPU_N15
>>> +   bool "AndesCore N15"
>>> +config CPU_N13
>>> +   bool "AndesCore N13"
>>> +   select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
>>> +config CPU_N10
>>> +   bool "AndesCore N10"
>>> +   select CPU_CACHE_ALIASING
>>> +config CPU_D15
>>> +   bool "AndesCore D15"
>>> +config CPU_D10
>>> +   bool "AndesCore D10"
>>> +   select CPU_CACHE_ALIASING
>>> +config CPU_V3
>>> +   bool "AndesCore v3 compatible"
>>> +   select ANDES_PAGE_SIZE_8KB
>>> +endchoice
>>
>> I forget what we discussed here earlier, but at the very least, there should 
>> be
>> some help text here to explain what the implications are. I assume that you
>> generally want to be able to build one kernel to run on all of the above, 
>> right?
>>
>> Will selecting 'CPU_V3' result in a kernel binary that can run on all of 
>> them?
>> If so, please explain it here as that is not obvious.
>>
>> For the other CPU types, can you list the what backwards-compatiblity
>> you get? E.g. will a kernel built for N13 run on any of N15, D15 or N10?
>>
> Yes, we would like to build a kernel with CPU_V3 to run on all of the above.
>
> Not sure if these help texts clear enough?
>
> choice
> prompt "CPU type"
> default CPU_V3
> help
>   The data cache of N15/D15 is implemented as PIPT and it will
> not cause the
>   cache aliasing issue. The rest cpus(N13, N10 and D10) are
> implemented as
>   VIPT data cache. It may cause the cache aliasing issue if
> its cache way
>   size is larger than page size. You can specify the the CPU
> type direcly or
>   choose CPU_V3 if unsure.
>
>   A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
>   A kernel built for N15 is able to run on N15 or D15.
>   A kernel built for D10 is able to run on D10 or D15.
>   A kernel built for D15 is able to run on D15.
>   A kernel built for N13 with CPU_CACHE_ALIASING is able to
> run on N15, D15, N13, N10 or D10
>   A kernel built for N13 without CPU_CACHE_ALIASING is able to
> run on N15, N13 or D15
>
> config CPU_N15
> bool "AndesCore N15"
> config CPU_N13
> bool "AndesCore N13"
> select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
> config CPU_N10
> bool "AndesCore N10"
> select CPU_CACHE_ALIASING
> config CPU_D15
> bool "AndesCore D15"
> config CPU_D10
> bool "AndesCore D10"
> select CPU_CACHE_ALIASING
> config CPU_V3
> bool "AndesCore v3 compatible"
> select CPU_CACHE_ALIASING
> endchoice

I would drop the description about CPU_CACHE_ALIASING in the list
of compatibilities text and simply say 'A kernel built for N13 is able to run
on N15, N13 or D15', it's more logical that way, and it gives you the freedom
to later change the rules about whether it can or cannot run.

Maybe also change the initial prompt from "CPU type" to "minimum CPU type".

>> I think the 'select ANDES_PAGE_SIZE_8KB' cannot work as expected,
>> since ANDES_PAGE_SIZE_8KB is inside of a 'choice' statement. Since
>> there are only two options (4K and 8K), you can address that by making
>> it a simple bool option and fall back to 4K when ANDES_PAGE_SIZE_8KB
>> is disabled.
>
> After reviewing this config, it seems to make much more sense if we
> select CPU_CACHE_ALIASING.
> A kernel with aliasing cache handling should be able to run on
> aliasing/non-aliasing CPU.
>
> config CPU_V3
> bool "AndesCore v3 compatible"
> select CPU_CACHE_ALIASING

Sure, that's a possible way out.

Arnd

Re: [PATCH v6 29/36] nds32: Build infrastructure

2018-01-22 Thread Greentime Hu

Hi, Arnd:

2018-01-18 19:00 GMT+08:00 Arnd Bergmann :
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu  wrote:
>> From: Greentime Hu 
>>
>> This patch adds Makefile, Kconfig and vmlinux.lds.S files required for 
>> building
>> an nds32 kernel.
>>
>> Signed-off-by: Vincent Chen 
>> Signed-off-by: Greentime Hu 
>
> I find some new details every time I look here ;-)

Thank you for revewing so detailedly. :)

>> @@ -0,0 +1,107 @@
>> +#
>> +# For a description of the syntax of this configuration file,
>> +# see Documentation/kbuild/kconfig-language.txt.
>> +#
>> +
>> +config NDS32
>> +def_bool y
>> +   select ARCH_HAS_RAW_COPY_USER
>
> I don't think this symbol was ever merged. Do you remember why you added it?

I will drop it. It must be added in earlier kernel version.

>> +   select ARCH_WANT_FRAME_POINTERS if FTRACE
>> +   select ARCH_WANT_IPC_PARSE_VERSION
>
> You most certainly don't want IPC_PARSE_VERSION, please drop this
> and adapt your glibc.

ok. I will drop it.

>> +   select CLKSRC_MMIO
>> +   select CLONE_BACKWARDS
>> +   select COMMON_CLK
>> +   select FRAME_POINTER
>
> Do you need both ARCH_WANT_FRAME_POINTERS and FRAME_POINTER here?

I will drop FRAME_POINTER.

>> +   select GENERIC_ATOMIC64
>> +   select GENERIC_CPU_DEVICES
>> +   select GENERIC_CLOCKEVENTS
>> +   select GENERIC_IRQ_CHIP
>> +   select GENERIC_IRQ_PROBE
>
> I think it's better to drop GENERIC_IRQ_PROBE here, no modern driver
> should rely on that.

I will drop it.

>> +choice
>> +   prompt "CPU type"
>> +   default CPU_V3
>> +config CPU_N15
>> +   bool "AndesCore N15"
>> +config CPU_N13
>> +   bool "AndesCore N13"
>> +   select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
>> +config CPU_N10
>> +   bool "AndesCore N10"
>> +   select CPU_CACHE_ALIASING
>> +config CPU_D15
>> +   bool "AndesCore D15"
>> +config CPU_D10
>> +   bool "AndesCore D10"
>> +   select CPU_CACHE_ALIASING
>> +config CPU_V3
>> +   bool "AndesCore v3 compatible"
>> +   select ANDES_PAGE_SIZE_8KB
>> +endchoice
>
> I forget what we discussed here earlier, but at the very least, there should 
> be
> some help text here to explain what the implications are. I assume that you
> generally want to be able to build one kernel to run on all of the above, 
> right?
>
> Will selecting 'CPU_V3' result in a kernel binary that can run on all of them?
> If so, please explain it here as that is not obvious.
>
> For the other CPU types, can you list the what backwards-compatiblity
> you get? E.g. will a kernel built for N13 run on any of N15, D15 or N10?
>
Yes, we would like to build a kernel with CPU_V3 to run on all of the above.

Not sure if these help texts clear enough?

choice
prompt "CPU type"
default CPU_V3
help
  The data cache of N15/D15 is implemented as PIPT and it will
not cause the
  cache aliasing issue. The rest cpus(N13, N10 and D10) are
implemented as
  VIPT data cache. It may cause the cache aliasing issue if
its cache way
  size is larger than page size. You can specify the the CPU
type direcly or
  choose CPU_V3 if unsure.

  A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
  A kernel built for N15 is able to run on N15 or D15.
  A kernel built for D10 is able to run on D10 or D15.
  A kernel built for D15 is able to run on D15.
  A kernel built for N13 with CPU_CACHE_ALIASING is able to
run on N15, D15, N13, N10 or D10
  A kernel built for N13 without CPU_CACHE_ALIASING is able to
run on N15, N13 or D15

config CPU_N15
bool "AndesCore N15"
config CPU_N13
bool "AndesCore N13"
select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
config CPU_N10
bool "AndesCore N10"
select CPU_CACHE_ALIASING
config CPU_D15
bool "AndesCore D15"
config CPU_D10
bool "AndesCore D10"
select CPU_CACHE_ALIASING
config CPU_V3
bool "AndesCore v3 compatible"
select CPU_CACHE_ALIASING
endchoice

> I think the 'select ANDES_PAGE_SIZE_8KB' cannot work as expected,
> since ANDES_PAGE_SIZE_8KB is inside of a 'choice' statement. Since
> there are only two options (4K and 8K), you can address that by making
> it a simple bool option and fall back to 4K when ANDES_PAGE_SIZE_8KB
> is disabled.

After reviewing this config, it seems to make much more sense if we
select CPU_CACHE_ALIASING.
A kernel with aliasing cache handling should be able to run on
aliasing/non-aliasing CPU.

config CPU_V3
bool "AndesCore v3 compatible"
select CPU_CACHE_ALIASING

>> +config CACHE_L2
>> +   bool "Support L2 cache"
>> +default y
>> +   help
>> + Say Y here to enable L2 cache if your SoC are integrated with L2CC.
>> + If unsure, say N.
>> +
>> +menu

Re: [PATCH v6 29/36] nds32: Build infrastructure

2018-01-18 Thread Arnd Bergmann

On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu  wrote:
> From: Greentime Hu 
>
> This patch adds Makefile, Kconfig and vmlinux.lds.S files required for 
> building
> an nds32 kernel.
>
> Signed-off-by: Vincent Chen 
> Signed-off-by: Greentime Hu 

I find some new details every time I look here ;-)

> @@ -0,0 +1,107 @@
> +#
> +# For a description of the syntax of this configuration file,
> +# see Documentation/kbuild/kconfig-language.txt.
> +#
> +
> +config NDS32
> +def_bool y
> +   select ARCH_HAS_RAW_COPY_USER

I don't think this symbol was ever merged. Do you remember why you added it?

> +   select ARCH_WANT_FRAME_POINTERS if FTRACE
> +   select ARCH_WANT_IPC_PARSE_VERSION

You most certainly don't want IPC_PARSE_VERSION, please drop this
and adapt your glibc.

> +   select CLKSRC_MMIO
> +   select CLONE_BACKWARDS
> +   select COMMON_CLK
> +   select FRAME_POINTER

Do you need both ARCH_WANT_FRAME_POINTERS and FRAME_POINTER here?

> +   select GENERIC_ATOMIC64
> +   select GENERIC_CPU_DEVICES
> +   select GENERIC_CLOCKEVENTS
> +   select GENERIC_IRQ_CHIP
> +   select GENERIC_IRQ_PROBE

I think it's better to drop GENERIC_IRQ_PROBE here, no modern driver
should rely on that.

> +choice
> +   prompt "CPU type"
> +   default CPU_V3
> +config CPU_N15
> +   bool "AndesCore N15"
> +config CPU_N13
> +   bool "AndesCore N13"
> +   select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
> +config CPU_N10
> +   bool "AndesCore N10"
> +   select CPU_CACHE_ALIASING
> +config CPU_D15
> +   bool "AndesCore D15"
> +config CPU_D10
> +   bool "AndesCore D10"
> +   select CPU_CACHE_ALIASING
> +config CPU_V3
> +   bool "AndesCore v3 compatible"
> +   select ANDES_PAGE_SIZE_8KB
> +endchoice

I forget what we discussed here earlier, but at the very least, there should be
some help text here to explain what the implications are. I assume that you
generally want to be able to build one kernel to run on all of the above, right?

Will selecting 'CPU_V3' result in a kernel binary that can run on all of them?
If so, please explain it here as that is not obvious.

For the other CPU types, can you list the what backwards-compatiblity
you get? E.g. will a kernel built for N13 run on any of N15, D15 or N10?

I think the 'select ANDES_PAGE_SIZE_8KB' cannot work as expected,
since ANDES_PAGE_SIZE_8KB is inside of a 'choice' statement. Since
there are only two options (4K and 8K), you can address that by making
it a simple bool option and fall back to 4K when ANDES_PAGE_SIZE_8KB
is disabled.

> +config CACHE_L2
> +   bool "Support L2 cache"
> +default y
> +   help
> + Say Y here to enable L2 cache if your SoC are integrated with L2CC.
> + If unsure, say N.
> +
> +menu "Memory configuration"
> +
> +choice
> +   prompt "Memory split"
> +   depends on MMU
> +   default VMSPLIT_3G

Why not default to VMSPLIT_3G_OPT?

Arnd

[PATCH v6 29/36] nds32: Build infrastructure

2018-01-14 Thread Greentime Hu

From: Greentime Hu 

This patch adds Makefile, Kconfig and vmlinux.lds.S files required for building
an nds32 kernel.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/Kconfig |  107 
 arch/nds32/Kconfig.cpu |  161 
 arch/nds32/Makefile|   66 +++
 arch/nds32/boot/Makefile   |   15 
 arch/nds32/include/asm/Kbuild  |   54 
 arch/nds32/include/uapi/asm/Kbuild |   28 +++
 arch/nds32/kernel/Makefile |   23 ++
 arch/nds32/kernel/vmlinux.lds.S|   57 +
 arch/nds32/mm/Makefile |7 ++
 9 files changed, 518 insertions(+)
 create mode 100644 arch/nds32/Kconfig
 create mode 100644 arch/nds32/Kconfig.cpu
 create mode 100644 arch/nds32/Makefile
 create mode 100644 arch/nds32/boot/Makefile
 create mode 100644 arch/nds32/include/asm/Kbuild
 create mode 100644 arch/nds32/include/uapi/asm/Kbuild
 create mode 100644 arch/nds32/kernel/Makefile
 create mode 100644 arch/nds32/kernel/vmlinux.lds.S
 create mode 100644 arch/nds32/mm/Makefile

diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
new file mode 100644
index 000..56e1be1
--- /dev/null
+++ b/arch/nds32/Kconfig
@@ -0,0 +1,107 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config NDS32
+def_bool y
+   select ARCH_HAS_RAW_COPY_USER
+   select ARCH_WANT_FRAME_POINTERS if FTRACE
+   select ARCH_WANT_IPC_PARSE_VERSION
+   select CLKSRC_MMIO
+   select CLONE_BACKWARDS
+   select COMMON_CLK
+   select FRAME_POINTER
+   select GENERIC_ATOMIC64
+   select GENERIC_CPU_DEVICES
+   select GENERIC_CLOCKEVENTS
+   select GENERIC_IRQ_CHIP
+   select GENERIC_IRQ_PROBE
+   select GENERIC_IRQ_SHOW
+   select GENERIC_STRNCPY_FROM_USER
+   select GENERIC_STRNLEN_USER
+   select GENERIC_TIME_VSYSCALL
+   select HANDLE_DOMAIN_IRQ
+   select HAVE_ARCH_TRACEHOOK
+   select HAVE_DEBUG_KMEMLEAK
+   select HAVE_MEMBLOCK
+   select HAVE_REGS_AND_STACK_ACCESS_API
+   select IRQ_DOMAIN
+   select LOCKDEP_SUPPORT
+   select MODULES_USE_ELF_RELA
+   select OF
+   select OF_EARLY_FLATTREE
+   select NO_BOOTMEM
+   select NO_IOPORT_MAP
+   select RTC_LIB
+   select THREAD_INFO_IN_TASK
+   help
+ Andes(nds32) Linux support.
+
+config GENERIC_CALIBRATE_DELAY
+   def_bool n
+
+config GENERIC_CSUM
+def_bool y
+
+config GENERIC_HWEIGHT
+def_bool y
+
+config GENERIC_LOCKBREAK
+def_bool y
+   depends on PREEMPT
+
+config RWSEM_GENERIC_SPINLOCK
+   def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
+   def_bool y
+
+config STACKTRACE_SUPPORT
+def_bool y
+
+config FIX_EARLYCON_MEM
+   def_bool y
+
+config PGTABLE_LEVELS
+   default 2
+
+source "init/Kconfig"
+
+menu "System Type"
+source "arch/nds32/Kconfig.cpu"
+config NR_CPUS
+   int
+   default 1
+
+config MMU
+def_bool y
+
+config NDS32_BUILTIN_DTB
+string "Builtin DTB"
+default ""
+   help
+ User can use it to specify the dts of the SoC
+endmenu
+
+menu "Kernel Features"
+source "kernel/Kconfig.preempt"
+source "mm/Kconfig"
+source "kernel/Kconfig.hz"
+endmenu
+
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+endmenu
+
+source "net/Kconfig"
+source "drivers/Kconfig"
+source "fs/Kconfig"
+
+menu "Kernel hacking"
+source "lib/Kconfig.debug"
+endmenu
+
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
new file mode 100644
index 000..43e2f3f
--- /dev/null
+++ b/arch/nds32/Kconfig.cpu
@@ -0,0 +1,161 @@
+comment "Processor Features"
+
+config CPU_BIG_ENDIAN
+   bool "Big endian"
+
+config CPU_LITTLE_ENDIAN
+def_bool !CPU_BIG_ENDIAN
+
+config HWZOL
+   bool "hardware zero overhead loop support"
+   depends on CPU_D10 || CPU_D15
+   default n
+   help
+ A set of Zero-Overhead Loop mechanism is provided to reduce the
+ instruction fetch and execution overhead of loop-control instructions.
+ It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
+ You don't need to save these registers if you can make sure your user
+ program doesn't use these registers.
+
+ If unsure, say N.
+
+config CPU_CACHE_ALIASING
+   bool "Aliasing cache"
+   depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
+   default y
+   help
+ If this CPU is using VIPT data cache and its cache way size is larger
+ than page size, say Y. If it is using PIPT data cache, say N.
+
+ If unsure, say Y.
+
+choice
+   prompt "CPU type"
+   default CPU_V3
+config CPU_N15
+

Re: [PATCH v6 29/36] nds32: Build infrastructure

Re: [PATCH v6 29/36] nds32: Build infrastructure

Re: [PATCH v6 29/36] nds32: Build infrastructure

Re: [PATCH v6 29/36] nds32: Build infrastructure

[PATCH v6 29/36] nds32: Build infrastructure

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