Re: [PATCH v6 32/36] dt-bindings: nds32 L2 cache controller Bindings

[Arnd Bergmann]

On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu  wrote:
> From: Greentime Hu 
>
> This patch adds nds32 L2 cache controller binding documents.
>
> Signed-off-by: Greentime Hu 
> Reviewed-by: Rob Herring 

Acked-by: Arnd Bergmann 

[PATCH v6 32/36] dt-bindings: nds32 L2 cache controller Bindings

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 L2 cache controller binding documents.

Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/nds32/atl2c.txt |   29 +
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt

diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt 
b/Documentation/devicetree/bindings/nds32/atl2c.txt
new file mode 100644
index 000..6b34e04
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
@@ -0,0 +1,29 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: "andestech,atl2c"
+   - reg : Physical base address and size of cache controller's memory 
mapped
+   - cache-unified : Specifies the cache is a unified cache.
+   - cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+   cache-controller@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
-- 
1.7.9.5