Re: [patch net 2/2] mlxsw: pci: Correctly determine if descriptor queue is full

2016-03-07 Thread Ido Schimmel
Mon, Mar 07, 2016 at 04:04:59PM IST, sergei.shtyl...@cogentembedded.com wrote: >Hello. > >On 3/7/2016 11:24 AM, Jiri Pirko wrote: > >> From: Ido Schimmel >> >> The descriptor queues for sending (SDQs) and receiving (RDQs) packets >> are managed by two counters - producer and

Re: [patch net 2/2] mlxsw: pci: Correctly determine if descriptor queue is full

2016-03-07 Thread Sergei Shtylyov
Hello. On 3/7/2016 11:24 AM, Jiri Pirko wrote: From: Ido Schimmel The descriptor queues for sending (SDQs) and receiving (RDQs) packets are managed by two counters - producer and consumer - which are both 16-bit in size. A queue is considered full when the difference

[patch net 2/2] mlxsw: pci: Correctly determine if descriptor queue is full

2016-03-07 Thread Jiri Pirko
From: Ido Schimmel The descriptor queues for sending (SDQs) and receiving (RDQs) packets are managed by two counters - producer and consumer - which are both 16-bit in size. A queue is considered full when the difference between the two equals the queue's maximum number of