: cca8b1337541 (net: dsa: Use mnemonics rather than register numbers)
Acked-by: Andrew Lunn and...@lunn.ch
Thanks
Andrew
---
drivers/net/dsa/mv88e6xxx.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c
index
On Mon, Apr 20, 2015 at 05:43:26PM -0400, Vivien Didelot wrote:
Minor, use the explicit PORT_DEFAULT_VLAN define instead of 0x07.
Hi Vivien
I would not normally use the word Minor here, since it will end up
in the commit log.
Other than that:
Acked-by: Andrew Lunn and...@lunn.ch
Thanks
I would however say that sysfs is the wrong API. The linux network
stack uses netlink for most configuration activities. So i would
suggest adding a netlink binding to DSA, and place the code in
net/dsa/, not within an MDIO driver.
I suppose we could do that, but that sounds like a
My goal in reworking this weird DSA device/driver model is that you
could just register your switch devices as an enhanced
phy_driver/spi_driver/pci_driver etc..., such that libphy-ready drivers
could just take advantage of that when they scan/detect their MDIO buses
and find a switch. We are
Hi Jan
Interesting work, but i think the architecture is wrong.
DSA needs an Ethernet device, an MDIO bus, and information about ports
on the switch. The MDIO bus and the Ethernet need no knowledge of
DSA. So putting your DSA configuration code in the MDIO driver is
wrong.
The problem you have
On Wed, Apr 22, 2015 at 04:14:33PM +, Jan Kaisrlik wrote:
2015-04-21 17:51 GMT+00:00 Florian Fainelli f.faine...@gmail.com:
On 21/04/15 10:39, Andrew Lunn wrote:
I would however say that sysfs is the wrong API. The linux network
stack uses netlink for most configuration activities. So i
On Wed, Apr 29, 2015 at 06:57:39PM -0700, Florian Fainelli wrote:
Some Ethernet MAC drivers using the PHY library require the hardcoding
of link parameters when interfaced to a switch device. This has
typically lead to various ad-hoc implementations looking like this:
- using a fixed PHY
On Wed, Apr 29, 2015 at 10:56:15AM -0700, Guenter Roeck wrote:
eeprom-length is a switch property, not a dsa property, and thus
needs to be attached to the switch node, not to the dsa node.
Reported-by: Andrew Lunn and...@lunn.ch
Fixes: 6793abb4e849 (net: dsa: Add support for switch EEPROM
there is no compiler warning, possibly used
before set.
Reviewed-by: Andrew Lunn and...@lunn.ch
Thanks
Andrew
---
drivers/net/dsa/mv88e6xxx.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c
index
On Tue, Jun 02, 2015 at 07:31:56PM -0700, Chris Healy wrote:
Guenter,
That's a very valid concern. I have a configuration with a 6352 controlled
by a low end ARM core with a 100mbps connection on the CPU port. This
switch needs to support passing multicast streams that are more than
On Tue, Jun 09, 2015 at 11:54:50AM -0700, Florian Fainelli wrote:
Hi,
I am observing a strange problem on net-next (not observed with net,
bisection in progress) where the initial DHCP configuration using
busybox's udhcpc is able to configure the local interface address and
DNS serer, but
On Tue, Jun 09, 2015 at 01:31:31PM -0700, Florian Fainelli wrote:
Hi Andrew,
On 09/06/15 12:22, Andrew Lunn wrote:
On Tue, Jun 09, 2015 at 11:54:50AM -0700, Florian Fainelli wrote:
Hi,
I am observing a strange problem on net-next (not observed with net,
bisection in progress) where
On Sat, Jun 20, 2015 at 06:01:33PM -0700, Florian Fainelli wrote:
Le 06/20/15 09:15, Andrew Lunn a écrit :
When a switch is attached to the mdio bus, the mdio bus can be used
while the interface is not open. If the IPG clock are not enabled,
MDIO reads/writes will simply time out. So enable
the clock will only be disabled if there are no
other users.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
v2:
Only enable/disable the IPG clock.
drivers/net/ethernet/freescale/fec_main.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet
Allow the contents of the statistics counters to be shown in debugfs.
This is particularly useful for the cpu and dsa ports, which cannot be
seen using ethtools -S.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 59 +
1
The device map is used to route packets between cascaded switches.
Add dumping a switches device map via debugfs.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 41 +
drivers/net/dsa/mv88e6xxx.h | 1 +
2 files changed, 42
Dump the Address Translation Unit via a file in debugfs.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 81 +
drivers/net/dsa/mv88e6xxx.h | 3 ++
2 files changed, 84 insertions(+)
diff --git a/drivers/net/dsa/mv88e6xxx.c
,
including the CPU port and any DSA ports. You cannot get statistics
for these ports via ethtool.
Andrew Lunn (6):
dsa: mv88e6xxx: Add debugfs interface for registers
dsa: mv88e6xxx: Add debugfs interface for ATU
dsa: mv88x6xxx: Refactor getting a single statistic
dsa: mv88x6xxx: Add
Move the code to retrieve a statistics counter into a function of its
own, so it can later be reused.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 63 ++---
drivers/net/dsa/mv88e6xxx.h | 4 +++
2 files changed, 40 insertions
Allow the contents of the registers to be shown in debugfs.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 50 +
drivers/net/dsa/mv88e6xxx.h | 2 ++
2 files changed, 52 insertions(+)
diff --git a/drivers/net/dsa
Allow the contents of the scratch registers to be shown in debugfs.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 54 +
drivers/net/dsa/mv88e6xxx.h | 3 +++
2 files changed, 57 insertions(+)
diff --git a/drivers/net/dsa
Yes I do have debug too, but via sysfs (with eventually write access) for:
GLOBAL1, GLOBAL2, cpu port registers, SerDes registers, PVIDs, and VTU.
Not really standard though.
We should really get an implementation into mainline. There is no
point us all implementing our own.
You say your code
int mii_id, int regnum) {
struct fec_enet_private *fep = bus-priv;
unsigned long time_left;
+ int ret;
+
+ ret = clk_prepare_enable(fep-clk_ipg);
+ if (ret)
+ return ret;
fep-mii_timeout = 0;
init_completion(fep-mdio_done);
@@ -1779,11
On Tue, Jun 23, 2015 at 03:12:15AM +, Duan Andy wrote:
From: Andrew Lunn and...@lunn.ch Sent: Tuesday, June 23, 2015 10:52 AM
To: Duan Fugang-B38611; Florian Fainelli
Cc: David Miller; Cory Tusar; netdev
Subject: Re: [PATCHv3 net-next] net: fec: Ensure clocks are enabled while
using
On Sat, Jun 20, 2015 at 02:47:20PM -0300, Fabio Estevam wrote:
On Sat, Jun 20, 2015 at 1:15 PM, Andrew Lunn and...@lunn.ch wrote:
@@ -1764,6 +1765,11 @@ static int fec_enet_mdio_read(struct mii_bus *bus,
int mii_id, int regnum)
{
struct fec_enet_private *fep = bus-priv
Zero the statistics counters when setting up the global
registers. Otherwise the counters will remain from the last boot if
the power has not been removed.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
This patch will only cleanly apply after the debug series. There is
no actual dependency, so
On Tue, Jun 23, 2015 at 05:46:08PM -0400, Vivien Didelot wrote:
Implement the Get Next operation for the VLAN Table Unit, and a vtu
debugfs file to dump the hardware VLANs.
A populated VTU can look like this:
# cat /sys/kernel/debug/dsa0/vtu
VID FID SID P0 P1 P2 P3 P4 P5 P6
+static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds, u16 vid,
+ struct mv88e6xxx_vtu_entry *entry)
+{
+int ret, i;
+
+ret = _mv88e6xxx_vtu_wait(ds);
+if (ret 0)
+return ret;
+
+ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
On Tue, Jun 23, 2015 at 05:46:09PM -0400, Vivien Didelot wrote:
This commit implements the port_vlan_dump function in the
dsa_switch_driver structure for Marvell 88E6xxx compatible switches.
This allows to access a switch VLAN Table Unit from standard userspace
commands such as bridge vlan
On Tue, Jun 23, 2015 at 05:46:10PM -0400, Vivien Didelot wrote:
Add support for dumping the VLAN Table Unit entries by pointing to the
port_vlan_dump function implemented for mv88e6xxx.
Signed-off-by: Vivien Didelot vivien.dide...@savoirfairelinux.com
---
drivers/net/dsa/mv88e6352.c | 1 +
gil...@ezchip.com
CC: David S. Miller da...@davemloft.net
CC: Florian Fainelli f.faine...@gmail.com
CC: Guenter Roeck li...@roeck-us.net
CC: Andrew Lunn and...@lunn.ch
CC: Scott Feldman sfel...@gmail.com
Hi Gilad
Acked-by: Andrew Lunn and...@lunn.ch
FYI: I grep'ed the whole kernel
On Fri, Jun 26, 2015 at 01:31:09PM -0700, Phil Hofer wrote:
I've made some changes based on advice from Willy Tarreau.
The changes don't influence the IPv6 performance numbers on our board
relative to the previous patch. I still get about 90% of IPv4
performance.
Enabling NETIF_F_TSO6 still
the clock will only be disabled if there are no
other users.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
v3:
Return the error code from clk_prepare_enable()
v2:
Only enable the IGP clock.
drivers/net/ethernet/freescale/fec_main.c | 21 +++--
1 file changed, 19 insertions(+), 2
On Fri, Jun 12, 2015 at 11:14:25AM -0700, Florian Fainelli wrote:
On 12/06/15 10:18, Andrew Lunn wrote:
By default, DSA and CPU ports are configured to the maximum speed the
switch supports. However there can be use cases where the peer device
port is slower. Allow a fixed-link property
On Sun, Jun 14, 2015 at 08:07:12AM +, Duan Andy wrote:
From: Andrew Lunn and...@lunn.ch Sent: Friday, June 12, 2015 11:39 PM
To: David Miller
Cc: Duan Fugang-B38611; Cory Tusar; netdev; Andrew Lunn
Subject: [PATCH] net: fec: Ensure clocks are enabled while using mdio bus
When
On Wed, Jun 17, 2015 at 02:09:52PM -0400, Vivien Didelot wrote:
Hi Andrew, All,
On 12/06/15 10:18, Andrew Lunn wrote:
By default, DSA and CPU ports are configured to the maximum speed the
switch supports. However there can be use cases where the peer device
port is slower. Allow a fixed
the clocks will only be disabled if there are no
other users.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/ethernet/freescale/fec_main.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec_main.c
b/drivers/net
-by: Florian Fainelli f.faine...@gmail.com
Signed-off-by: Andrew Lunn and...@lunn.ch
---
include/linux/phy.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/linux/phy.h b/include/linux/phy.h
index a26c3f84b8dd..5c3b87c0773c 100644
--- a/include/linux/phy.h
+++ b/include
, allow
port settings to be read from a fixed_phy devices.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6123_61_65.c | 1 +
drivers/net/dsa/mv88e6131.c | 1 +
drivers/net/dsa/mv88e6171.c | 1 +
drivers/net/dsa/mv88e6352.c | 1 +
drivers/net/dsa/mv88e6xxx.c
-off-by: Andrew Lunn and...@lunn.ch
---
include/net/dsa.h | 1 +
net/dsa/dsa.c | 39 +++
2 files changed, 40 insertions(+)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index fbca63ba8f73..24572f99224c 100644
--- a/include/net/dsa.h
+++ b/include/net
Hi Andy
If so, it just need to enable ENET ipg clock for your cases, not all enet
clocks.
Ipg clock is for MDIO bus read/write, for ENET registers accessing.
(fep-clk_ipg)
O.K, thanks. I will respin the patch with just the ipg clock.
Which switch phy do you use ? I tried BCM54220 switch
On Thu, May 28, 2015 at 06:42:15PM -0700, Mathieu Olivari wrote:
This patch set adds initial support for AR8xxx switches using the DSA
subsystem. It currently supports QCA8337 switch, and can be extended to
other hardware in the same family.
This switch was already discussed in the following
+static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
+{
+ int reg;
+
+ switch (port) {
+ case 0:
+ reg = AR8327_REG_PORT0_PAD_CTRL;
+ break;
+ case 6:
+ reg = AR8327_REG_PORT6_PAD_CTRL;
+ break;
+
Fair enough, are there other global things besides counters that could
deserve adding maybe some sort of global/master net_device to help query
switch-wide information?
This was discussed a while back. I like the current abstraction, all
interfaces are real interfaces you can send and receive
On Sat, May 30, 2015 at 02:09:55PM +0200, Bjørn Mork wrote:
Andrew Lunn and...@lunn.ch writes:
Some boards have two CPU interfaces connected to the switch, e.g. WiFi
access points, with 1 port labeled WAN, 4 ports labeled lan1-lan4, and
two port connected to the SoC.
This patch
Do you have lock debugging enabled in your code ? I am getting a recursive
lock warning due to a recursive call to dev_mc_sync(). I think we may have
to implement lock nesting for dsa, similar to how it id done for vlan
support, but I have not been able to figure out how exactly it works yet.
On Fri, May 29, 2015 at 10:36:49AM -0700, Mathieu Olivari wrote:
Alternatively, we could have something similar to what happens for the phy
in the wireless subsystems. Wireless PHYs are not registered as net_device
but they can still be listed, queried or configured through netlink.
It is a
no such switch, such that drv-setup will
fail.
Fix this by using PTR_ERR() consistently which is both more informative
and avoids for the caller to use IS_ERR_OR_NULL().
Fixes: df197195a5248 (net: dsa: split dsa_switch_setup into two functions)
Reported-by: Andrew Lunn and...@lunn.ch
Signed
On Wed, May 27, 2015 at 03:51:59PM -0700, Guenter Roeck wrote:
On 05/27/2015 02:05 PM, Andrew Lunn wrote:
Do you have lock debugging enabled in your code ? I am getting a recursive
lock warning due to a recursive call to dev_mc_sync(). I think we may have
to implement lock nesting for dsa
Also, we already have cases where the switch is connected to the CPU with
more than one Ethernet port. It is easy to imagine that the user of such
a system might want to configure two bridge groups.
Hi Guenter
I think that is orthogonal. Having multiple CPU ports should really
only be seen
+int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
+ u16 bridge_flags)
+{
+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
+ struct mv88e6xxx_vtu_entry entry = { 0 };
+ int prev_vid = vid ? vid - 1 : 4095;
+ int i, ret;
+
+
On Tue, Jun 02, 2015 at 07:16:10AM -0700, Guenter Roeck wrote:
On 06/01/2015 06:27 PM, Vivien Didelot wrote:
Disable the mirroring policy in the monitor control register, since this
feature is not needed.
Signed-off-by: Vivien Didelot vivien.dide...@savoirfairelinux.com
Should this be a
is applicable to SF2, etc.
Andrew Lunn (3):
net: dsa: Refactor DT probing of a switch port
dsa: Add support for multiple cpu ports.
kirkwood: dir665: Enable the second Ethernet to the Switch
Documentation/devicetree/bindings/net/dsa/dsa.txt | 66 -
arch/arm/boot/dts/kirkwood-dir665.dts
Move the DT probing of a switch port into a function of its own, since
it is about to get more complex. Add better error handling as well.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
net/dsa/dsa.c | 77 ++-
1 file changed, 44 insertions
What it requires is that for each user port, you can configure what
cpu port it should use. Marvell devices have this ability, and at a
first look, it seems like SF2 does as well, but i will leave Florian
to answer definitively.
That's right, such configuration happens by using
On Fri, May 29, 2015 at 11:49:54AM -0700, Mathieu Olivari wrote:
On Fri, May 29, 2015 at 04:00:01AM +0200, Andrew Lunn wrote:
FYI:
I have patches which allow DSA to use two cpu interfaces. Seems to
work on my DIR665 with a Marvell Switch.
I will post the patches as an RFC
The Dlink DIR665 has two host Ethernet interfaces connected to the
switch. Now that the DSA core and mv88e6171 driver supports multiple
CPU ports, enable the second interface.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
arch/arm/boot/dts/kirkwood-dir665.dts | 22 --
1 file
interface it
connects to. Each user port can have a phandle to a cpu port which
should be used for traffic between the port and the CPU. Thus simple
load sharing over the two CPU ports can be achieved.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
Documentation/devicetree/bindings/net/dsa/dsa.txt
ports.
This is RFC since net-next is closed during the merge window.
Comments and acked-by, etc, welcome.
Changes since v1:
Move setting is_pseudo_fixed_link into fixed_phy_register.
Removed the precursor work for multiple CPU ports.
Andrew Lunn (3):
dsa: mv88e6xxx: Allow speed/duplex of port
-by: Florian Fainelli f.faine...@gmail.com
Signed-off-by: Andrew Lunn and...@lunn.ch
---
v2: set is_pseudo_fixed_link before registering the phy
---
drivers/net/phy/fixed_phy.c | 1 +
include/linux/phy.h | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/net/phy
Add an inline helper for determining is a port is a DSA port.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 5 ++---
include/net/dsa.h | 5 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa
-off-by: Andrew Lunn and...@lunn.ch
---
v2: Remove support for multiple CPU ports.
---
net/dsa/dsa.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index 392e29a0227d..18eed3fbae93 100644
--- a/net/dsa/dsa.c
+++ b/net/dsa
, allow
port settings to be read from a fixed_phy devices.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6123_61_65.c | 1 +
drivers/net/dsa/mv88e6131.c | 1 +
drivers/net/dsa/mv88e6171.c | 1 +
drivers/net/dsa/mv88e6352.c | 1 +
drivers/net/dsa/mv88e6xxx.c
-by: Andrew Lunn and...@lunn.ch
---
v5:
Rewrite to use runtime PM with fec_runtime_suspend and fec_runtime_resume
drivers/net/ethernet/freescale/fec_main.c | 88 ++-
1 file changed, 75 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec_main.c
b
On Sun, Jul 05, 2015 at 10:14:50PM -0400, Vivien Didelot wrote:
Hi all,
This patchset brings full support for hardware VLANs in DSA, and the Marvell
88E6xxx compatible switch chips.
Hi Vivien
I just booted these patches on my board, and i'm getting WARNINGS:
[ 61.111302] WARNING: CPU: 0
On Tue, Jul 07, 2015 at 01:38:04AM +0200, Andrew Lunn wrote:
On Sun, Jul 05, 2015 at 10:14:50PM -0400, Vivien Didelot wrote:
Hi all,
This patchset brings full support for hardware VLANs in DSA, and the Marvell
88E6xxx compatible switch chips.
Hi Vivien
I just booted these patches
+static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds, u16 vid,
+ struct mv88e6xxx_vtu_entry *entry)
+{
+ int ret, i;
+
+ ret = _mv88e6xxx_vtu_wait(ds);
+ if (ret 0)
+ return ret;
+
+ ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
It has occurred to me that dev_set_promiscuity() and its brethren
dev_set_allmulti() may not be the best of interfaces:
- On cursory inspection of code using these function their name
implies the value of the relevant counter is set to the value passed
as parameter, not incremented by it.
()/close() and mdio read()/write() function
triggering runtime PM operations. Auto suspend is used, since there
are likely to be a number of MDIO operations in a burst during DSA
probe.
Signed-off-by: Andrew Lunn and...@lunn.ch
Cc: Duan Andy fugang.d...@freescale.com
---
RFC since net-next
@@ -3496,10 +3523,11 @@ static int __maybe_unused fec_suspend(struct
device *dev)
netif_device_detach(ndev);
netif_tx_unlock_bh(ndev);
fec_stop(ndev);
- fec_enet_clk_enable(ndev, false);
if (!(fep-wol_flag
On Tue, Jul 07, 2015 at 12:17:57PM -0400, Vivien Didelot wrote:
Hi Andrew, Scott,
Does this fixup http://ix.io/jxq look good to you?
Yes, that looks good.
Andrew
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More
On Mon, Aug 03, 2015 at 05:50:11PM +0200, Lucas Stach wrote:
The clocks are initially active and thus the device is marked active.
This still keeps the PM refcount at 0, the pm_runtime_put_autosuspend()
call at the end of probe then leaves us with an invalid refcount of -1,
which in turn leads
Add register definitions #defines for accessing the EEPROM.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6352.c | 18 ++
drivers/net/dsa/mv88e6xxx.h | 8 ++--
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/net/dsa/mv88e6352.c b
only the device tree binding needs extending
with an additional optional phandle.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
Documentation/devicetree/bindings/net/dsa/dsa.txt | 5 +
net/dsa/dsa.c | 12 +++-
2 files changed, 16 insertions(+), 1
When using a cluster of switches, some topologies will have an MDIO
bus per switch, not one for the whole cluster. Allow this to be
represented in the device tree, by adding an optional mii-bus property
at the switch level.
Signed-off-by: Andrew Lunn and...@lunn.ch
Reviewed-by: Florian Fainelli
switches.
Andrew Lunn (3):
net: dsa: Allow multi hop routes to be expressed
net: dsa: Add dsa_is_dsa_port() helper
dsa: mv88e6xxx: Set DSA mode based on chip abilities
Documentation/devicetree/bindings/net/dsa/dsa.txt | 33 +++
drivers/net/dsa/mv88e6xxx.c
Add an inline helper for determining is a port is a DSA port.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 5 ++---
include/net/dsa.h | 5 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa
to express that a port should be used to reach
more than one switch and the switch maybe more than one hop away.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
Documentation/devicetree/bindings/net/dsa/dsa.txt | 33 +++
net/dsa/dsa.c | 40
Older devices only support a single DSA frame format, where as newer
devices have two. Take this into account when configuring a DSA port.
The port needs to be in plain old DSA mode, since this is a DSA link,
where as the newer format can be used for the CPU port.
Signed-off-by: Andrew Lunn
Modules which are soldered onto the motherboard may also use the sff8079
EEPROM format. Dump these in the same way as SFP modules.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
sfpid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sfpid.c b/sfpid.c
index b1a5044..0b5cd62
On Tue, Aug 18, 2015 at 10:18:51AM -0700, Scott Feldman wrote:
On Tue, Aug 18, 2015 at 7:01 AM, Andrew Lunn and...@lunn.ch wrote:
On Mon, Aug 17, 2015 at 03:36:17PM -0700, sfel...@gmail.com wrote:
From: Scott Feldman sfel...@gmail.com
tree /sys/kernel/debug/rocker
/sys/kernel/debug
On Tue, Aug 18, 2015 at 12:01:10PM -0700, David Miller wrote:
From: Andrew Lunn and...@lunn.ch
Date: Tue, 18 Aug 2015 15:36:41 +0200
We currently take the first address from the interface which is scope
link or higher.
Historically, the global scope address would of been used, but my
-negotiation complete bit unset, but set all
the other bits depending on the fixed phy speed.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/phy/fixed_phy.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/fixed_phy.c b/drivers/net/phy/fixed_phy.c
status, for example that of an
SFP module, to be read from a gpio.
Please don't merge these patches until Florian Fainelli has reviewed
them.
Andrew Lunn (8):
dsa: mv88e6xxx: Allow speed/duplex of port to be configured
phy: fixed_phy: Set supported speed in phydev
net: dsa: Allow
It can be useful for DSA and CPU ports to have a phy-mode property, in
particular to specify RGMII delays. Parse the property and set it in
the fixed-link phydev.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
net/dsa/dsa.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
-off-by: Andrew Lunn and...@lunn.ch
---
net/dsa/dsa.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index 053eb2b8e682..afff17341b73 100644
--- a/net/dsa/dsa.c
+++ b/net/dsa/dsa.c
@@ -176,6 +176,35 @@ __ATTRIBUTE_GROUPS
, port
settings to be read from a fixed_phy devices. The switch driver then
needs to implement the adjust_link op, so the port settings can be
set.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6123_61_65.c | 1 +
drivers/net/dsa/mv88e6131.c | 1 +
drivers/net/dsa
When polling for link status, don't consider ports which have a forced
link. Such ports don't monitor their phy or may not even have a phy.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/net/dsa
Set the supported field of the phydev to indicate the speed features
of the phy. If the phy is never attached to a netdev, but used in an
adjust_link() function, the speed will be incorrectly evaluated to
10/half rather than the correct speed/duplex.
Signed-off-by: Andrew Lunn and...@lunn.ch
-by: Florian Fainelli f.faine...@gmail.com
Signed-off-by: Andrew Lunn and...@lunn.ch
---
v2: set is_pseudo_fixed_link before registering the phy
---
drivers/net/phy/fixed_phy.c | 1 +
include/linux/phy.h | 12
2 files changed, 13 insertions(+)
diff --git a/drivers/net/phy
Some Marvell switches allow the RGMII Rx and Tx clock to be delayed
when the port is using RGMII. Have the adjust_link function look at
the phy interface type and enable this delay as requested.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
drivers/net/dsa/mv88e6xxx.c | 10 ++
drivers
On Sun, Aug 23, 2015 at 11:44:01AM -0700, Florian Fainelli wrote:
Le 08/23/15 02:46, Andrew Lunn a écrit :
Some Marvell switches allow the RGMII Rx and Tx clock to be delayed
when the port is using RGMII. Have the adjust_link function look at
the phy interface type and enable this delay
On Sun, Aug 23, 2015 at 11:40:07AM -0700, Florian Fainelli wrote:
Le 08/23/15 02:47, Andrew Lunn a écrit :
What features a phy supports is masked in genphy_config_init() by
looking at the PHYs BMSR register.
If the link is down, fixed_phy_update_regs() will only set the auto
+ port_dn = cd-port_dn[port];
+ if (of_phy_is_fixed_link(port_dn)) {
+ ret = of_phy_register_fixed_link(port_dn);
+ if (ret) {
+ netdev_err(master,
+ failed to
On Sun, Aug 23, 2015 at 11:40:07AM -0700, Florian Fainelli wrote:
Le 08/23/15 02:47, Andrew Lunn a écrit :
What features a phy supports is masked in genphy_config_init() by
looking at the PHYs BMSR register.
If the link is down, fixed_phy_update_regs() will only set the auto
to find the highest scope address on an
interface, and this is then used for IGMP messages in the routing
code.
Signed-off-by: Andrew Lunn and...@lunn.ch
---
This is RFC because i personally don't know if this is the best fix.
The patch restores previous behavior, while still keeping the bug fix
On Mon, Aug 17, 2015 at 09:31:58PM -0700, David Miller wrote:
From: Andrew Lunn and...@lunn.ch
Date: Mon, 17 Aug 2015 18:09:24 +0200
This is RFC because i personally don't know if this is the best fix.
The patch restores previous behavior, while still keeping the bug fix
On Mon, Aug 17, 2015 at 03:36:17PM -0700, sfel...@gmail.com wrote:
From: Scott Feldman sfel...@gmail.com
tree /sys/kernel/debug/rocker
/sys/kernel/debug/rocker
? 525400123501
? fdb_tbl
? internal_vlan_tbl
? neigh_tbl
?
On Mon, Aug 03, 2015 at 03:13:40PM +0200, Uwe Kleine-König wrote:
Hello,
On Mon, Aug 03, 2015 at 02:55:40PM +0200, Andrew Lunn wrote:
v5 was accepted and then reverted, because it broke imx6. Lucas Stach
debugged what was going wrong and provided a patch. Thanks Lucas. This
has been
On Tue, Aug 04, 2015 at 02:33:38AM -0400, Vivien Didelot wrote:
Refactor mv88e6xxx_port_fdb_{add,del,getnext} to respect the new DSA
switch driver FDB access routines.
The Marvell 88E6xxx switches support up to 4094 FIDs (from 1 to 0xfff;
FID 0 means that multiple address databases are not
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