Signed-off-by: Niklas Cassel nikl...@axis.com
---
drivers/net/phy/micrel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 1190fd8..a422036 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -548,7
Since NULL is a valid clock, we shouldn't use
IS_ERR_OR_NULL.
Implemented as Russell King suggested in:
http://lkml.kernel.org/r/20150207172949.ge8...@n2100.arm.linux.org.uk
Signed-off-by: Niklas Cassel nikl...@axis.com
---
drivers/net/phy/micrel.c | 7 +--
1 file changed, 5 insertions
regression) would return 0
when building without CONFIG_HAVE_CLK.
Cc: stable sta...@vger.kernel.org # 3.19+
Fixes: 63f44b2bfccd (net: phy: micrel: add generic clock-mode-select
support)
Signed-off-by: Niklas Cassel nikl...@axis.com
---
drivers/net/phy/micrel.c | 6 +-
1 file changed, 5 insertions(+), 1
Commit c39c4c6abb89 ("tcp: double default TSQ output bytes limit")
updated default value for tcp_limit_output_bytes
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
Already sent the patch to linux-...@vger.kernel.org,
but sending it to netdev@vger.kernel.org too.
I have a ethernet driver for a 100 Mbps NIC.
The NIC has dedicated hardware for offloading.
The driver has implemented TSO, GSO and BQL.
Since the CPU on the SoC is rather weak, I'd rather
not increase the CPU load by turning off offloading.
Since commit
605ad7f184b6 ("tcp: refine TSO
On 11/09/2015 04:50 PM, Eric Dumazet wrote:
> On Mon, 2015-11-09 at 16:41 +0100, Niklas Cassel wrote:
>> I have a ethernet driver for a 100 Mbps NIC.
>> The NIC has dedicated hardware for offloading.
>> The driver has implemented TSO, GSO and BQL.
>> Since the CPU on
On 11/09/2015 05:24 PM, Eric Dumazet wrote:
> On Mon, 2015-11-09 at 08:07 -0800, Eric Dumazet wrote:
>
>> Your numbers suggest a cwnd growth then, which might show a CC bug.
>>
>> Please run the following when your iper3 runs on regular 4.3 kernel
>>
>> for i in `seq 1 10`
>> do
>> ss -temoi dst
On 11/09/2015 06:23 PM, Eric Dumazet wrote:
> On Mon, 2015-11-09 at 17:50 +0100, Niklas Cassel wrote:
>
>>
>> for i in `seq 1 20`; do ss -temoi dst 192.168.0.141; sleep 1; done
> ...
>> ESTAB 0 0
Greetings fellow hackers :)
I have managed to reproduce my streaming unfairness with the intel e1000 driver.
I believe that commit
605ad7f184b6 ("tcp: refine TSO autosizing")
changed the behavior for 100 Mbps NIC:s with TSO enabled.
I have 2 e1000 cards connected in the same computer, with a
On 11/20/2015 07:16 PM, Eric Dumazet wrote:
> On Fri, 2015-11-20 at 16:33 +0100, Niklas Cassel wrote:
>
>> I've been able to reproduce this on a ARMv7, single core, 100 Mbps NIC.
>> Kernel vanilla 4.3, driver has BQL implemented, but is unfortunately not
>> upstreame
On 11/09/2015 05:07 PM, Eric Dumazet wrote:
> On Mon, 2015-11-09 at 16:53 +0100, Niklas Cassel wrote:
>> On 11/09/2015 04:50 PM, Eric Dumazet wrote:
>>> On Mon, 2015-11-09 at 16:41 +0100, Niklas Cassel wrote:
>>>> I have a ethernet driver for a 100 Mbps NIC.
>&
Hello
I would like to request that
commit eab127717a6af54401ba534790c793ec143cd1fc
Author: Florian Fainelli
Date: Fri Jan 20 15:31:52 2017 -0800
net: phy: Avoid deadlock during phy_error()
phy_error() is called in the PHY state machine workqueue context, and
From: Niklas Cassel <niklas.cas...@axis.com>
phy_device->supported is originally set by the PHY driver.
The ethernet driver should filter phy_device->supported to only contain
flags supported by the IP.
The IP supports setting rx and tx flow control independently,
therefore SUP
From: Niklas Cassel <niklas.cas...@axis.com>
Allow autoneg to enable flow control by default.
The behavior when autoneg is off has not changed.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
Signed-off-by: Jesper Nilsson <jesp...@axis.com>
Acked-by: Lars Persso
On 11/25/2016 04:40 PM, Alexandre Torgue wrote:
> Hi Niklas
>
> On 11/25/2016 01:14 PM, Niklas Cassel wrote:
>> On 11/25/2016 01:10 PM, Niklas Cassel wrote:
>>> On 11/24/2016 07:11 PM, Alexandre Torgue wrote:
>>>> Hi Niklas,
>>> Hello Alexandre
>>
From: Niklas Cassel <niklas.cas...@axis.com>
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
Since dwmac-generic.c calls stmmac_probe_confi
From: Niklas Cassel <niklas.cas...@axis.com>
snps,tso was previously placed under AXI BUS Mode parameters,
suggesting that the property should be in the stmmac-axi-config node.
TSO (TCP Segmentation Offloading) has nothing to do with AXI BUS Mode
parameters, and the parser actually e
From: Niklas Cassel <niklas.cas...@axis.com>
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
Previously, when specifying "snps,dwmac-4.10a
From: Niklas Cassel <niklas.cas...@axis.com>
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled
by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effe
On 11/24/2016 07:11 PM, Alexandre Torgue wrote:
> Hi Niklas,
Hello Alexandre
>
> On 11/24/2016 03:36 PM, Niklas Cassel wrote:
>> From: Niklas Cassel <niklas.cas...@axis.com>
>>
>> The dwmac4 IP can synthesized with 1-8 number of tx queues.
>> On an IP syn
On 11/25/2016 01:10 PM, Niklas Cassel wrote:
> On 11/24/2016 07:11 PM, Alexandre Torgue wrote:
>> Hi Niklas,
> Hello Alexandre
>
>> On 11/24/2016 03:36 PM, Niklas Cassel wrote:
>>> From: Niklas Cassel <niklas.cas...@axis.com>
>>>
>>> The
From: Niklas Cassel <niklas.cas...@axis.com>
phy_device->supported is originally set by the PHY driver.
The ethernet driver should filter phy_device->supported to only contain
flags supported by the IP.
The IP supports setting rx and tx flow control independently,
therefore SUP
From: Niklas Cassel <niklas.cas...@axis.com>
Allow autoneg to enable flow control by default.
The behavior when autoneg is off has not changed.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
Signed-off-by: Lars Persson <lar...@axis.com>
---
drivers/net/ethernet/synopsys
On 12/08/2016 10:02 AM, Alexandre Torgue wrote:
> Hi Niklas
>
> On 12/07/2016 03:20 PM, Niklas Cassel wrote:
>> From: Niklas Cassel <niklas.cas...@axis.com>
>>
>> commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
>> changed the par
Hello Jie Deng
In your cover letter you wrote
dwc-eth-xxx.x
The DWC ethernet core layer (DWC ECL). This layer contains codes
can be shared by different DWC series ethernet cores
Does this mean that code in dwc-eth-xxx.x is common to all
the different Synopsys IPs, GMAC, XGMAC and XLGMAC ?
On 12/08/2016 02:36 PM, Alexandre Torgue wrote:
> Hi Niklas,
>
> On 12/05/2016 05:18 PM, Niklas Cassel wrote:
>> Hello Giuseppe
>>
>>
>> I'm trying to figure out what snps,axi_all is supposed to represent.
>>
>> It appears that the value is sav
On 12/09/2016 10:20 AM, Niklas Cassel wrote:
> On 12/08/2016 02:36 PM, Alexandre Torgue wrote:
>> Hi Niklas,
>>
>> On 12/05/2016 05:18 PM, Niklas Cassel wrote:
>>> Hello Giuseppe
>>>
>>>
>>> I'm trying to figure out what snps,axi_all is
e whole tree.
So I still think that my patch is valid.
>
> Regards
> Peppe
>
> On 12/12/2016 3:18 PM, Giuseppe CAVALLARO wrote:
>> Please Niklas
>>
>> when you send the patch, add my
>>
>> Acked-by: Giuseppe Cavallaro <peppe.cavall...@st.com>
>&
On 12/13/2016 08:22 AM, Giuseppe CAVALLARO wrote:
> On 12/12/2016 5:25 PM, Niklas Cassel wrote:
>>
>>
>> On 12/12/2016 11:19 AM, Joao Pinto wrote:
>>> Hi,
>>>
>>> Às 1:44 AM de 12/10/2016, Florian Fainelli escreveu:
>>>> Le 12/09/16 à
On 12/13/2016 12:49 PM, Joao Pinto wrote:
> Hi Niklas,
>
> Às 4:25 PM de 12/12/2016, Niklas Cassel escreveu:
>>
>> On 12/12/2016 11:19 AM, Joao Pinto wrote:
>>> Hi,
>>>
>>> Às 1:44 AM de 12/10/2016, Florian Fainelli escreveu:
>>>> Le 1
(resend with netdev included)
On 12/09/2016 05:29 PM, Jie Deng wrote:
>
> On 2016/12/9 18:50, Niklas Cassel wrote:
>> Hello Jie Deng
>>
>>
>> In your cover letter you wrote
>>
>> dwc-eth-xxx.x
>> The DWC ethernet core layer (DWC ECL). This layer
You might want to include drivers/net/phy/dp83848.c in your patch.
Support for pause frames in that phy was recently added to netdev-next.
On Wed, Dec 7, 2016 at 3:54 AM, Timur Tabi wrote:
> Florian Fainelli wrote:
>>
>> which is why this made me think the &
From: Niklas Cassel <niklas.cas...@axis.com>
All drivers except pci glue layer calls stmmac_probe_config_dt.
stmmac_probe_config_dt does a kzalloc dma_cfg.
pci glue layer does kzalloc dma_cfg explicitly, so all current
drivers does a kzalloc dma_cfg.
Return an error if no DMA configu
initialization of pbl to stmmac_platform.c
and added a check for pbl != 0 in stmmac_main.c,
to catch a possble pbl == 0 from pci glue.
Niklas Cassel (6):
net: stmmac: return error if no DMA configuration is found
net: stmmac: simplify the common DMA init API
net: stmmac: stmmac_platform: fix
From: Niklas Cassel <niklas.cas...@axis.com>
Use struct stmmac_dma_cfg *dma_cfg as an argument rather
than using all the struct members as individual arguments.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
drivers/net/ethernet/stmicro/stmmac/common.h| 4 ++--
From: Niklas Cassel <niklas.cas...@axis.com>
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT binding.
Before 64c3b252e9fc, snps,fixed-burst and snps,mixed-burst were parsed
regardless if the property snps,pbl existed or not.
From: Niklas Cassel <niklas.cas...@axis.com>
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
Since dwmac-generic.c calls stmmac_probe_confi
From: Niklas Cassel <niklas.cas...@axis.com>
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
Previously, when specifying "snps,dwmac-4.10a
From: Niklas Cassel <niklas.cas...@axis.com>
snps,tso was previously placed under AXI BUS Mode parameters,
suggesting that the property should be in the stmmac-axi-config node.
TSO (TCP Segmentation Offloading) has nothing to do with AXI BUS Mode
parameters, and the parser actually e
On 12/14/2016 01:57 PM, Pavel Machek wrote:
> Hi!
>
>> So if there is a long time before handling interrupts,
>> I guess that it makes sense that one stream could
>> get an advantage in the net scheduler.
>>
>> If I find the time, and if no one beats me to it, I will try to replace
>> the normal
On 12/12/2016 11:19 AM, Joao Pinto wrote:
> Hi,
>
> Às 1:44 AM de 12/10/2016, Florian Fainelli escreveu:
>> Le 12/09/16 à 16:16, Andy Shevchenko a écrit :
>>> On Sat, Dec 10, 2016 at 12:52 AM, Florian Fainelli
>>> wrote:
>>>
It's kind of sad that customers of that IP
On 01/12/2017 04:54 PM, Joao Pinto wrote:
> Às 3:48 PM de 1/12/2017, David Miller escreveu:
>> From: Joao Pinto
>> Date: Thu, 12 Jan 2017 15:46:31 +
>>
>>> Hope we can meet in a LinuxCon soon and have a talk, for you to know
>>> me and this way you will see that I am
From: Niklas Cassel <niklas.cas...@axis.com>
All drivers except pci glue layer calls stmmac_probe_config_dt.
stmmac_probe_config_dt does a kzalloc dma_cfg.
pci glue layer does kzalloc dma_cfg explicitly, so all current
drivers does a kzalloc dma_cfg.
Return an error if no DMA configu
From: Niklas Cassel <niklas.cas...@axis.com>
GMAC and newer supports independent programmable burst lengths for
DMA tx/rx. Add new optional devicetree properties representing this.
To be backwards compatible, snps,pbl will still be valid, but
snps,txpbl/snps,rxpbl will override the value i
From: Niklas Cassel <niklas.cas...@axis.com>
The driver currently always sets the PBLx8/PBLx4 bit, which means that
the pbl values configured via the pbl/txpbl/rxpbl DT properties are
always multiplied by 8/4 in the hardware.
In order to allow the DT to configure lower pbl values,
From: Niklas Cassel <niklas.cas...@axis.com>
Use struct stmmac_dma_cfg *dma_cfg as an argument rather
than using all the struct members as individual arguments.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
drivers/net/ethernet/stmicro/stmmac/common.h| 4 ++--
From: Niklas Cassel <niklas.cas...@axis.com>
DMA_BUS_MODE_RPBL_MASK is really 6 bits,
just like DMA_BUS_MODE_PBL_MASK.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Niklas Cassel <niklas.cas...@axis.com>
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT binding.
Before 64c3b252e9fc, snps,fixed-burst and snps,mixed-burst were parsed
regardless if the property snps,pbl existed or not.
From: Niklas Cassel <niklas.cas...@axis.com>
WR_OSR_LMT and RD_OSR_LMT have a reset value of 1.
Since the reset value wasn't cleared before writing, the value in the
register would be incorrect if specifying an uneven value for
snps,wr_osr_lmt/snps,rd_osr_lmt.
Zero is a valid
From: Niklas Cassel <niklas.cas...@axis.com>
Use struct stmmac_dma_cfg *dma_cfg as an argument rather
than using all the struct members as individual arguments.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
drivers/net/ethernet/stmicro/stmmac/common.h| 4 ++--
From: Niklas Cassel <niklas.cas...@axis.com>
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT binding.
Before 64c3b252e9fc, snps,fixed-burst and snps,mixed-burst were parsed
regardless if the property snps,pbl existed or not.
From: Niklas Cassel <niklas.cas...@axis.com>
Make DMA programmable burst length more configurable in the stmmac driver.
This is done by adding support for independent pbl for tx/rx through DT.
More fine grained tuning of pbl is possible thanks to a DT property saying
that we should NOT mu
From: Niklas Cassel <niklas.cas...@axis.com>
All drivers except pci glue layer calls stmmac_probe_config_dt.
stmmac_probe_config_dt does a kzalloc dma_cfg.
pci glue layer does kzalloc dma_cfg explicitly, so all current
drivers does a kzalloc dma_cfg.
Return an error if no DMA configu
From: Niklas Cassel <niklas.cas...@axis.com>
The driver currently always sets the PBLx8/PBLx4 bit, which means that
the pbl values configured via the pbl/txpbl/rxpbl DT properties are
always multiplied by 8/4 in the hardware.
In order to allow the DT to configure lower pbl values,
From: Niklas Cassel <niklas.cas...@axis.com>
GMAC and newer supports independent programmable burst lengths for
DMA tx/rx. Add new optional devicetree properties representing this.
To be backwards compatible, snps,pbl will still be valid, but
snps,txpbl/snps,rxpbl will override the value i
From: Niklas Cassel <niklas.cas...@axis.com>
DMA_BUS_MODE_RPBL_MASK is really 6 bits,
just like DMA_BUS_MODE_PBL_MASK.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hello Giuseppe
I'm trying to figure out what snps,axi_all is supposed to represent.
It appears that the value is saved, but never used in the code.
Looking at the register specification, I'm guessing that it represents
Address-Aligned Beats, but there is already the property snps,aal
for that.
On 12/05/2016 10:10 AM, Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cas...@axis.com>
>
> commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
> changed the parsing of the DT binding.
>
> Before 64c3b252e9fc, snps,fixed-burst and snps,mi
From: Niklas Cassel <niklas.cas...@axis.com>
>From what I can tell, spin_lock(>lock) is not needed, since the
phy_ethtool_ksettings_set call is not given the priv struct.
phy_start_aneg takes the phydev->lock. Calls to phy_adjust_link
from phy_state_machine also takes t
On 01/04/2017 05:38 PM, Nathan Sullivan wrote:
> On Tue, Dec 20, 2016 at 05:34:34PM +0100, Ralf Baechle wrote:
>> On Fri, Dec 02, 2016 at 09:42:09AM -0600, Nathan Sullivan wrote:
>>> Date: Fri, 2 Dec 2016 09:42:09 -0600
>>> From: Nathan Sullivan
>>> To:
From: Niklas Cassel <niklas.cas...@axis.com>
For core revision 3.x Address-Aligned Beats is available in two registers.
The DT property snps,aal was created for AAL in the DMA bus register,
which is a read/write bit.
The DT property snps,axi_all was created for AXI_AAL in the AXI bu
Let's see if patchwork is smart enough to add the tag to the whole series.
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 01/04/2017 12:48 PM, Joao Pinto wrote:
> This patch set contains the porting of the synopsys/dwc_eth_qos.c driver
> to the stmmac structure. This operat
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 01/04/2017 05:22 PM, Joao Pinto wrote:
> This patch adds a new glue driver called dwmac-dwc-qos-eth which
> was based in the dwc_eth_qos as is. To assure retro-compatibility a slight
> tweak was also added to stmmac_platform.
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 01/04/2017 05:22 PM, Joao Pinto wrote:
> This patch moves stmmac_clk, pclk, clk_ptp_ref and stmmac_rst to the
> plat_stmmacenet_data structure. It also moves these platform variables
> initialization to stmmac_platform. This w
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 01/04/2017 05:22 PM, Joao Pinto wrote:
> This patch adds a new parameter to the stmmac DT: snps,en-tx-lpi-clockgating.
> It was ported from synopsys/dwc_eth_qos.c and it is useful if lpi tx clock
> gating is needed by st
I think you accidentally removed the Reviewed-by from Lars.
On 01/04/2017 05:22 PM, Joao Pinto wrote:
> This patch adds a new glue driver called dwmac-dwc-qos-eth which
> was based in the dwc_eth_qos as is. To assure retro-compatibility a slight
> tweak was also added to stmmac_platform.
>
>
Hello Joao
I just tested this series using the dwc_eth_qos DT bindings.
Good work!
Unfortunately I get the following error:
<3>[ 12.032463] dwc-eth-dwmac f801.ethernet eth0: stmmac_open: ERROR:
allocating the WoL IRQ -1098801248 (-22)
This appears to be because of a corner case in
On 01/04/2017 12:08 PM, Joao Pinto wrote:
> Hi Niklas,
>
> Às 10:59 AM de 1/4/2017, Niklas Cassel escreveu:
>> Hello Joao
>>
>> I just tested this series using the dwc_eth_qos DT bindings.
>> Good work!
>>
>> Unfortunately I get the following error:
&
On 12/13/2016 01:56 PM, Joao Pinto wrote:
> Às 12:50 PM de 12/13/2016, Lars Persson escreveu:
>>> 13 dec. 2016 kl. 13:31 skrev Niklas Cassel <niklas.cas...@axis.com>:
>>>
>>>
>>>
>>>> On 12/13/2016 12:49 PM, Joao Pinto wrote:
>>
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 12/18/2016 09:38 PM, Pavel Machek wrote:
> Fix up memory barriers in stmmac driver. They are meant to protect
> against DMA engine, so smp_ variants are certainly wrong, and dma_
> variants are preferable.
>
> Signed
On 12/14/2016 01:57 PM, Pavel Machek wrote:
> Hi!
>
>> So if there is a long time before handling interrupts,
>> I guess that it makes sense that one stream could
>> get an advantage in the net scheduler.
>>
>> If I find the time, and if no one beats me to it, I will try to replace
>> the normal
On 12/20/2016 03:52 PM, Joao Pinto wrote:
> Hi Niklas,
>
> Às 2:43 PM de 12/20/2016, Niklas Cassel escreveu:
>>
>> On 12/20/2016 01:55 PM, Joao Pinto wrote:
>>> When the hardware is synthesized with multiple queues, all queues are
>>> disabled for
On 12/20/2016 01:55 PM, Joao Pinto wrote:
> When the hardware is synthesized with multiple queues, all queues are
> disabled for default. This patch adds the rx queues configuration.
> This patch was successfully tested in a Synopsys QoS Reference design.
>
> Signed-off-by: Joao Pinto
On 12/19/2016 06:10 PM, Joao Pinto wrote:
> Hi,
>
> I am trying to built net-next git tree and it is failing:
>
> CC drivers/pnp/card.o
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c: In function
> ‘stmmac_hw_fix_mac_speed’:
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c:224:34:
From: Niklas Cassel <niklas.cas...@axis.com>
DMA_BUS_MODE_RPBL_MASK is really 6 bits,
just like DMA_BUS_MODE_PBL_MASK.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Niklas Cassel <niklas.cas...@axis.com>
The driver currently always sets the PBLx8/PBLx4 bit, which means that
the pbl values configured via the pbl/txpbl/rxpbl DT properties are
always multiplied by 8/4 in the hardware.
In order to allow the DT to configure lower pbl values,
From: Niklas Cassel <niklas.cas...@axis.com>
GMAC and newer supports independent programmable burst lengths for
DMA tx/rx. Add new optional devicetree properties representing this.
To be backwards compatible, snps,pbl will still be valid, but
snps,txpbl/snps,rxpbl will override the value i
On 03/24/2017 06:16 PM, Joao Pinto wrote:
> This patch set contains two fixes for problems I detected when ran the driver
> in single queue mode.
>
> Please test in your setups to check if you get better results.
>
> Joao Pinto (2):
> net: stmmac: fix netdev release
> net: stmmac: fix number
On 03/28/2017 03:57 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> Even if hardware supports multiple queues, software can choose to only
> use a subset of them. Make sure we never try to access uninitialized
> queues.
>
> Signed-off-by: Thierry Reding
On 03/27/2017 07:44 PM, Joao Pinto wrote:
> Às 6:28 PM de 3/27/2017, David Miller escreveu:
>> From: Corentin Labbe
>> Date: Mon, 27 Mar 2017 19:00:58 +0200
>>
>>> On Mon, Mar 27, 2017 at 04:26:48PM +0100, Joao Pinto wrote:
Hi David,
Às 7:26 AM de
On 03/30/2017 04:34 PM, Thierry Reding wrote:
> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote:
>> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote:
>>> From: Arnd Bergmann
>>> Date: Tue, 28 Mar 2017 11:48:21 +0200
>>>
A driver must not access the
changes,
so it might be hard to point to a single commit.
Nevertheless:
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 03/28/2017 03:57 PM, Thierry Reding wrote:
> From: Thierry Reding <tred...@nvidia.com>
>
> Some of the data in the new queue structures seems to not be p
On 03/27/2017 11:12 AM, Joao Pinto wrote:
> Às 10:09 AM de 3/27/2017, Corentin Labbe escreveu:
>> On Mon, Mar 27, 2017 at 10:04:57AM +0100, Joao Pinto wrote:
>>> Às 7:26 AM de 3/25/2017, Corentin Labbe escreveu:
On Fri, Mar 24, 2017 at 05:16:45PM +, Joao Pinto wrote:
> For cores
Hello Joao
I was looking at
commit 19d9187317979cf0c25f67017d2676149abc46b2
Author: Joao Pinto
Date: Fri Mar 10 18:24:59 2017 +
net: stmmac: configuration of CBS in case of a TX AVB queue
This patch adds the configuration of the AVB Credit-Based
On 03/20/2017 11:07 PM, Florian Fainelli wrote:
>
> (snip)
>>
>> However, it is kind of sad that drivers are so inconsistent of what goes
>> in probe and what goes in ndo_open...which is tied together with the
>> whole mess of when certain ethtool commands work or do not work.
> Well, inconsistent
From: Niklas Cassel <niklas.cas...@axis.com>
It is usually possible to do
ethtool -s autoneg on
so that you trigger an autoneg before calling
ip link set dev eth0 up
However, stmmac returns -EBUSY if !netif_running.
The only reason for this appears to be that stmmac_init_phy
is calle
On 03/20/2017 06:42 PM, Joao Pinto wrote:
> Às 5:29 PM de 3/20/2017, Niklas Cassel escreveu:
>> From: Niklas Cassel <niklas.cas...@axis.com>
>>
>> It is usually possible to do
>> ethtool -s autoneg on
>> so that you trigger an autoneg before calling
>>
On 03/20/2017 06:43 PM, Florian Fainelli wrote:
> On 03/20/2017 10:29 AM, Niklas Cassel wrote:
>> From: Niklas Cassel <niklas.cas...@axis.com>
>>
>> It is usually possible to do
>> ethtool -s autoneg on
>> so that you trigger an autoneg be
From: Niklas Cassel <niklas.cas...@axis.com>
Setting ethtool ops for stmmac is only allowed when the interface is up.
Setting MTU (a netdev op) for stmmac is only allowed when the interface
is down.
It seems that the only reason why MTU cannot be changed when running is
that we have not bo
On 04/04/2017 03:32 PM, Corentin Labbe wrote:
> This patch add a generic testsuite for testing ethernet network device driver.
>
> Signed-off-by: Corentin Labbe
> ---
>
> Changes since v1:
> - Test for starting master interface
> - Changed printing format to "RESULT:
From: Niklas Cassel <niklas.cas...@axis.com>
Field FL/TPL in register TDES3 is not correctly set on GMAC4.
TX appears to be functional on GMAC 4.10a even if this field is not set,
however, to avoid relying on undefined behavior, set the length in TDES3.
The field has a different m
Survived 10/10 reboot + ping test
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 04/06/2017 10:49 AM, Joao Pinto wrote:
> This patch adds the structure stmmac_tx_queue which contains
> tx queues specific data (previously in stmmac_priv).
>
> Signed-off-by: Joao Pinto &l
Survived 10/10 reboot + ping test
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 04/06/2017 10:49 AM, Joao Pinto wrote:
> This patch adds the structure stmmac_rx_queue which contains
> rx queues specific data (previously in stmmac_priv).
>
> Signed-off-by: Joao Pinto &l
Survived 10/10 reboot + ping test
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 04/06/2017 10:49 AM, Joao Pinto wrote:
> This patch breaks several functions into RX and TX scopes, which
> will be useful when adding multiple buffers mechanism.
>
> Signed-off-b
Survived 10/10 reboot + ping test
Tested-by: Niklas Cassel <niklas.cas...@axis.com>
On 04/06/2017 10:49 AM, Joao Pinto wrote:
> This patch adds the napi variable to the stmmac_rx_queue
> structure and forces that operations like netif_queue_stopped,
> netif_wake_queue, n
From: Niklas Cassel <niklas.cas...@axis.com>
The hardware has a LPI interrupt.
There is already code in the stmmac driver to parse and handle the
interrupt. However, this information was missing from the DT binding.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
---
D
On 04/07/2017 06:48 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 04/07/2017 05:30 PM, Niklas Cassel wrote:
>
>> From: Niklas Cassel <niklas.cas...@axis.com>
>>
>> The hardware has a LPI interrupt.
>> There is already code in the stmmac driver to
On 04/11/2017 10:48 AM, Joao Pinto wrote:
>
> Hi Niklas,
>
> Às 7:33 PM de 4/10/2017, Niklas Cassel escreveu:
>> From: Niklas Cassel <niklas.cas...@axis.com>
>>
>> Field FL/TPL in register TDES3 is not correctly set on GMAC4.
>> TX appears to be f
On 01/04/2017 03:33 PM, Florian Fainelli wrote:
> On 12/02/2016 09:48 AM, Florian Fainelli wrote:
Peppe, any thoughts on this?
>>>
>>> I share what you say.
>>>
>>> In sum, the EEE management inside the stmmac is:
>>>
>>> - the driver looks at own HW cap register if EEE is supported
>>>
>>>
On 03/08/2017 01:22 PM, Joao Pinto wrote:
> This patch adds the RX and TX scheduling algorithms programming.
> It introduces the multiple queues configuration function
> (stmmac_mtl_configuration) in stmmac_main.
>
> Signed-off-by: Joao Pinto
> ---
> changes v1->v2:
> - Just
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