On Thu, 2006-12-28 at 21:05 -0800, David Miller wrote:
From: Benjamin Herrenschmidt [EMAIL PROTECTED]
Date: Wed, 13 Dec 2006 15:07:24 +1100
tg3 says
tg3: eth0: Link is up at 1000 Mbps, full duplex.
tg3: eth0: Flow control is on for TX and on for RX.
but sungem says
eth0:
From: Benjamin Herrenschmidt [EMAIL PROTECTED]
Date: Sat, 30 Dec 2006 08:36:07 +1100
Heh, it's very possible it's a regression I added indeed. I'll try to
have a look next week. Do you know of anybody who can verify on non-mii
hardware or is pause irrelevant there ?
For PCS based PHY's most
From: Benjamin Herrenschmidt [EMAIL PROTECTED]
Date: Wed, 13 Dec 2006 15:07:24 +1100
tg3 says
tg3: eth0: Link is up at 1000 Mbps, full duplex.
tg3: eth0: Flow control is on for TX and on for RX.
but sungem says
eth0: Link is up at 1000 Mbps, full-duplex.
eth0: Pause is disabled
Thanks for testing this stuff.
I'll take a look at the pause-enabling issue in the sungem
drive then work on integrating Eric's patch.
Ok, thanks.
Probably we'll need to put this in post-2.6.20 as the merge
window is closed.
Yup, no hurry there.
Ben.
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On Tue, 2006-12-12 at 06:49 +0100, Eric Lemoine wrote:
On 12/12/06, Benjamin Herrenschmidt [EMAIL PROTECTED] wrote:
On Tue, 2006-12-12 at 06:33 +0100, Eric Lemoine wrote:
On 12/12/06, David Miller [EMAIL PROTECTED] wrote:
[...]
Anyways, Eric your changes look fine as far as I can
On Wed, 2006-12-13 at 14:12 +1100, Benjamin Herrenschmidt wrote:
Been hitting a raw throughput in both directions plus a few other things
on a dual G5 and the driver didn't crash :-)
I'm seeing a problem though but I'm not sure it's related to your patch,
I'll have to test without it.
From: Benjamin Herrenschmidt [EMAIL PROTECTED]
Date: Wed, 13 Dec 2006 14:12:13 +1100
David, could that be the pause stuff not working properly ?
It could be, but if the tg3 says flow control is up in the kernel logs
things ought to be OK.
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Been hitting a raw throughput in both directions plus a few other things
on a dual G5 and the driver didn't crash :-)
I'm seeing a problem though but I'm not sure it's related to your patch,
I'll have to test without it.
Basically, if I use a slightly modified versio of tridge's socklib (raw
On Tue, 2006-12-12 at 20:03 -0800, David Miller wrote:
From: Benjamin Herrenschmidt [EMAIL PROTECTED]
Date: Wed, 13 Dec 2006 14:12:13 +1100
David, could that be the pause stuff not working properly ?
It could be, but if the tg3 says flow control is up in the kernel logs
things ought to
From: Eric Lemoine [EMAIL PROTECTED]
Date: Wed, 29 Nov 2006 11:56:30 +0100
I don't understand why we'd need all this.
I think the following code for gem_interrupt should do the trick:
...
The important thing is: we __netif_rx_schedule even if gem_status is 0
(shared irq case) because we
On 12/12/06, David Miller [EMAIL PROTECTED] wrote:
[...]
Anyways, Eric your changes look fine as far as I can tell, can you
give them a really good testing on some SMP boxes?
Unfortunately I can't, I don't have the hardware (only an old ibook here).
--
Eric
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On Tue, 2006-12-12 at 06:33 +0100, Eric Lemoine wrote:
On 12/12/06, David Miller [EMAIL PROTECTED] wrote:
[...]
Anyways, Eric your changes look fine as far as I can tell, can you
give them a really good testing on some SMP boxes?
Unfortunately I can't, I don't have the hardware (only an
On 12/12/06, Benjamin Herrenschmidt [EMAIL PROTECTED] wrote:
On Tue, 2006-12-12 at 06:33 +0100, Eric Lemoine wrote:
On 12/12/06, David Miller [EMAIL PROTECTED] wrote:
[...]
Anyways, Eric your changes look fine as far as I can tell, can you
give them a really good testing on some SMP
On 11/29/06, David Miller [EMAIL PROTECTED] wrote:
From: Benjamin Herrenschmidt [EMAIL PROTECTED]
Date: Wed, 29 Nov 2006 09:57:24 +1100
This looks mostly fine.
I was thinking about the lockless stuff, and I wonder if there
is a clever way you can get it back down to one PIO on the
On 11/28/06, David Miller [EMAIL PROTECTED] wrote:
From: Eric Lemoine [EMAIL PROTECTED]
Date: Tue, 14 Nov 2006 22:54:40 +0100
On 11/14/06, David Miller [EMAIL PROTECTED] wrote:
From: Eric Lemoine [EMAIL PROTECTED]
Date: Tue, 14 Nov 2006 08:28:42 +0100
because it makes it explicit that
From: Eric Lemoine [EMAIL PROTECTED]
Date: Tue, 14 Nov 2006 22:54:40 +0100
On 11/14/06, David Miller [EMAIL PROTECTED] wrote:
From: Eric Lemoine [EMAIL PROTECTED]
Date: Tue, 14 Nov 2006 08:28:42 +0100
because it makes it explicit that only bits 0 through 6 are taken into
account when
From: Benjamin Herrenschmidt [EMAIL PROTECTED]
Date: Wed, 29 Nov 2006 09:57:24 +1100
This looks mostly fine.
I was thinking about the lockless stuff, and I wonder if there
is a clever way you can get it back down to one PIO on the
GREG_STAT register.
I think you'd need to have
On Tue, 2006-11-28 at 15:43 -0800, David Miller wrote:
At least in theory the atomic + any necessary memory barriers
would be cheaper than the extra PIO read we need otherwise.
Yes, IO reads are generally the worst case scenarios even on machines
with fairly slow locks.
Ben.
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To
From: Eric Lemoine [EMAIL PROTECTED]
Date: Mon, 13 Nov 2006 00:11:49 +0100
+#if GEM_INTERRUPT_LOCKLESS
+
+/* Bitmask representing the interrupt conditions that we clear using
GREG_IACK.
+ * We clear all the top-level interrupt conditions (bits 0 through 6) that we
+ * handle.
+ */
On 11/14/06, David Miller [EMAIL PROTECTED] wrote:
From: Eric Lemoine [EMAIL PROTECTED]
Date: Mon, 13 Nov 2006 00:11:49 +0100
+#if GEM_INTERRUPT_LOCKLESS
+
+/* Bitmask representing the interrupt conditions that we clear using
GREG_IACK.
+ * We clear all the top-level interrupt conditions
From: Eric Lemoine [EMAIL PROTECTED]
Date: Tue, 14 Nov 2006 08:28:42 +0100
because it makes it explicit that only bits 0 through 6 are taken into
account when writing the IACK register.
The phrase bits 0 through 6 doesn't make any sense when bit 3 DOES
NOT EXIST in the hardware, it's reserved,
On 11/10/06, David Miller [EMAIL PROTECTED] wrote:
Please use GREG_STAT_* instead of magic constants for the
interrupt mask and ACK register writes. In fact, there are
some questionable values you use, in particular this one:
+static inline void gem_ack_int(struct gem *gp)
+{
+
Yes, the bit 4 isn't used, but I assumed clearing it shouldn't be prolem.
Always leave reserved bits alone ... I agree it's very unlikely in this
case that it could cause a problem but I've seen stranger things
Ben.
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the
From: Eric Lemoine [EMAIL PROTECTED]
Date: Fri, 10 Nov 2006 14:28:41 +0100
On 11/10/06, David Miller [EMAIL PROTECTED] wrote:
Please use GREG_STAT_* instead of magic constants for the
interrupt mask and ACK register writes. In fact, there are
some questionable values you use, in
Please use GREG_STAT_* instead of magic constants for the
interrupt mask and ACK register writes. In fact, there are
some questionable values you use, in particular this one:
+static inline void gem_ack_int(struct gem *gp)
+{
+ writel(0x3f, gp-regs + GREG_IACK);
+}
There is no bit
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