Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Add a missing newline at the end of a DRM_INFO message.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
Hi everyone,
Here is the second batch of patches to add GK20A support to Nouveau. This time
we are adding the actual chip support, and this series brings the driver to a
point where a slightly-tweaked Mesa successfully runs shaders and renders
triangles on GBM! Many thanks to Thierry Reding and
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h| 1 +
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git
nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
enabled at all on chips that rely exclusively on external firmware, even
though such a use-case is valid.
Relax the conditions enabling the GR engine to
Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 2 +
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply neither.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
https://bugs.freedesktop.org/show_bug.cgi?id=76483
--- Comment #2 from Damien Diederen d...@crosstwine.com ---
Created attachment 96281
-- https://bugs.freedesktop.org/attachment.cgi?id=96281action=edit
[WIP,BROKEN] drm/nv50: Hack FORCE_DP_TRAIN method for DPMS power-on
Hi Ben,
Excellent!
Hello,
One of my GPU (GK107/NVE7) fails to properly fetch its vbios from PROM
at boot time but, if I blacklist the module and load it myself later on,
it always succeeds. To make things weirder, the same card works great on
another computer.
Here is the relevant code in Nouveau to fetch the
On Mon, Mar 24, 2014 at 05:42:23PM +0900, Alexandre Courbot wrote:
Add a missing newline at the end of a DRM_INFO message.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by:
On Mon, Mar 24, 2014 at 05:42:24PM +0900, Alexandre Courbot wrote:
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
On Mon, Mar 24, 2014 at 05:42:26PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
[...]
static int
-nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-
On Mon, Mar 24, 2014 at 05:42:25PM +0900, Alexandre Courbot wrote:
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by:
On Mon, Mar 24, 2014 at 05:42:27PM +0900, Alexandre Courbot wrote:
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
[...]
+#include subdev/ibus.h
+
+struct nvea_ibus_priv {
+ struct nouveau_ibus base;
+};
+
+static
On Mon, Mar 24, 2014 at 05:42:30PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 6ef8bf181b2d..f997a18f5760 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++
On Mon, Mar 24, 2014 at 05:42:31PM +0900, Alexandre Courbot wrote:
Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
run from non-prepadded firmware files.
Perhaps this (and the comment in the code) should mention a unit. In
this case it's 0x40 words. Also, I think using
On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply
On Mon, Mar 24, 2014 at 05:42:34PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
[...]
+ /* TODO will need an implementation for this at some point... */
Do we? If so the
I hope I'm writing to people who can help me. If not you, then I have a
serious inconvenience and am going to be at a complete loss for where to turn.
Let me explain my setup. I have an HTPC with a GeForce GT620. It is connected
to a Denon AVR-1913 via HDMI, because that does all the
26 matches
Mail list logo
