On Tue, Sep 17, 2019 at 01:48:20PM +1000, Ben Skeggs wrote:
> On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote:
> >
> > From: Thierry Reding
> >
> > The engine field in the FIFO fault information registers is actually 9
> > bits wide.
> Looks like this is true for fault buffer parsing too.
On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote:
>
> From: Thierry Reding
>
> The engine field in the FIFO fault information registers is actually 9
> bits wide.
Looks like this is true for fault buffer parsing too.
>
> Signed-off-by: Thierry Reding
> ---
>
From: Thierry Reding
The engine field in the FIFO fault information registers is actually 9
bits wide.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
