Re: [Nouveau] [PATCH v4 2/4] pci: add nvkm_pcie_get_speed
On Fri, 13 Sep 2019 at 21:33, Karol Herbst wrote:
>
> v2: fixed compilation error
Is there any need for this patch at all now, if you're forcing 8_0
rather than the pre-DEVINIT speed?
>
> Signed-off-by: Karol Herbst
> Reviewed-by: Lyude Paul
> ---
> drm/nouveau/include/nvkm/subdev/pci.h | 1 +
> drm/nouveau/nvkm/subdev/pci/pcie.c| 8
> 2 files changed, 9 insertions(+)
>
> diff --git a/drm/nouveau/include/nvkm/subdev/pci.h
> b/drm/nouveau/include/nvkm/subdev/pci.h
> index 4803a4fad..b29101e48 100644
> --- a/drm/nouveau/include/nvkm/subdev/pci.h
> +++ b/drm/nouveau/include/nvkm/subdev/pci.h
> @@ -53,4 +53,5 @@ int gp100_pci_new(struct nvkm_device *, int, struct
> nvkm_pci **);
>
> /* pcie functions */
> int nvkm_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8 width);
> +enum nvkm_pcie_speed nvkm_pcie_get_speed(struct nvkm_pci *);
> #endif
> diff --git a/drm/nouveau/nvkm/subdev/pci/pcie.c
> b/drm/nouveau/nvkm/subdev/pci/pcie.c
> index 354ac4c85..b4203ff1a 100644
> --- a/drm/nouveau/nvkm/subdev/pci/pcie.c
> +++ b/drm/nouveau/nvkm/subdev/pci/pcie.c
> @@ -177,3 +177,11 @@ nvkm_pcie_set_link(struct nvkm_pci *pci, enum
> nvkm_pcie_speed speed, u8 width)
>
> return ret;
> }
> +
> +enum nvkm_pcie_speed
> +nvkm_pcie_get_speed(struct nvkm_pci *pci)
> +{
> + if (!pci || !pci_is_pcie(pci->pdev) || !pci->func->pcie.cur_speed)
> + return -ENODEV;
> + return pci->func->pcie.cur_speed(pci);
> +}
> --
> 2.21.0
>
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Re: [Nouveau] [PATCH 1/3] pci: force disable ASPM before changing the link speed
On Fri, 13 Sep 2019 at 05:00, Karol Herbst wrote:
>
> taken from nvgpu
>
> Signed-off-by: Karol Herbst
> ---
> drm/nouveau/nvkm/subdev/pci/g84.c | 9 +
> drm/nouveau/nvkm/subdev/pci/g92.c | 1 +
> drm/nouveau/nvkm/subdev/pci/g94.c | 1 +
> drm/nouveau/nvkm/subdev/pci/gf100.c | 1 +
> drm/nouveau/nvkm/subdev/pci/gf106.c | 1 +
> drm/nouveau/nvkm/subdev/pci/gk104.c | 1 +
> drm/nouveau/nvkm/subdev/pci/pcie.c | 14 ++
> drm/nouveau/nvkm/subdev/pci/priv.h | 2 ++
> 8 files changed, 30 insertions(+)
>
> diff --git a/drm/nouveau/nvkm/subdev/pci/g84.c
> b/drm/nouveau/nvkm/subdev/pci/g84.c
> index 62438d892..353d70d7e 100644
> --- a/drm/nouveau/nvkm/subdev/pci/g84.c
> +++ b/drm/nouveau/nvkm/subdev/pci/g84.c
> @@ -122,6 +122,14 @@ g84_pci_init(struct nvkm_pci *pci)
> nvkm_pci_mask(pci, 0x041c, 0x0060, 0x);
> }
>
> +void
> +g84_pcie_force_aspm_off(struct nvkm_pci *pci, bool status)
> +{
> + /* L0s and L1 */
> + u32 value = status ? 0x180 : 0x0;
> + nvkm_pci_mask(pci, 0x150, 0x180, value);
> +}
> +
> int
> g84_pcie_init(struct nvkm_pci *pci)
> {
> @@ -147,6 +155,7 @@ g84_pci_func = {
> .pcie.set_version = g84_pcie_set_version,
> .pcie.version = g84_pcie_version,
> .pcie.version_supported = g84_pcie_version_supported,
> + .pcie.force_aspm_off = g84_pcie_force_aspm_off,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/pci/g92.c
> b/drm/nouveau/nvkm/subdev/pci/g92.c
> index 48874359d..8c35cc89e 100644
> --- a/drm/nouveau/nvkm/subdev/pci/g92.c
> +++ b/drm/nouveau/nvkm/subdev/pci/g92.c
> @@ -48,6 +48,7 @@ g92_pci_func = {
> .pcie.set_version = g84_pcie_set_version,
> .pcie.version = g84_pcie_version,
> .pcie.version_supported = g92_pcie_version_supported,
> + .pcie.force_aspm_off = g84_pcie_force_aspm_off,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/pci/g94.c
> b/drm/nouveau/nvkm/subdev/pci/g94.c
> index 09adb37a5..aa152d798 100644
> --- a/drm/nouveau/nvkm/subdev/pci/g94.c
> +++ b/drm/nouveau/nvkm/subdev/pci/g94.c
> @@ -40,6 +40,7 @@ g94_pci_func = {
> .pcie.set_version = g84_pcie_set_version,
> .pcie.version = g84_pcie_version,
> .pcie.version_supported = g92_pcie_version_supported,
> + .pcie.force_aspm_off = g84_pcie_force_aspm_off,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/pci/gf100.c
> b/drm/nouveau/nvkm/subdev/pci/gf100.c
> index 00a5e7d3e..8676480c3 100644
> --- a/drm/nouveau/nvkm/subdev/pci/gf100.c
> +++ b/drm/nouveau/nvkm/subdev/pci/gf100.c
> @@ -93,6 +93,7 @@ gf100_pci_func = {
> .pcie.set_version = gf100_pcie_set_version,
> .pcie.version = gf100_pcie_version,
> .pcie.version_supported = g92_pcie_version_supported,
> + .pcie.force_aspm_off = g84_pcie_force_aspm_off,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/pci/gf106.c
> b/drm/nouveau/nvkm/subdev/pci/gf106.c
> index 11bf419af..8079ebdd4 100644
> --- a/drm/nouveau/nvkm/subdev/pci/gf106.c
> +++ b/drm/nouveau/nvkm/subdev/pci/gf106.c
> @@ -40,6 +40,7 @@ gf106_pci_func = {
> .pcie.set_version = gf100_pcie_set_version,
> .pcie.version = gf100_pcie_version,
> .pcie.version_supported = g92_pcie_version_supported,
> + .pcie.force_aspm_off = g84_pcie_force_aspm_off,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/pci/gk104.c
> b/drm/nouveau/nvkm/subdev/pci/gk104.c
> index e68030507..b73922c52 100644
> --- a/drm/nouveau/nvkm/subdev/pci/gk104.c
> +++ b/drm/nouveau/nvkm/subdev/pci/gk104.c
> @@ -219,6 +219,7 @@ gk104_pci_func = {
> .pcie.set_version = gf100_pcie_set_version,
> .pcie.version = gf100_pcie_version,
> .pcie.version_supported = gk104_pcie_version_supported,
> + .pcie.force_aspm_off = g84_pcie_force_aspm_off,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/pci/pcie.c
> b/drm/nouveau/nvkm/subdev/pci/pcie.c
> index d71e5db50..354ac4c85 100644
> --- a/drm/nouveau/nvkm/subdev/pci/pcie.c
> +++ b/drm/nouveau/nvkm/subdev/pci/pcie.c
> @@ -111,6 +111,14 @@ nvkm_pcie_init(struct nvkm_pci *pci)
> return 0;
> }
>
> +void
> +nvkm_pcie_force_aspm_off(struct nvkm_pci *pci, bool status)
> +{
> + if (!pci->func->pcie.force_aspm_off)
> + return;
> + pci->func->pcie.force_aspm_off(pci, status);
> +}
> +
> int
> nvkm_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8
> width)
> {
> @@ -157,9 +165,15 @@ nvkm_pcie_set_link(struct nvkm_pci *pci, enum
> nvkm_pcie_speed speed, u8 width)
> nvkm_debug(subdev, "set link to %s x%i\n",
>nvkm_pcie_speeds[speed], width);
>
> + /* force disable ASPM */
> + nvkm_pcie_force_aspm_off(pci, true);
> +
> ret = pci->func->pcie.set_link(pci, speed, width);
> if (ret < 0)
> nvkm_error(subdev, "setting link failed: %i\n", ret);
>
> + /* lift force disable ASPM */
> + nvkm_pcie_force_aspm_off(pci,
Re: [Nouveau] [PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers
On Tue, 17 Sep 2019 at 01:04, Thierry Reding wrote:
>
> From: Thierry Reding
>
> The GPUs found on Tegra SoCs have registers that can be used to read the
> WPR configuration. Use these registers instead of reaching into the
> memory controller's register space to read the same information.
>
> Signed-off-by: Thierry Reding
> ---
> .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +-
> .../drm/nouveau/nvkm/subdev/secboot/gm20b.c | 81 ---
> .../drm/nouveau/nvkm/subdev/secboot/gp10b.c | 4 +-
> 3 files changed, 53 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
> b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
> index 62c5e162099a..280b1448df88 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
> @@ -41,6 +41,6 @@ int gm200_secboot_run_blob(struct nvkm_secboot *, struct
> nvkm_gpuobj *,
>struct nvkm_falcon *);
>
> /* Tegra-only */
> -int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32);
> +int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *);
>
> #endif
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
> index df8b919dcf09..f8a543122219 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
> @@ -23,39 +23,65 @@
> #include "acr.h"
> #include "gm200.h"
>
> -#define TEGRA210_MC_BASE 0x70019000
> -
> #ifdef CONFIG_ARCH_TEGRA
> -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
> -#define MC_SECURITY_CARVEOUT2_BOM_00xc5c
> -#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60
> -#define MC_SECURITY_CARVEOUT2_SIZE_128K0xc64
> -#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1)
> /**
> * gm20b_secboot_tegra_read_wpr() - read the WPR registers on Tegra
> *
> - * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR
> region
> - * is reserved from system memory by the bootloader and irreversibly locked.
> - * This function reads the address and size of the pre-configured WPR region.
> + * On dGPU, we can manage the WPR region ourselves, but on Tegra this region
> + * is allocated from system memory by the secure firmware. The region is then
> + * marked as a "secure carveout" and irreversibly locked. Furthermore, the
> WPR
> + * secure carveout is also configured to be sent to the GPU via a dedicated
> + * serial bus between the memory controller and the GPU. The GPU requests
> this
> + * information upon leaving reset and exposes it through a FIFO register at
> + * offset 0x100cd4.
> + *
> + * The FIFO register's lower 4 bits can be used to set the read index into
> the
> + * FIFO. After each read of the FIFO register, the read index is incremented.
> + *
> + * Indices 2 and 3 contain the lower and upper addresses of the WPR. These
> are
> + * stored in units of 256 B. The WPR is inclusive of both addresses.
> + *
> + * Unfortunately, for some reason the WPR info register doesn't contain the
> + * correct values for the secure carveout. It seems like the upper address is
> + * always too small by 128 KiB - 1. Given that the secure carvout size in the
> + * memory controller configuration is specified in units of 128 KiB, it's
> + * possible that the computation of the upper address of the WPR is wrong and
> + * causes this difference.
> */
> int
> -gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
> +gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb)
> {
> + struct nvkm_device *device = gsb->base.subdev.device;
> struct nvkm_secboot *sb = >base;
> - void __iomem *mc;
> - u32 cfg;
> + u64 base, limit;
> + u32 value;
>
> - mc = ioremap(mc_base, 0xd00);
> - if (!mc) {
> - nvkm_error(>subdev, "Cannot map Tegra MC registers\n");
> - return -ENOMEM;
> - }
> - sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
> - ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) <<
> 32);
> - sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K)
> - << 17;
> - cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0);
> - iounmap(mc);
> + /* set WPR info register to point at WPR base address register */
> + value = nvkm_rd32(device, 0x100cd4);
> + value &= ~0xf;
> + value |= 0x2;
> + nvkm_wr32(device, 0x100cd4, value);
> +
> + /* read base address */
> + value = nvkm_rd32(device, 0x100cd4);
> + base = (u64)(value >> 4) << 12;
> +
> + /* read limit */
> + value = nvkm_rd32(device, 0x100cd4);
> + limit = (u64)(value >> 4) << 12;
acr_r352_wpr_is_set() does a similar readout to confirm the HS
firmware did its job on dGPU, perhaps this part of it
Re: [Nouveau] [PATCH 2/6] drm/nouveau: fault: Widen engine field
On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote: > > From: Thierry Reding > > The engine field in the FIFO fault information registers is actually 9 > bits wide. Looks like this is true for fault buffer parsing too. > > Signed-off-by: Thierry Reding > --- > drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c > b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c > index b5e32295237b..28306c5f6651 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c > @@ -137,8 +137,8 @@ gv100_fault_intr_fault(struct nvkm_fault *fault) > info.addr = ((u64)addrhi << 32) | addrlo; > info.inst = ((u64)insthi << 32) | (info0 & 0xf000); > info.time = 0; > - info.engine = (info0 & 0x00ff); > info.aperture = (info0 & 0x0c00) >> 10; > + info.engine = (info0 & 0x01ff); > info.valid = (info1 & 0x8000) >> 31; > info.gpc= (info1 & 0x1f00) >> 24; > info.hub= (info1 & 0x0010) >> 20; > -- > 2.23.0 > > ___ > Nouveau mailing list > Nouveau@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/nouveau ___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [PATCH 1/6] drm/nouveau: fault: Store aperture in fault information
On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote:
>
> From: Thierry Reding
>
> The fault information register contains data about the aperture that
> caused the failure. This can be useful in debugging aperture related
> programming bugs.
Should this be parsed for fault buffer entries too?
>
> Signed-off-by: Thierry Reding
> ---
> drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h | 1 +
> drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c| 3 ++-
> drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 1 +
> 3 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
> b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
> index 97322f95b3ee..1cc862bc1122 100644
> --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
> +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
> @@ -21,6 +21,7 @@ struct nvkm_fault_data {
> u64 addr;
> u64 inst;
> u64 time;
> + u8 aperture;
> u8 engine;
> u8 valid;
> u8gpc;
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
> index 5d4b695cab8e..81cbe1cc4804 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
> @@ -519,9 +519,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct
> nvkm_fault_data *info)
> chan = nvkm_fifo_chan_inst_locked(>base, info->inst);
>
> nvkm_error(subdev,
> - "fault %02x [%s] at %016llx engine %02x [%s] client %02x "
> + "fault %02x [%s] at %016llx aperture %02x engine %02x [%s]
> client %02x "
>"[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n",
>info->access, ea ? ea->name : "", info->addr,
> + info->aperture,
>info->engine, ee ? ee->name : en,
>info->client, ct, ec ? ec->name : "",
>info->reason, er ? er->name : "", chan ? chan->chid : -1,
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
> index 6747f09c2dc3..b5e32295237b 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
> @@ -138,6 +138,7 @@ gv100_fault_intr_fault(struct nvkm_fault *fault)
> info.inst = ((u64)insthi << 32) | (info0 & 0xf000);
> info.time = 0;
> info.engine = (info0 & 0x00ff);
> + info.aperture = (info0 & 0x0c00) >> 10;
> info.valid = (info1 & 0x8000) >> 31;
> info.gpc= (info1 & 0x1f00) >> 24;
> info.hub= (info1 & 0x0010) >> 20;
> --
> 2.23.0
>
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Re: [Nouveau] [PATCH 3/6] drm/nouveau: Remove bogus gk20a aperture callback
On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote:
>
> From: Thierry Reding
>
> The gk20a (as well as all subsequent Tegra instantiations of the GPU) do
> in fact use the same apertures as regular GPUs. Prior to gv11b there are
> no checks in hardware for the aperture, so we get away with setting VRAM
> as the aperture for buffers that are actually in system memory.
Can GK20A take comptags with aperture set to system memory? For some
reason I can recall, I was under the impression PTEs needed to be
pointed at "vidmem" (despite them actually accessing system memory
anyway) on Tegra parts for compression to work? I could be mistaken
though.
Ben.
>
> Signed-off-by: Thierry Reding
> ---
> drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 1 -
> drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c | 10 --
> drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c | 4 ++--
> drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c | 2 +-
> 4 files changed, 3 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
> b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
> index fb3a9e8bb9cd..9862f44ac8b5 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
> @@ -212,7 +212,6 @@ void gf100_vmm_flush(struct nvkm_vmm *, int);
> void gf100_vmm_invalidate(struct nvkm_vmm *, u32 type);
> void gf100_vmm_invalidate_pdb(struct nvkm_vmm *, u64 addr);
>
> -int gk20a_vmm_aper(enum nvkm_memory_target);
> int gk20a_vmm_valid(struct nvkm_vmm *, void *, u32, struct nvkm_vmm_map *);
>
> int gm200_vmm_new_(const struct nvkm_vmm_func *, const struct nvkm_vmm_func
> *,
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
> index 16d7bf727292..999b953505b3 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
> @@ -25,16 +25,6 @@
>
> #include
>
> -int
> -gk20a_vmm_aper(enum nvkm_memory_target target)
> -{
> - switch (target) {
> - case NVKM_MEM_TARGET_NCOH: return 0;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> int
> gk20a_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
> struct nvkm_vmm_map *map)
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
> index 7a6066d886cd..f5d7819c4a40 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
> @@ -25,7 +25,7 @@ static const struct nvkm_vmm_func
> gm20b_vmm_17 = {
> .join = gm200_vmm_join,
> .part = gf100_vmm_part,
> - .aper = gk20a_vmm_aper,
> + .aper = gf100_vmm_aper,
> .valid = gk20a_vmm_valid,
> .flush = gf100_vmm_flush,
> .invalidate_pdb = gf100_vmm_invalidate_pdb,
> @@ -41,7 +41,7 @@ static const struct nvkm_vmm_func
> gm20b_vmm_16 = {
> .join = gm200_vmm_join,
> .part = gf100_vmm_part,
> - .aper = gk20a_vmm_aper,
> + .aper = gf100_vmm_aper,
> .valid = gk20a_vmm_valid,
> .flush = gf100_vmm_flush,
> .invalidate_pdb = gf100_vmm_invalidate_pdb,
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
> index 180c8f006e32..ffe84ea2f7d9 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
> @@ -43,7 +43,7 @@ static const struct nvkm_vmm_func
> gp10b_vmm = {
> .join = gp100_vmm_join,
> .part = gf100_vmm_part,
> - .aper = gk20a_vmm_aper,
> + .aper = gf100_vmm_aper,
> .valid = gp10b_vmm_valid,
> .flush = gp100_vmm_flush,
> .mthd = gp100_vmm_mthd,
> --
> 2.23.0
>
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Re: [Nouveau] [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached
On 16/09/2019 16:57, Thierry Reding wrote:
On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote:
Hi Thierry,
On 16/09/2019 16:04, Thierry Reding wrote:
From: Thierry Reding
If the GPU is already attached to an IOMMU, don't detach it and setup an
explicit IOMMU domain. Since Nouveau can now properly handle the case of
the DMA API being backed by an IOMMU, just continue using the DMA API.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/nvkm/engine/device/tegra.c| 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index d0d52c1d4aee..fc652aaa41c7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -23,10 +23,6 @@
#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
#include "priv.h"
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
-#include
-#endif
-
static int
nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
{
@@ -109,14 +105,13 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra
*tdev)
unsigned long pgsize_bitmap;
int ret;
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
- if (dev->archdata.mapping) {
- struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
-
- arm_iommu_detach_device(dev);
- arm_iommu_release_mapping(mapping);
- }
-#endif
+ /*
+* Skip explicit IOMMU initialization if the GPU is already attached
+* to an IOMMU domain. This can happen if the DMA API is backed by an
+* IOMMU.
+*/
+ if (iommu_get_domain_for_dev(dev))
+ return;
Beware of "iommu.passthrough=1" - you could get a valid default domain here
yet still have direct/SWIOTLB DMA ops. I guess you probably want to
double-check the domain type as well.
Good point. An earlier version of this patch had an additional check for
IOMMU_DOMAIN_DMA, but then that failed on 32-bit ARM because there the
DMA API can also use IOMMU_DOMAIN_UNMANAGED type domains. Checking for
IOMMU_DOMAIN_IDENTIFY should be safe, though. That doesn't seem to
appear in arch/arm, arch/arm64 or drivers/iommu/dma-iommu.c.
Right, "domain && domain->type != IOMMU_DOMAIN_IDENTITY" should be
sufficient to answer "is the DMA layer managing my address space for
me?" unless and until some massive API change happens (which I certainly
don't foresee).
Robin.
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Re: [Nouveau] [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached
On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote:
> Hi Thierry,
>
> On 16/09/2019 16:04, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > If the GPU is already attached to an IOMMU, don't detach it and setup an
> > explicit IOMMU domain. Since Nouveau can now properly handle the case of
> > the DMA API being backed by an IOMMU, just continue using the DMA API.
> >
> > Signed-off-by: Thierry Reding
> > ---
> > .../drm/nouveau/nvkm/engine/device/tegra.c| 19 +++
> > 1 file changed, 7 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
> > b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
> > index d0d52c1d4aee..fc652aaa41c7 100644
> > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
> > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
> > @@ -23,10 +23,6 @@
> > #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
> > #include "priv.h"
> > -#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
> > -#include
> > -#endif
> > -
> > static int
> > nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
> > {
> > @@ -109,14 +105,13 @@ nvkm_device_tegra_probe_iommu(struct
> > nvkm_device_tegra *tdev)
> > unsigned long pgsize_bitmap;
> > int ret;
> > -#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
> > - if (dev->archdata.mapping) {
> > - struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
> > -
> > - arm_iommu_detach_device(dev);
> > - arm_iommu_release_mapping(mapping);
> > - }
> > -#endif
> > + /*
> > +* Skip explicit IOMMU initialization if the GPU is already attached
> > +* to an IOMMU domain. This can happen if the DMA API is backed by an
> > +* IOMMU.
> > +*/
> > + if (iommu_get_domain_for_dev(dev))
> > + return;
>
> Beware of "iommu.passthrough=1" - you could get a valid default domain here
> yet still have direct/SWIOTLB DMA ops. I guess you probably want to
> double-check the domain type as well.
Good point. An earlier version of this patch had an additional check for
IOMMU_DOMAIN_DMA, but then that failed on 32-bit ARM because there the
DMA API can also use IOMMU_DOMAIN_UNMANAGED type domains. Checking for
IOMMU_DOMAIN_IDENTIFY should be safe, though. That doesn't seem to
appear in arch/arm, arch/arm64 or drivers/iommu/dma-iommu.c.
Thierry
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Re: [Nouveau] [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
On Mon, Sep 16, 2019 at 05:49:46PM +0200, Thierry Reding wrote:
> On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote:
> > On 16/09/2019 16:04, Thierry Reding wrote:
> > > From: Thierry Reding
> > >
> > > There are extra registers that need to be programmed to make the level 2
> > > cache work on GP10B, such as the stream ID register that is used when an
> > > SMMU is used to translate memory addresses.
> > >
> > > Signed-off-by: Thierry Reding
> > > ---
> > > .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
> > > .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild| 1 +
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 69 +++
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h| 2 +
> > > 5 files changed, 74 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > >
> > > diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > > b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > > index 644d527c3b96..d76f60d7d29a 100644
> > > --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > > +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > > @@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct
> > > nvkm_ltc **);
> > > int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > +int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > > #endif
> > > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > > b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > > index c3c7159f3411..d2d6d5f4028a 100644
> > > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > > @@ -2380,7 +2380,7 @@ nv13b_chipset = {
> > > .fuse = gm107_fuse_new,
> > > .ibus = gp10b_ibus_new,
> > > .imem = gk20a_instmem_new,
> > > - .ltc = gp102_ltc_new,
> > > + .ltc = gp10b_ltc_new,
> > > .mc = gp10b_mc_new,
> > > .mmu = gp10b_mmu_new,
> > > .secboot = gp10b_secboot_new,
> > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > > b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > > index 2b6d36ea7067..728d75010847 100644
> > > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > > @@ -6,3 +6,4 @@ nvkm-y += nvkm/subdev/ltc/gm107.o
> > > nvkm-y += nvkm/subdev/ltc/gm200.o
> > > nvkm-y += nvkm/subdev/ltc/gp100.o
> > > nvkm-y += nvkm/subdev/ltc/gp102.o
> > > +nvkm-y += nvkm/subdev/ltc/gp10b.o
> > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > > b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > > new file mode 100644
> > > index ..4d27c6ea1552
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > > @@ -0,0 +1,69 @@
> > > +/*
> > > + * Copyright (c) 2019 NVIDIA Corporation.
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person obtaining
> > > a
> > > + * copy of this software and associated documentation files (the
> > > "Software"),
> > > + * to deal in the Software without restriction, including without
> > > limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute,
> > > sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > + * Software is furnished to do so, subject to the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice shall be
> > > included in
> > > + * all copies or substantial portions of the Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > > EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > > MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> > > SHALL
> > > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES
> > > OR
> > > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > > + * OTHER DEALINGS IN THE SOFTWARE.
> > > + *
> > > + * Authors: Thierry Reding
> > > + */
> > > +
> > > +#include "priv.h"
> > > +
> > > +static void
> > > +gp10b_ltc_init(struct nvkm_ltc *ltc)
> > > +{
> > > + struct nvkm_device *device = ltc->subdev.device;
> > > +#ifdef CONFIG_IOMMU_API
> > > + struct iommu_fwspec *spec;
> > > +#endif
> > > +
> > > + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
> > > + nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
> > > + nvkm_wr32(device, 0x100800, ltc->ltc_nr);
> > > +
> > > +#ifdef CONFIG_IOMMU_API
> > > + spec = dev_iommu_fwspec_get(device->dev);
> > > + if (spec) {
> > > +
Re: [Nouveau] [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote:
> On 16/09/2019 16:04, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > There are extra registers that need to be programmed to make the level 2
> > cache work on GP10B, such as the stream ID register that is used when an
> > SMMU is used to translate memory addresses.
> >
> > Signed-off-by: Thierry Reding
> > ---
> > .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
> > .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
> > .../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild| 1 +
> > .../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 69 +++
> > .../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h| 2 +
> > 5 files changed, 74 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> >
> > diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > index 644d527c3b96..d76f60d7d29a 100644
> > --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
> > @@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct
> > nvkm_ltc **);
> > int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > +int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
> > #endif
> > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > index c3c7159f3411..d2d6d5f4028a 100644
> > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> > @@ -2380,7 +2380,7 @@ nv13b_chipset = {
> > .fuse = gm107_fuse_new,
> > .ibus = gp10b_ibus_new,
> > .imem = gk20a_instmem_new,
> > - .ltc = gp102_ltc_new,
> > + .ltc = gp10b_ltc_new,
> > .mc = gp10b_mc_new,
> > .mmu = gp10b_mmu_new,
> > .secboot = gp10b_secboot_new,
> > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > index 2b6d36ea7067..728d75010847 100644
> > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
> > @@ -6,3 +6,4 @@ nvkm-y += nvkm/subdev/ltc/gm107.o
> > nvkm-y += nvkm/subdev/ltc/gm200.o
> > nvkm-y += nvkm/subdev/ltc/gp100.o
> > nvkm-y += nvkm/subdev/ltc/gp102.o
> > +nvkm-y += nvkm/subdev/ltc/gp10b.o
> > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > new file mode 100644
> > index ..4d27c6ea1552
> > --- /dev/null
> > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
> > @@ -0,0 +1,69 @@
> > +/*
> > + * Copyright (c) 2019 NVIDIA Corporation.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included
> > in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: Thierry Reding
> > + */
> > +
> > +#include "priv.h"
> > +
> > +static void
> > +gp10b_ltc_init(struct nvkm_ltc *ltc)
> > +{
> > + struct nvkm_device *device = ltc->subdev.device;
> > +#ifdef CONFIG_IOMMU_API
> > + struct iommu_fwspec *spec;
> > +#endif
> > +
> > + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
> > + nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
> > + nvkm_wr32(device, 0x100800, ltc->ltc_nr);
> > +
> > +#ifdef CONFIG_IOMMU_API
> > + spec = dev_iommu_fwspec_get(device->dev);
> > + if (spec) {
> > + u32 sid = spec->ids[0] & 0x;
> > +
> > + /* stream ID */
> > + nvkm_wr32(device, 0x16, sid << 2);
> > + }
> > +#endif
>
> Could we get rid of the #ifdef blocks here if there was a NULL
> inline version of dev_iommu_fwspec_get() in the include/linux/iommu.h
> header? The compiler should then
Re: [Nouveau] [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached
Hi Thierry,
On 16/09/2019 16:04, Thierry Reding wrote:
From: Thierry Reding
If the GPU is already attached to an IOMMU, don't detach it and setup an
explicit IOMMU domain. Since Nouveau can now properly handle the case of
the DMA API being backed by an IOMMU, just continue using the DMA API.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/nvkm/engine/device/tegra.c| 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index d0d52c1d4aee..fc652aaa41c7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -23,10 +23,6 @@
#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
#include "priv.h"
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
-#include
-#endif
-
static int
nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
{
@@ -109,14 +105,13 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra
*tdev)
unsigned long pgsize_bitmap;
int ret;
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
- if (dev->archdata.mapping) {
- struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
-
- arm_iommu_detach_device(dev);
- arm_iommu_release_mapping(mapping);
- }
-#endif
+ /*
+* Skip explicit IOMMU initialization if the GPU is already attached
+* to an IOMMU domain. This can happen if the DMA API is backed by an
+* IOMMU.
+*/
+ if (iommu_get_domain_for_dev(dev))
+ return;
Beware of "iommu.passthrough=1" - you could get a valid default domain
here yet still have direct/SWIOTLB DMA ops. I guess you probably want to
double-check the domain type as well.
Robin.
if (!tdev->func->iommu_bit)
return;
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[Nouveau] [PATCH 0/6] drm/nouveau: Preparatory work for GV11B support
From: Thierry Reding Hi Ben, these are a couple of patches that are in preparation for adding GV11B support. The fundamental issue that these are trying to solve is that the GV11B is the first Tegra incarnation of the GPU where the aperture really matters. All prior generations would accept any of them. For dGPUs we usually allocate memory in VRAM, so the default aperture (0) is correct. However, on Tegra the buffers are allocated in system memory, and since the GPU actually cares about the aperture, we need to ensure that the aperture field is written in all the necessary places. This series of patches does three things: the first two patches make it easier to debug aperture related faults by actually reading the aperture information from the fault information registers. The second patch is actually only a small cleanup. Patches 3-5 unify the aperture values. All generations have the same definitions for these, so there's little use in separating them out into callbacks. Finally, patch 6 writes the aperture field in the places where required. I've used these patches to test my initial support for GV11B. This is enough to get me through the driver probe without any faults, but I have not made much progress on secboot support yet, so I can't use the GV11B to do anything very interesting yet. I should also note that this is completely untested on dGPU because I don't currently have a way of testing them. I'm working on that, but in the meantime it'd be great if somebody could give this set a quick spin on a dGPU to confirm that these don't break. Thierry Thierry Reding (6): drm/nouveau: fault: Store aperture in fault information drm/nouveau: fault: Widen engine field drm/nouveau: Remove bogus gk20a aperture callback drm/nouveau: Implement nvkm_memory_aperture() drm/nouveau: Remove unused nvkm_vmm_func->aper() implementations drm/nouveau: Program aperture field where necessary .../drm/nouveau/include/nvkm/core/memory.h| 28 +++ .../drm/nouveau/include/nvkm/subdev/fault.h | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 3 +- .../nouveau/nvkm/engine/fifo/gpfifogk104.c| 7 +++-- .../nouveau/nvkm/engine/fifo/gpfifogv100.c| 5 ++-- .../gpu/drm/nouveau/nvkm/engine/fifo/gv100.c | 7 - .../gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 3 +- .../gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 3 -- .../drm/nouveau/nvkm/subdev/mmu/vmmgf100.c| 21 ++ .../drm/nouveau/nvkm/subdev/mmu/vmmgk104.c| 2 -- .../drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c| 12 .../drm/nouveau/nvkm/subdev/mmu/vmmgm200.c| 2 -- .../drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c| 2 -- .../drm/nouveau/nvkm/subdev/mmu/vmmgp100.c| 8 ++ .../drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c| 1 - .../drm/nouveau/nvkm/subdev/mmu/vmmgv100.c| 1 - .../drm/nouveau/nvkm/subdev/mmu/vmmtu102.c| 1 - 18 files changed, 55 insertions(+), 55 deletions(-) -- 2.23.0 ___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 6/6] drm/nouveau: Program aperture field where necessary
From: Thierry Reding
Some registers and instance block entries need the aperture to be
programmed correctly. This is important on recent Tegra GPUs where
the GPU actually checks the value of this field and faults if an
invalid aperture is programmed.
For example GV11B no longer supports VRAM and all memory is already
allocated from system (coherent or non-coherent), so make sure to
also program the right aperture.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 7 +--
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c | 5 +++--
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c | 7 ++-
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c| 3 ++-
4 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
index 728a1edbf98c..843ebb41dbc6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
@@ -201,6 +201,7 @@ gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
void
gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
{
+ u32 aperture = nvkm_memory_aperture(base->inst->memory) << 28;
struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
struct gk104_fifo *fifo = chan->fifo;
struct nvkm_device *device = fifo->base.engine.subdev.device;
@@ -208,7 +209,7 @@ gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
u32 coff = chan->base.chid * 8;
nvkm_mask(device, 0x84 + coff, 0x000f, chan->runl << 16);
- nvkm_wr32(device, 0x80 + coff, 0x8000 | addr);
+ nvkm_wr32(device, 0x80 + coff, 0x8000 | aperture | addr);
if (list_empty(>head) && !chan->killed) {
gk104_fifo_runlist_insert(fifo, chan);
@@ -250,6 +251,7 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64
*runlists, u16 *chid,
unsigned long engm;
u64 subdevs = 0;
u64 usermem;
+ u32 target;
if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
return -EINVAL;
@@ -303,10 +305,11 @@ gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64
*runlists, u16 *chid,
nvkm_wo32(fifo->user.mem, usermem + i, 0x);
nvkm_done(fifo->user.mem);
usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
+ target = nvkm_memory_aperture(fifo->user.mem);
/* RAMFC */
nvkm_kmap(chan->base.inst);
- nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
+ nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem) | target);
nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
nvkm_wo32(chan->base.inst, 0x10, 0xface);
nvkm_wo32(chan->base.inst, 0x30, 0xf902);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
index a7462cf59d65..97d084ffcfd5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
@@ -132,7 +132,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func
*func,
unsigned long engm;
u64 subdevs = 0;
u64 usermem, mthd;
- u32 size;
+ u32 size, target;
if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
return -EINVAL;
@@ -183,6 +183,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func
*func,
nvkm_wo32(fifo->user.mem, usermem + i, 0x);
nvkm_done(fifo->user.mem);
usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
+ target = nvkm_memory_target(fifo->user.mem);
/* Allocate fault method buffer (magics come from nvgpu). */
size = nvkm_rd32(device, 0x104028); /* NV_PCE_PCE_MAP */
@@ -200,7 +201,7 @@ gv100_fifo_gpfifo_new_(const struct nvkm_fifo_chan_func
*func,
/* RAMFC */
nvkm_kmap(chan->base.inst);
- nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
+ nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem) | target);
nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem));
nvkm_wo32(chan->base.inst, 0x010, 0xface);
nvkm_wo32(chan->base.inst, 0x030, 0x7902);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
index 6ee1bb32a071..449f669f43b0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
@@ -32,11 +32,16 @@ void
gv100_fifo_runlist_chan(struct gk104_fifo_chan *chan,
struct nvkm_memory *memory, u32 offset)
{
+ struct nvkm_memory *instmem = chan->base.inst->memory;
struct nvkm_memory *usermem = chan->fifo->user.mem;
const u64 user = nvkm_memory_addr(usermem) + (chan->base.chid * 0x200);
const u64 inst =
[Nouveau] [PATCH 5/6] drm/nouveau: Remove unused nvkm_vmm_func->aper() implementations
From: Thierry Reding
These implementations are now all unused. Remove them.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 2 --
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c | 14 --
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c | 2 --
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c | 2 --
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c | 2 --
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c | 2 --
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 1 -
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c | 1 -
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c | 1 -
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c | 1 -
10 files changed, 28 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
index 9862f44ac8b5..767870c2d24c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
@@ -140,7 +140,6 @@ struct nvkm_vmm_func {
int (*join)(struct nvkm_vmm *, struct nvkm_memory *inst);
void (*part)(struct nvkm_vmm *, struct nvkm_memory *inst);
- int (*aper)(enum nvkm_memory_target);
int (*valid)(struct nvkm_vmm *, void *argv, u32 argc,
struct nvkm_vmm_map *);
void (*flush)(struct nvkm_vmm *, int depth);
@@ -206,7 +205,6 @@ int gf100_vmm_new_(const struct nvkm_vmm_func *, const
struct nvkm_vmm_func *,
int gf100_vmm_join_(struct nvkm_vmm *, struct nvkm_memory *, u64 base);
int gf100_vmm_join(struct nvkm_vmm *, struct nvkm_memory *);
void gf100_vmm_part(struct nvkm_vmm *, struct nvkm_memory *);
-int gf100_vmm_aper(enum nvkm_memory_target);
int gf100_vmm_valid(struct nvkm_vmm *, void *, u32, struct nvkm_vmm_map *);
void gf100_vmm_flush(struct nvkm_vmm *, int);
void gf100_vmm_invalidate(struct nvkm_vmm *, u32 type);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
index ffa64c0d3eda..ccf5a92d7b54 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
@@ -318,18 +318,6 @@ gf100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
return 0;
}
-int
-gf100_vmm_aper(enum nvkm_memory_target target)
-{
- switch (target) {
- case NVKM_MEM_TARGET_VRAM: return 0;
- case NVKM_MEM_TARGET_HOST: return 2;
- case NVKM_MEM_TARGET_NCOH: return 3;
- default:
- return -EINVAL;
- }
-}
-
void
gf100_vmm_part(struct nvkm_vmm *vmm, struct nvkm_memory *inst)
{
@@ -370,7 +358,6 @@ static const struct nvkm_vmm_func
gf100_vmm_17 = {
.join = gf100_vmm_join,
.part = gf100_vmm_part,
- .aper = gf100_vmm_aper,
.valid = gf100_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
@@ -385,7 +372,6 @@ static const struct nvkm_vmm_func
gf100_vmm_16 = {
.join = gf100_vmm_join,
.part = gf100_vmm_part,
- .aper = gf100_vmm_aper,
.valid = gf100_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c
index 0b59c01fd146..8efd147fa930 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c
@@ -68,7 +68,6 @@ static const struct nvkm_vmm_func
gk104_vmm_17 = {
.join = gf100_vmm_join,
.part = gf100_vmm_part,
- .aper = gf100_vmm_aper,
.valid = gf100_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
@@ -83,7 +82,6 @@ static const struct nvkm_vmm_func
gk104_vmm_16 = {
.join = gf100_vmm_join,
.part = gf100_vmm_part,
- .aper = gf100_vmm_aper,
.valid = gf100_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
index 999b953505b3..774b6fe9d4a9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
@@ -45,7 +45,6 @@ static const struct nvkm_vmm_func
gk20a_vmm_17 = {
.join = gf100_vmm_join,
.part = gf100_vmm_part,
- .aper = gf100_vmm_aper,
.valid = gk20a_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
@@ -60,7 +59,6 @@ static const struct nvkm_vmm_func
gk20a_vmm_16 = {
.join = gf100_vmm_join,
.part = gf100_vmm_part,
- .aper = gf100_vmm_aper,
.valid = gk20a_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c
[Nouveau] [PATCH 4/6] drm/nouveau: Implement nvkm_memory_aperture()
From: Thierry Reding
The aperture of a buffer is always specific to where its memory was
allocated from. Furthermore, the encoding of the aperture is always
the same, regardless of GPU generation.
Implement the memory target to aperture conversion in one central
place and make the aperture independent of the VMM.
Note that we no longer return a negative error code for unsupported
apertures. First, this should never happen to begin with and is a
programming error, which is why we have a WARN already. Second, the
standard aperture (0, VRAM) should be correct for the vast majority
of memory objects. Lastly, the aperture also needs to be programmed
into many registers and instance blocks. Having to check for error
codes at every step of the way would make this very unwieldy. If in
any case there is ever a problem with the aperture being wrong, let
us rely on the WARN to tell us about it.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/include/nvkm/core/memory.h| 28 +++
.../drm/nouveau/nvkm/subdev/mmu/vmmgf100.c| 7 ++---
.../drm/nouveau/nvkm/subdev/mmu/vmmgp100.c| 7 ++---
3 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
index b23bf6109f2d..29c60fbed167 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
@@ -64,6 +64,34 @@ void nvkm_memory_tags_put(struct nvkm_memory *, struct
nvkm_device *,
#define nvkm_memory_map(p,o,vm,va,av,ac)
\
(p)->func->map((p),(o),(vm),(va),(av),(ac))
+static inline u32
+nvkm_memory_aperture(struct nvkm_memory *mem)
+{
+ enum nvkm_memory_target target = nvkm_memory_target(mem);
+
+ switch (target) {
+ case NVKM_MEM_TARGET_VRAM:
+ return 0;
+
+ case NVKM_MEM_TARGET_HOST:
+ return 2;
+
+ case NVKM_MEM_TARGET_NCOH:
+ return 3;
+
+ default:
+ break;
+ }
+
+ /*
+* This is invalid, so warn about this loudly. However, return 0 to
+* avoid writing garbage into registers. 0 is the VRAM aperture and
+* might still work in most cases.
+*/
+ WARN(1, "invalid memory target: %d\n", target);
+ return 0;
+}
+
/* accessor macros - kmap()/done() must bracket use of the other accessor
* macros to guarantee correct behaviour across all chipsets
*/
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
index ab6424faf84c..ffa64c0d3eda 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c
@@ -248,8 +248,9 @@ gf100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
struct nvkm_device *device = vmm->mmu->subdev.device;
struct nvkm_memory *memory = map->memory;
u8 kind, priv, ro, vol;
- int kindn, aper, ret = -ENOSYS;
+ int kindn, ret = -ENOSYS;
const u8 *kindm;
+ u32 aper;
map->next = (1 << page->shift) >> 8;
map->type = map->ctag = 0;
@@ -270,9 +271,7 @@ gf100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
return ret;
}
- aper = vmm->func->aper(target);
- if (WARN_ON(aper < 0))
- return aper;
+ aper = nvkm_memory_aperture(map->memory);
kindm = vmm->mmu->func->kind(vmm->mmu, );
if (kind >= kindn || kindm[kind] == 0xff) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
index b4f519768d5e..4a1a658328e5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
@@ -321,8 +321,9 @@ gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
struct nvkm_device *device = vmm->mmu->subdev.device;
struct nvkm_memory *memory = map->memory;
u8 kind, priv, ro, vol;
- int kindn, aper, ret = -ENOSYS;
+ int kindn, ret = -ENOSYS;
const u8 *kindm;
+ u32 aper;
map->next = (1ULL << page->shift) >> 4;
map->type = 0;
@@ -343,9 +344,7 @@ gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
return ret;
}
- aper = vmm->func->aper(target);
- if (WARN_ON(aper < 0))
- return aper;
+ aper = nvkm_memory_aperture(map->memory);
kindm = vmm->mmu->func->kind(vmm->mmu, );
if (kind >= kindn || kindm[kind] == 0xff) {
--
2.23.0
___
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https://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 1/6] drm/nouveau: fault: Store aperture in fault information
From: Thierry Reding
The fault information register contains data about the aperture that
caused the failure. This can be useful in debugging aperture related
programming bugs.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h | 1 +
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c| 3 ++-
drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
index 97322f95b3ee..1cc862bc1122 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h
@@ -21,6 +21,7 @@ struct nvkm_fault_data {
u64 addr;
u64 inst;
u64 time;
+ u8 aperture;
u8 engine;
u8 valid;
u8gpc;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index 5d4b695cab8e..81cbe1cc4804 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -519,9 +519,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct
nvkm_fault_data *info)
chan = nvkm_fifo_chan_inst_locked(>base, info->inst);
nvkm_error(subdev,
- "fault %02x [%s] at %016llx engine %02x [%s] client %02x "
+ "fault %02x [%s] at %016llx aperture %02x engine %02x [%s]
client %02x "
"[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n",
info->access, ea ? ea->name : "", info->addr,
+ info->aperture,
info->engine, ee ? ee->name : en,
info->client, ct, ec ? ec->name : "",
info->reason, er ? er->name : "", chan ? chan->chid : -1,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
index 6747f09c2dc3..b5e32295237b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c
@@ -138,6 +138,7 @@ gv100_fault_intr_fault(struct nvkm_fault *fault)
info.inst = ((u64)insthi << 32) | (info0 & 0xf000);
info.time = 0;
info.engine = (info0 & 0x00ff);
+ info.aperture = (info0 & 0x0c00) >> 10;
info.valid = (info1 & 0x8000) >> 31;
info.gpc= (info1 & 0x1f00) >> 24;
info.hub= (info1 & 0x0010) >> 20;
--
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[Nouveau] [PATCH 3/6] drm/nouveau: Remove bogus gk20a aperture callback
From: Thierry Reding
The gk20a (as well as all subsequent Tegra instantiations of the GPU) do
in fact use the same apertures as regular GPUs. Prior to gv11b there are
no checks in hardware for the aperture, so we get away with setting VRAM
as the aperture for buffers that are actually in system memory.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 1 -
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c | 10 --
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c | 4 ++--
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c | 2 +-
4 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
index fb3a9e8bb9cd..9862f44ac8b5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
@@ -212,7 +212,6 @@ void gf100_vmm_flush(struct nvkm_vmm *, int);
void gf100_vmm_invalidate(struct nvkm_vmm *, u32 type);
void gf100_vmm_invalidate_pdb(struct nvkm_vmm *, u64 addr);
-int gk20a_vmm_aper(enum nvkm_memory_target);
int gk20a_vmm_valid(struct nvkm_vmm *, void *, u32, struct nvkm_vmm_map *);
int gm200_vmm_new_(const struct nvkm_vmm_func *, const struct nvkm_vmm_func *,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
index 16d7bf727292..999b953505b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c
@@ -25,16 +25,6 @@
#include
-int
-gk20a_vmm_aper(enum nvkm_memory_target target)
-{
- switch (target) {
- case NVKM_MEM_TARGET_NCOH: return 0;
- default:
- return -EINVAL;
- }
-}
-
int
gk20a_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 argc,
struct nvkm_vmm_map *map)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
index 7a6066d886cd..f5d7819c4a40 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c
@@ -25,7 +25,7 @@ static const struct nvkm_vmm_func
gm20b_vmm_17 = {
.join = gm200_vmm_join,
.part = gf100_vmm_part,
- .aper = gk20a_vmm_aper,
+ .aper = gf100_vmm_aper,
.valid = gk20a_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
@@ -41,7 +41,7 @@ static const struct nvkm_vmm_func
gm20b_vmm_16 = {
.join = gm200_vmm_join,
.part = gf100_vmm_part,
- .aper = gk20a_vmm_aper,
+ .aper = gf100_vmm_aper,
.valid = gk20a_vmm_valid,
.flush = gf100_vmm_flush,
.invalidate_pdb = gf100_vmm_invalidate_pdb,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
index 180c8f006e32..ffe84ea2f7d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c
@@ -43,7 +43,7 @@ static const struct nvkm_vmm_func
gp10b_vmm = {
.join = gp100_vmm_join,
.part = gf100_vmm_part,
- .aper = gk20a_vmm_aper,
+ .aper = gf100_vmm_aper,
.valid = gp10b_vmm_valid,
.flush = gp100_vmm_flush,
.mthd = gp100_vmm_mthd,
--
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[Nouveau] [PATCH 2/6] drm/nouveau: fault: Widen engine field
From: Thierry Reding The engine field in the FIFO fault information registers is actually 9 bits wide. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c index b5e32295237b..28306c5f6651 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c @@ -137,8 +137,8 @@ gv100_fault_intr_fault(struct nvkm_fault *fault) info.addr = ((u64)addrhi << 32) | addrlo; info.inst = ((u64)insthi << 32) | (info0 & 0xf000); info.time = 0; - info.engine = (info0 & 0x00ff); info.aperture = (info0 & 0x0c00) >> 10; + info.engine = (info0 & 0x01ff); info.valid = (info1 & 0x8000) >> 31; info.gpc= (info1 & 0x1f00) >> 24; info.hub= (info1 & 0x0010) >> 20; -- 2.23.0 ___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 11/11] arm64: tegra: Enable SMMU for GPU on Tegra186
From: Thierry Reding
The GPU has a connection to the ARM SMMU found on Tegra186, which can be
used to support large pages. Make sure the GPU is attached to the SMMU
to take advantage of its capabilities.
Signed-off-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 47cd831fcf44..171fd4dfa58d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1172,6 +1172,7 @@
status = "disabled";
power-domains = < TEGRA186_POWER_DOMAIN_GPU>;
+ iommus = < TEGRA186_SID_GPU>;
};
sysram@3000 {
--
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[Nouveau] [PATCH 10/11] arm64: tegra: Enable GPU on Jetson TX2
From: Alexandre Courbot
Enable the GPU node for the Jetson TX2 board.
Signed-off-by: Alexandre Courbot
Signed-off-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts
b/arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts
index bdace01561ba..6f7c7c4c5c29 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts
@@ -276,6 +276,10 @@
};
};
+ gpu@1700 {
+ status = "okay";
+ };
+
gpio-keys {
compatible = "gpio-keys";
--
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[Nouveau] [PATCH 07/11] drm/nouveau: gk20a: Implement custom MMU class
From: Thierry Reding
The GPU integrated in NVIDIA Tegra SoCs is connected to system memory
via two paths: one direct path to the memory controller and another path
that goes through a system MMU first. It's not typically necessary to go
through the system MMU because the GPU's MMU can already map buffers so
that they appear contiguous to the GPU.
However, in order to support big pages, the system MMU has to be used to
combine multiple small pages into one virtually contiguous chunk so that
the GPU can then treat that as a single big page.
In order to prepare for big page support, implement a custom MMU class
that takes care of setting the IOMMU bit when writing page tables and
when appropriate.
This is also necessary to make sure that Nouveau works correctly on
Tegra devices where the GPU is connected to a system MMU and that IOMMU
is used to back the DMA API. Currently Nouveau assumes that the DMA API
is never backed by an IOMMU, so access to DMA-mapped buffers fault when
suddenly this assumption is no longer true.
One situation where this can happen is on 32-bit Tegra SoCs where the
ARM architecture code automatically attaches the GPU with a DMA/IOMMU
domain. This is currently worked around by detaching the GPU from the
IOMMU domain at probe time. However, with Tegra186 and later this can
now also happen, but unfortunately no mechanism exists to detach from
the domain in the 64-bit ARM architecture code.
Using this Tegra-specific MMU class ensures that DMA-mapped buffers are
properly mapped (with the IOMMU bit set) if the DMA API is backed by an
IOMMU domain.
Signed-off-by: Thierry Reding
---
.../gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c | 50 ++-
.../gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.h | 44
.../gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.c | 6 ++-
.../gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c | 4 +-
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 1 +
.../drm/nouveau/nvkm/subdev/mmu/vmmgk20a.c| 22 +++-
.../drm/nouveau/nvkm/subdev/mmu/vmmgm20b.c| 4 +-
.../drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c| 20 +++-
8 files changed, 142 insertions(+), 9 deletions(-)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c
index ac74965a60d4..d9a5e05b7dc7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.c
@@ -19,11 +19,59 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
+
+#include "gk20a.h"
#include "mem.h"
#include "vmm.h"
+#include
#include
+static void
+gk20a_mmu_ctor(const struct nvkm_mmu_func *func, struct nvkm_device *device,
+ int index, struct gk20a_mmu *mmu)
+{
+ struct iommu_domain *domain = iommu_get_domain_for_dev(device->dev);
+ struct nvkm_device_tegra *tegra = device->func->tegra(device);
+
+ nvkm_mmu_ctor(func, device, index, >base);
+
+ /*
+* If the DMA API is backed by an IOMMU, make sure the IOMMU bit is
+* set for all buffer accesses. If the IOMMU is explicitly used, it
+* is only used for instance blocks and the MMU doesn't care, since
+* buffer objects are only mapped through the MMU, not through the
+* IOMMU.
+*
+* Big page support could be implemented using explicit IOMMU usage,
+* but the DMA API already provides that for free, so we don't worry
+* about it for now.
+*/
+ if (domain && !tegra->iommu.domain) {
+ mmu->iommu_mask = BIT_ULL(tegra->func->iommu_bit);
+ nvkm_debug(>base.subdev, "IOMMU mask: %llx\n",
+ mmu->iommu_mask);
+ }
+}
+
+int
+gk20a_mmu_new_(const struct nvkm_mmu_func *func, struct nvkm_device *device,
+ int index, struct nvkm_mmu **pmmu)
+{
+ struct gk20a_mmu *mmu;
+
+ mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
+ if (!mmu)
+ return -ENOMEM;
+
+ gk20a_mmu_ctor(func, device, index, mmu);
+
+ if (pmmu)
+ *pmmu = >base;
+
+ return 0;
+}
+
static const struct nvkm_mmu_func
gk20a_mmu = {
.dma_bits = 40,
@@ -37,5 +85,5 @@ gk20a_mmu = {
int
gk20a_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
{
- return nvkm_mmu_new_(_mmu, device, index, pmmu);
+ return gk20a_mmu_new_(_mmu, device, index, pmmu);
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.h
b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.h
new file mode 100644
index ..bb81fc62509c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2019 NVIDIA Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+
[Nouveau] [PATCH 09/11] drm/nouveau: tegra: Fall back to 32-bit DMA mask without IOMMU
From: Thierry Reding
The GPU can usually address more than 32-bit, even without being
attached to an IOMMU. However, if the GPU is not attached to an IOMMU,
it's likely that there is no IOMMU in the system, in which case any
buffers allocated by Nouveau will likely end up in a region of memory
that cannot be accessed by host1x.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/nvkm/engine/device/tegra.c| 111 +++---
1 file changed, 70 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index fc652aaa41c7..221238a2cf53 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -97,7 +97,7 @@ nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
return 0;
}
-static void
+static int
nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev)
{
#if IS_ENABLED(CONFIG_IOMMU_API)
@@ -111,47 +111,65 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra
*tdev)
* IOMMU.
*/
if (iommu_get_domain_for_dev(dev))
- return;
+ return -ENODEV;
if (!tdev->func->iommu_bit)
- return;
+ return -ENODEV;
+
+ if (!iommu_present(_bus_type))
+ return -ENODEV;
mutex_init(>iommu.mutex);
- if (iommu_present(_bus_type)) {
- tdev->iommu.domain = iommu_domain_alloc(_bus_type);
- if (!tdev->iommu.domain)
- goto error;
+ tdev->iommu.domain = iommu_domain_alloc(_bus_type);
+ if (!tdev->iommu.domain)
+ return -ENOMEM;
- /*
-* A IOMMU is only usable if it supports page sizes smaller
-* or equal to the system's PAGE_SIZE, with a preference if
-* both are equal.
-*/
- pgsize_bitmap = tdev->iommu.domain->ops->pgsize_bitmap;
- if (pgsize_bitmap & PAGE_SIZE) {
- tdev->iommu.pgshift = PAGE_SHIFT;
- } else {
- tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
- if (tdev->iommu.pgshift == 0) {
- dev_warn(dev, "unsupported IOMMU page size\n");
- goto free_domain;
- }
- tdev->iommu.pgshift -= 1;
+ /*
+* An IOMMU is only usable if it supports page sizes smaller or equal
+* to the system's PAGE_SIZE, with a preference if both are equal.
+*/
+ pgsize_bitmap = tdev->iommu.domain->ops->pgsize_bitmap;
+ if (pgsize_bitmap & PAGE_SIZE) {
+ tdev->iommu.pgshift = PAGE_SHIFT;
+ } else {
+ tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
+ if (tdev->iommu.pgshift == 0) {
+ dev_warn(dev, "unsupported IOMMU page size\n");
+ ret = -ENOTSUPP;
+ goto free_domain;
}
- ret = iommu_attach_device(tdev->iommu.domain, dev);
- if (ret)
- goto free_domain;
+ tdev->iommu.pgshift -= 1;
+ }
- ret = nvkm_mm_init(>iommu.mm, 0, 0,
- (1ULL << tdev->func->iommu_bit) >>
- tdev->iommu.pgshift, 1);
- if (ret)
- goto detach_device;
+ ret = iommu_attach_device(tdev->iommu.domain, dev);
+ if (ret) {
+ dev_warn(dev, "failed to attach to IOMMU: %d\n", ret);
+ goto free_domain;
+ }
+
+ ret = nvkm_mm_init(>iommu.mm, 0, 0,
+ (1ULL << tdev->func->iommu_bit) >>
+ tdev->iommu.pgshift, 1);
+ if (ret) {
+ dev_warn(dev, "failed to initialize IOVA space: %d\n", ret);
+ goto detach_device;
+ }
+
+ /*
+* The IOMMU bit defines the upper limit of the GPU-addressable space.
+*/
+ ret = dma_set_mask(dev, DMA_BIT_MASK(tdev->func->iommu_bit));
+ if (ret) {
+ dev_warn(dev, "failed to set DMA mask: %d\n", ret);
+ goto fini_mm;
}
- return;
+ return 0;
+
+fini_mm:
+ nvkm_mm_fini(>iommu.mm);
detach_device:
iommu_detach_device(tdev->iommu.domain, dev);
@@ -159,10 +177,15 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra
*tdev)
free_domain:
iommu_domain_free(tdev->iommu.domain);
-error:
+ /* reset these so that the DMA API code paths are executed */
tdev->iommu.domain = NULL;
tdev->iommu.pgshift = 0;
- dev_err(dev, "cannot initialize IOMMU MM\n");
+
+ dev_warn(dev, "cannot initialize IOMMU MM\n");
+
+ return ret;
+#else
+ return -ENOTSUPP;
#endif
}
[Nouveau] [PATCH 05/11] drm/nouveau: gp10b: Use correct copy engine
From: Thierry Reding
gp10b uses the new engine enumeration mechanism introduced in the Pascal
architecture. As a result, the copy engine, which used to be at index 2
for prior Tegra GPU instantiations, has now moved to index 0. Fix up the
index and also use the gp100 variant of the copy engine class because on
gp10b the PASCAL_DMA_COPY_B class is not supported.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index d2d6d5f4028a..99d3fa3fad89 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -2387,7 +2387,7 @@ nv13b_chipset = {
.pmu = gm20b_pmu_new,
.timer = gk20a_timer_new,
.top = gk104_top_new,
- .ce[2] = gp102_ce_new,
+ .ce[0] = gp100_ce_new,
.dma = gf119_dma_new,
.fifo = gp10b_fifo_new,
.gr = gp10b_gr_new,
--
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[Nouveau] [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
From: Thierry Reding
There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.
Signed-off-by: Thierry Reding
---
.../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
.../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild| 1 +
.../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 69 +++
.../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h| 2 +
5 files changed, 74 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
index 644d527c3b96..d76f60d7d29a 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
@@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc
**);
int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
+int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index c3c7159f3411..d2d6d5f4028a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -2380,7 +2380,7 @@ nv13b_chipset = {
.fuse = gm107_fuse_new,
.ibus = gp10b_ibus_new,
.imem = gk20a_instmem_new,
- .ltc = gp102_ltc_new,
+ .ltc = gp10b_ltc_new,
.mc = gp10b_mc_new,
.mmu = gp10b_mmu_new,
.secboot = gp10b_secboot_new,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
index 2b6d36ea7067..728d75010847 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
@@ -6,3 +6,4 @@ nvkm-y += nvkm/subdev/ltc/gm107.o
nvkm-y += nvkm/subdev/ltc/gm200.o
nvkm-y += nvkm/subdev/ltc/gp100.o
nvkm-y += nvkm/subdev/ltc/gp102.o
+nvkm-y += nvkm/subdev/ltc/gp10b.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
new file mode 100644
index ..4d27c6ea1552
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2019 NVIDIA Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Thierry Reding
+ */
+
+#include "priv.h"
+
+static void
+gp10b_ltc_init(struct nvkm_ltc *ltc)
+{
+ struct nvkm_device *device = ltc->subdev.device;
+#ifdef CONFIG_IOMMU_API
+ struct iommu_fwspec *spec;
+#endif
+
+ nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
+ nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
+ nvkm_wr32(device, 0x100800, ltc->ltc_nr);
+
+#ifdef CONFIG_IOMMU_API
+ spec = dev_iommu_fwspec_get(device->dev);
+ if (spec) {
+ u32 sid = spec->ids[0] & 0x;
+
+ /* stream ID */
+ nvkm_wr32(device, 0x16, sid << 2);
+ }
+#endif
+}
+
+static const struct nvkm_ltc_func
+gp10b_ltc = {
+ .oneinit = gp100_ltc_oneinit,
+ .init = gp10b_ltc_init,
+ .intr = gp100_ltc_intr,
+ .cbc_clear = gm107_ltc_cbc_clear,
+ .cbc_wait = gm107_ltc_cbc_wait,
+ .zbc = 16,
+ .zbc_clear_color = gm107_ltc_zbc_clear_color,
+ .zbc_clear_depth = gm107_ltc_zbc_clear_depth,
+ .zbc_clear_stencil = gp102_ltc_zbc_clear_stencil,
+ .invalidate = gf100_ltc_invalidate,
+ .flush = gf100_ltc_flush,
+};
+
+int
+gp10b_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
+{
+ return nvkm_ltc_new_(_ltc, device, index, pltc);
+}
diff
[Nouveau] [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached
From: Thierry Reding
If the GPU is already attached to an IOMMU, don't detach it and setup an
explicit IOMMU domain. Since Nouveau can now properly handle the case of
the DMA API being backed by an IOMMU, just continue using the DMA API.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/nvkm/engine/device/tegra.c| 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index d0d52c1d4aee..fc652aaa41c7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -23,10 +23,6 @@
#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
#include "priv.h"
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
-#include
-#endif
-
static int
nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
{
@@ -109,14 +105,13 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra
*tdev)
unsigned long pgsize_bitmap;
int ret;
-#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
- if (dev->archdata.mapping) {
- struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
-
- arm_iommu_detach_device(dev);
- arm_iommu_release_mapping(mapping);
- }
-#endif
+ /*
+* Skip explicit IOMMU initialization if the GPU is already attached
+* to an IOMMU domain. This can happen if the DMA API is backed by an
+* IOMMU.
+*/
+ if (iommu_get_domain_for_dev(dev))
+ return;
if (!tdev->func->iommu_bit)
return;
--
2.23.0
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[Nouveau] [PATCH 06/11] drm/nouveau: gk20a: Set IOMMU bit for DMA API if appropriate
From: Thierry Reding
Detect if the DMA API is backed by an IOMMU and set the IOMMU bit if so.
This is needed to make sure IOMMU addresses are properly translated even
the explicit IOMMU API is not used.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/nvkm/subdev/instmem/gk20a.c | 35 +--
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
index b0493f8df1fe..1120a2a7d5f1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
@@ -100,12 +100,14 @@ struct gk20a_instmem {
unsigned int vaddr_max;
struct list_head vaddr_lru;
+ /* IOMMU mapping */
+ unsigned int page_shift;
+ u64 iommu_mask;
+
/* Only used if IOMMU if present */
struct mutex *mm_mutex;
struct nvkm_mm *mm;
struct iommu_domain *domain;
- unsigned long iommu_pgshift;
- u16 iommu_bit;
/* Only used by DMA API */
unsigned long attrs;
@@ -357,12 +359,12 @@ gk20a_instobj_dtor_iommu(struct nvkm_memory *memory)
mutex_unlock(>lock);
/* clear IOMMU bit to unmap pages */
- r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift);
+ r->offset &= ~imem->iommu_mask;
/* Unmap pages from GPU address space and free them */
for (i = 0; i < node->base.mn->length; i++) {
iommu_unmap(imem->domain,
- (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE);
+ (r->offset + i) << imem->page_shift, PAGE_SIZE);
dma_unmap_page(dev, node->dma_addrs[i], PAGE_SIZE,
DMA_BIDIRECTIONAL);
__free_page(node->pages[i]);
@@ -440,7 +442,7 @@ gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32
npages, u32 align,
/* present memory for being mapped using small pages */
node->r.type = 12;
- node->r.offset = node->handle >> 12;
+ node->r.offset = imem->iommu_mask | node->handle >> 12;
node->r.length = (npages << PAGE_SHIFT) >> 12;
node->base.mn = >r;
@@ -493,7 +495,7 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32
npages, u32 align,
mutex_lock(imem->mm_mutex);
/* Reserve area from GPU address space */
ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages,
- align >> imem->iommu_pgshift, );
+ align >> imem->page_shift, );
mutex_unlock(imem->mm_mutex);
if (ret) {
nvkm_error(subdev, "IOMMU space is full!\n");
@@ -502,7 +504,7 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32
npages, u32 align,
/* Map into GPU address space */
for (i = 0; i < npages; i++) {
- u32 offset = (r->offset + i) << imem->iommu_pgshift;
+ u32 offset = (r->offset + i) << imem->page_shift;
ret = iommu_map(imem->domain, offset, node->dma_addrs[i],
PAGE_SIZE, IOMMU_READ | IOMMU_WRITE);
@@ -518,7 +520,7 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32
npages, u32 align,
}
/* IOMMU bit tells that an address is to be resolved through the IOMMU
*/
- r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift);
+ r->offset |= imem->iommu_mask;
node->base.mn = r;
return 0;
@@ -619,11 +621,12 @@ gk20a_instmem_new(struct nvkm_device *device, int index,
imem->mm_mutex = >iommu.mutex;
imem->mm = >iommu.mm;
imem->domain = tdev->iommu.domain;
- imem->iommu_pgshift = tdev->iommu.pgshift;
- imem->iommu_bit = tdev->func->iommu_bit;
+ imem->page_shift = tdev->iommu.pgshift;
nvkm_info(>base.subdev, "using IOMMU\n");
} else {
+ imem->page_shift = PAGE_SHIFT;
+
imem->attrs = DMA_ATTR_NON_CONSISTENT |
DMA_ATTR_WEAK_ORDERING |
DMA_ATTR_WRITE_COMBINE;
@@ -631,5 +634,17 @@ gk20a_instmem_new(struct nvkm_device *device, int index,
nvkm_info(>base.subdev, "using DMA API\n");
}
+ /*
+* The IOMMU mask needs to be set if an IOMMU is used explicitly (via
+* direct IOMMU API usage) or implicitly (via the DMA API). In both
+* cases the device will have been attached to an IOMMU domain.
+*/
+ if (iommu_get_domain_for_dev(device->dev)) {
+ imem->iommu_mask = BIT_ULL(tdev->func->iommu_bit -
+ imem->page_shift);
+ nvkm_debug(>base.subdev, "IOMMU mask: %016llx\n",
+ imem->iommu_mask);
+ }
+
return 0;
}
--
2.23.0
___
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[Nouveau] [PATCH 02/11] drm/nouveau: tegra: Set clock rate if not set
From: Thierry Reding
If the GPU clock has not had a rate set, initialize it to the maximum
clock rate to make sure it does run.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 747a775121cf..d0d52c1d4aee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -279,6 +279,7 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func
*func,
struct nvkm_device **pdevice)
{
struct nvkm_device_tegra *tdev;
+ unsigned long rate;
int ret;
if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL)))
@@ -307,6 +308,17 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func
*func,
goto free;
}
+ rate = clk_get_rate(tdev->clk);
+ if (rate == 0) {
+ ret = clk_set_rate(tdev->clk, ULONG_MAX);
+ if (ret < 0)
+ goto free;
+
+ rate = clk_get_rate(tdev->clk);
+
+ dev_dbg(>dev, "GPU clock set to %lu\n", rate);
+ }
+
if (func->require_ref_clk)
tdev->clk_ref = devm_clk_get(>dev, "ref");
if (IS_ERR(tdev->clk_ref)) {
--
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[Nouveau] [PATCH 01/11] drm/nouveau: tegra: Avoid pulsing reset twice
From: Thierry Reding
When the GPU powergate is controlled by a generic power domain provider,
the reset will automatically be asserted and deasserted as part of the
power-ungating procedure.
On some Jetson TX2 boards, doing an additional assert and deassert of
the GPU outside of the power-ungate procedure can cause the GPU to go
into a bad state where the memory interface can no longer access system
memory.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 0e372a190d3f..747a775121cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -52,18 +52,18 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
clk_set_rate(tdev->clk_pwr, 20400);
udelay(10);
- reset_control_assert(tdev->rst);
- udelay(10);
-
if (!tdev->pdev->dev.pm_domain) {
+ reset_control_assert(tdev->rst);
+ udelay(10);
+
ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
if (ret)
goto err_clamp;
udelay(10);
- }
- reset_control_deassert(tdev->rst);
- udelay(10);
+ reset_control_deassert(tdev->rst);
+ udelay(10);
+ }
return 0;
--
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[Nouveau] [PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers
From: Thierry Reding
The GPUs found on Tegra SoCs have registers that can be used to read the
WPR configuration. Use these registers instead of reaching into the
memory controller's register space to read the same information.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +-
.../drm/nouveau/nvkm/subdev/secboot/gm20b.c | 81 ---
.../drm/nouveau/nvkm/subdev/secboot/gp10b.c | 4 +-
3 files changed, 53 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
index 62c5e162099a..280b1448df88 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h
@@ -41,6 +41,6 @@ int gm200_secboot_run_blob(struct nvkm_secboot *, struct
nvkm_gpuobj *,
struct nvkm_falcon *);
/* Tegra-only */
-int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32);
+int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
index df8b919dcf09..f8a543122219 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
@@ -23,39 +23,65 @@
#include "acr.h"
#include "gm200.h"
-#define TEGRA210_MC_BASE 0x70019000
-
#ifdef CONFIG_ARCH_TEGRA
-#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
-#define MC_SECURITY_CARVEOUT2_BOM_00xc5c
-#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60
-#define MC_SECURITY_CARVEOUT2_SIZE_128K0xc64
-#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1)
/**
* gm20b_secboot_tegra_read_wpr() - read the WPR registers on Tegra
*
- * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region
- * is reserved from system memory by the bootloader and irreversibly locked.
- * This function reads the address and size of the pre-configured WPR region.
+ * On dGPU, we can manage the WPR region ourselves, but on Tegra this region
+ * is allocated from system memory by the secure firmware. The region is then
+ * marked as a "secure carveout" and irreversibly locked. Furthermore, the WPR
+ * secure carveout is also configured to be sent to the GPU via a dedicated
+ * serial bus between the memory controller and the GPU. The GPU requests this
+ * information upon leaving reset and exposes it through a FIFO register at
+ * offset 0x100cd4.
+ *
+ * The FIFO register's lower 4 bits can be used to set the read index into the
+ * FIFO. After each read of the FIFO register, the read index is incremented.
+ *
+ * Indices 2 and 3 contain the lower and upper addresses of the WPR. These are
+ * stored in units of 256 B. The WPR is inclusive of both addresses.
+ *
+ * Unfortunately, for some reason the WPR info register doesn't contain the
+ * correct values for the secure carveout. It seems like the upper address is
+ * always too small by 128 KiB - 1. Given that the secure carvout size in the
+ * memory controller configuration is specified in units of 128 KiB, it's
+ * possible that the computation of the upper address of the WPR is wrong and
+ * causes this difference.
*/
int
-gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
+gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb)
{
+ struct nvkm_device *device = gsb->base.subdev.device;
struct nvkm_secboot *sb = >base;
- void __iomem *mc;
- u32 cfg;
+ u64 base, limit;
+ u32 value;
- mc = ioremap(mc_base, 0xd00);
- if (!mc) {
- nvkm_error(>subdev, "Cannot map Tegra MC registers\n");
- return -ENOMEM;
- }
- sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
- ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);
- sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K)
- << 17;
- cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0);
- iounmap(mc);
+ /* set WPR info register to point at WPR base address register */
+ value = nvkm_rd32(device, 0x100cd4);
+ value &= ~0xf;
+ value |= 0x2;
+ nvkm_wr32(device, 0x100cd4, value);
+
+ /* read base address */
+ value = nvkm_rd32(device, 0x100cd4);
+ base = (u64)(value >> 4) << 12;
+
+ /* read limit */
+ value = nvkm_rd32(device, 0x100cd4);
+ limit = (u64)(value >> 4) << 12;
+
+ /*
+* The upper address of the WPR seems to be computed wrongly and is
+* actually SZ_128K - 1 bytes lower than it should be. Adjust the
+* value accordingly.
+*/
+ limit += SZ_128K - 1;
+
+ sb->wpr_size = limit - base + 1;
+ sb->wpr_addr = base;
+
+ nvkm_info(>subdev, "WPR: %016llx-%016llx\n", sb->wpr_addr,
+
[Nouveau] [PATCH 2/2] drm/nouveau: tegra: Do not try to disable PCI device
From: Thierry Reding
When Nouveau is instantiated on top of a platform device, the dev->pdev
field will be NULL and calling pci_disable_device() will crash. Move the
PCI disabling code to the PCI specific driver removal code.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 2cd83849600f..b65ae817eabf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -715,7 +715,6 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
void
nouveau_drm_device_remove(struct drm_device *dev)
{
- struct pci_dev *pdev = dev->pdev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_client *client;
struct nvkm_device *device;
@@ -727,7 +726,6 @@ nouveau_drm_device_remove(struct drm_device *dev)
device = nvkm_device_find(client->device);
nouveau_drm_device_fini(dev);
- pci_disable_device(pdev);
drm_dev_put(dev);
nvkm_device_del();
}
@@ -738,6 +736,7 @@ nouveau_drm_remove(struct pci_dev *pdev)
struct drm_device *dev = pci_get_drvdata(pdev);
nouveau_drm_device_remove(dev);
+ pci_disable_device(pdev);
}
static int
--
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[Nouveau] [PATCH 1/2] drm/nouveau: tegra: Fix NULL pointer dereference
From: Thierry Reding
Fill in BAR2 callbacks for instance memory. There's no BAR2 on Tegra
GPUs, but buffers are all in system memory anyway, so just return the
plain address.
Signed-off-by: Thierry Reding
---
.../drm/nouveau/nvkm/subdev/instmem/gk20a.c | 30 +++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
index 985f2990ab0d..b0493f8df1fe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
@@ -261,6 +261,34 @@ gk20a_instobj_release_iommu(struct nvkm_memory *memory)
nvkm_ltc_invalidate(ltc);
}
+static u64
+gk20a_instobj_bar2_dma(struct nvkm_memory *memory)
+{
+ struct gk20a_instobj_dma *iobj = gk20a_instobj_dma(memory);
+ u64 addr = ~0ULL;
+
+ if (gk20a_instobj_acquire_dma(>base.memory))
+ addr = gk20a_instobj_addr(>base.memory);
+
+ gk20a_instobj_release_dma(>base.memory);
+
+ return addr;
+}
+
+static u64
+gk20a_instobj_bar2_iommu(struct nvkm_memory *memory)
+{
+ struct gk20a_instobj_iommu *iobj = gk20a_instobj_iommu(memory);
+ u64 addr = ~0ULL;
+
+ if (gk20a_instobj_acquire_iommu(>base.memory))
+ addr = gk20a_instobj_addr(>base.memory);
+
+ gk20a_instobj_release_iommu(>base.memory);
+
+ return addr;
+}
+
static u32
gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset)
{
@@ -353,6 +381,7 @@ static const struct nvkm_memory_func
gk20a_instobj_func_dma = {
.dtor = gk20a_instobj_dtor_dma,
.target = gk20a_instobj_target,
+ .bar2 = gk20a_instobj_bar2_dma,
.page = gk20a_instobj_page,
.addr = gk20a_instobj_addr,
.size = gk20a_instobj_size,
@@ -365,6 +394,7 @@ static const struct nvkm_memory_func
gk20a_instobj_func_iommu = {
.dtor = gk20a_instobj_dtor_iommu,
.target = gk20a_instobj_target,
+ .bar2 = gk20a_instobj_bar2_iommu,
.page = gk20a_instobj_page,
.addr = gk20a_instobj_addr,
.size = gk20a_instobj_size,
--
2.23.0
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[Nouveau] [PATCH 0/2] drm/nouveau: Two more fixes
From: Thierry Reding Hi Ben, I messed up the ordering of patches in my tree a bit, so these two fixes got separated from the others. I don't consider these particularily urgent because the crash that the first one fixes only happens on gp10b which we don't enable by default yet and the second patch fixes a crash that only happens on module unload (or driver unbind, more accurately), which isn't a terribly common thing to do. I'll be sending out fixes shortly to make the GP10B work more properly on a wider range of Jetson TX2 devices and enable it by default. One thing to mention is that I'm not exactly sure if the first patch is the right thing to do. I haven't seen any issues after that change, but I'm also not exactly sure I understand what BAR2 is used for, so I don't know if I would've even covered those code paths (other than the one causing the crash at probe time) in my tests. It'd be great to get Lyude's feedback on the second patch, since that call to pci_disable_device() was rather oddly placed and I'm not sure if that was essential for things to work or whether the slightly different point in time where it's called after this patch is also okay. It looks to me like it should work fine, but I don't currently have a way to test this on desktop GPUs. Thierry Thierry Reding (2): drm/nouveau: tegra: Fix NULL pointer dereference drm/nouveau: tegra: Do not try to disable PCI device drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +- .../drm/nouveau/nvkm/subdev/instmem/gk20a.c | 30 +++ 2 files changed, 31 insertions(+), 2 deletions(-) -- 2.23.0 ___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 0/4] drm/nouveau: Miscellaneous fixes
From: Thierry Reding Hi Ben, these are fixes for a couple of issues that I've been running into when testing on various Tegra boards. The first two patches fix up issues in the fix that I had sent out earlier to fix the regression introduced in drm-misc-next. The first one is critical because it avoids a BUG_ON as reported by Ilia, while the second is less critical, but restores the locking correctness (at least to the best of my knowledge). Patch 3 is something that I think was also caused by the reservation object rework and is kind of a continuation of my earlier attempt to fix the VMA node sharing breakage. The current ordering between TTM and GEM teardown is causing a DEBUG_LOCKS_WARN_ON() because GEM cleanup already freed a mutex that TTM teardown will still want to use. Lastly, patch 4 is quite uncritical, but it's a one-line change that is causing an ugly (but harmless) external memory address decode error on Tegra210 and later. It seems that for some reason clearing this register will cause a DMA operation to be started by the GPU. I've verified that it's tied to exactly that register write by modifying the value written to the register, and stalling for a couple of seconds after the register write. The address decode error reflects the value written into this register exactly and it always happens a couple of milliseconds after this write. Thierry Thierry Reding (4): drm/nouveau: Fix fallout from reservation object rework drm/nouveau: prime: Extend DMA reservation object lock drm/nouveau: Fix ordering between TTM and GEM release drm/nouveau: gm20b: Avoid BAR1 teardown during init drivers/gpu/drm/nouveau/nouveau_bo.c | 26 +++--- drivers/gpu/drm/nouveau/nouveau_bo.h | 4 +-- drivers/gpu/drm/nouveau/nouveau_gem.c | 7 ++--- drivers/gpu/drm/nouveau/nouveau_prime.c | 27 --- .../gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c | 1 - 5 files changed, 39 insertions(+), 26 deletions(-) -- 2.23.0 ___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 2/4] drm/nouveau: prime: Extend DMA reservation object lock
From: Thierry Reding
Prior to commit 019cbd4a4feb ("drm/nouveau: Initialize GEM object before
TTM object"), the reservation object was locked across all of the buffer
object creation.
After splitting nouveau_bo_new() into separate nouveau_bo_alloc() and
nouveau_bo_init() functions, the reservation object is passed to the
latter, so the lock needs to be held across that function as well.
Fixes: 019cbd4a4feb ("drm/nouveau: Initialize GEM object before TTM object")
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nouveau_prime.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c
b/drivers/gpu/drm/nouveau/nouveau_prime.c
index 656c334ee7d9..bae6a3eccee0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -60,6 +60,7 @@ struct drm_gem_object
*nouveau_gem_prime_import_sg_table(struct drm_device *dev,
struct sg_table *sg)
{
struct nouveau_drm *drm = nouveau_drm(dev);
+ struct drm_gem_object *obj;
struct nouveau_bo *nvbo;
struct dma_resv *robj = attach->dmabuf->resv;
u64 size = attach->dmabuf->size;
@@ -71,9 +72,10 @@ struct drm_gem_object
*nouveau_gem_prime_import_sg_table(struct drm_device *dev,
dma_resv_lock(robj, NULL);
nvbo = nouveau_bo_alloc(>client, , , flags, 0, 0);
- dma_resv_unlock(robj);
- if (IS_ERR(nvbo))
- return ERR_CAST(nvbo);
+ if (IS_ERR(nvbo)) {
+ obj = ERR_CAST(nvbo);
+ goto unlock;
+ }
nvbo->valid_domains = NOUVEAU_GEM_DOMAIN_GART;
@@ -82,16 +84,22 @@ struct drm_gem_object
*nouveau_gem_prime_import_sg_table(struct drm_device *dev,
ret = drm_gem_object_init(dev, >bo.base, size);
if (ret) {
nouveau_bo_ref(NULL, );
- return ERR_PTR(-ENOMEM);
+ obj = ERR_PTR(-ENOMEM);
+ goto unlock;
}
ret = nouveau_bo_init(nvbo, size, align, flags, sg, robj);
if (ret) {
nouveau_bo_ref(NULL, );
- return ERR_PTR(ret);
+ obj = ERR_PTR(ret);
+ goto unlock;
}
- return >bo.base;
+ obj = >bo.base;
+
+unlock:
+ dma_resv_unlock(robj);
+ return obj;
}
int nouveau_gem_prime_pin(struct drm_gem_object *obj)
--
2.23.0
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[Nouveau] [PATCH 3/4] drm/nouveau: Fix ordering between TTM and GEM release
From: Thierry Reding
When the last reference to a TTM BO is dropped, ttm_bo_release() will
acquire the DMA reservation object's wound/wait mutex while trying to
clean up (ttm_bo_cleanup_refs_or_queue() via ttm_bo_release()). It is
therefore essential that drm_gem_object_release() be called after the
TTM BO has been uninitialized, otherwise drm_gem_object_release() has
already destroyed the wound/wait mutex (via dma_resv_fini()).
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 10 --
drivers/gpu/drm/nouveau/nouveau_gem.c | 4
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index e7803dca32c5..f8015e0318d7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -136,10 +136,16 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
struct drm_device *dev = drm->dev;
struct nouveau_bo *nvbo = nouveau_bo(bo);
- if (unlikely(nvbo->bo.base.filp))
- DRM_ERROR("bo %p still attached to GEM object\n", bo);
WARN_ON(nvbo->pin_refcnt > 0);
nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
+
+ /*
+* If nouveau_bo_new() allocated this buffer, the GEM object was never
+* initialized, so don't attempt to release it.
+*/
+ if (bo->base.dev)
+ drm_gem_object_release(>base);
+
kfree(nvbo);
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c
b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 1bdffd714456..1324c19f4e5c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -51,10 +51,6 @@ nouveau_gem_object_del(struct drm_gem_object *gem)
if (gem->import_attach)
drm_prime_gem_destroy(gem, nvbo->bo.sg);
- drm_gem_object_release(gem);
-
- /* reset filp so nouveau_bo_del_ttm() can test for it */
- gem->filp = NULL;
ttm_bo_put(>bo);
pm_runtime_mark_last_busy(dev);
--
2.23.0
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[Nouveau] [PATCH 4/4] drm/nouveau: gm20b: Avoid BAR1 teardown during init
From: Thierry Reding
Writing the 0x1704 (BUS_BAR1_BLOCK) register causes the GPU to probe the
memory region at the programmed address. The result is an address decode
error in the external memory controller because address 0, which is what
is written to the register, is not designated as accessible to devices.
Avoid triggering DMA from the GPU by removing teardown of the BAR1.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c
index 950bff1955ad..1ed6170891c4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.c
@@ -26,7 +26,6 @@ gm20b_bar_func = {
.dtor = gf100_bar_dtor,
.oneinit = gf100_bar_oneinit,
.bar1.init = gf100_bar_bar1_init,
- .bar1.fini = gf100_bar_bar1_fini,
.bar1.wait = gm107_bar_bar1_wait,
.bar1.vmm = gf100_bar_bar1_vmm,
.flush = g84_bar_flush,
--
2.23.0
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[Nouveau] [PATCH 1/4] drm/nouveau: Fix fallout from reservation object rework
From: Thierry Reding
Commit 019cbd4a4feb ("drm/nouveau: Initialize GEM object before TTM
object") introduced a subtle change in how the buffer allocation size is
handled. Prior to that change, the size would get aligned to at least a
page, whereas after that change a non-page-aligned size would get passed
through unmodified. This ultimately causes a BUG_ON() to trigger in
drm_gem_private_object_init() and crashes the system.
Fix this by restoring the code that align the allocation size.
Fixes: 019cbd4a4feb ("drm/nouveau: Initialize GEM object before TTM object")
Reported-by: Ilia Mirkin
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nouveau_bo.c| 16 +---
drivers/gpu/drm/nouveau/nouveau_bo.h| 4 ++--
drivers/gpu/drm/nouveau/nouveau_gem.c | 3 ++-
drivers/gpu/drm/nouveau/nouveau_prime.c | 7 ---
4 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/drm/nouveau/nouveau_bo.c
index e918b437af17..e7803dca32c5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -186,8 +186,8 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
}
struct nouveau_bo *
-nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32 flags, u32 tile_mode,
-u32 tile_flags)
+nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags,
+u32 tile_mode, u32 tile_flags)
{
struct nouveau_drm *drm = cli->drm;
struct nouveau_bo *nvbo;
@@ -195,8 +195,8 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32
flags, u32 tile_mode,
struct nvif_vmm *vmm = cli->svm.cli ? >svm.vmm : >vmm.vmm;
int i, pi = -1;
- if (!size) {
- NV_WARN(drm, "skipped size %016llx\n", size);
+ if (!*size) {
+ NV_WARN(drm, "skipped size %016llx\n", *size);
return ERR_PTR(-EINVAL);
}
@@ -266,7 +266,7 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32
flags, u32 tile_mode,
pi = i;
/* Stop once the buffer is larger than the current page size. */
- if (size >= 1ULL << vmm->page[i].shift)
+ if (*size >= 1ULL << vmm->page[i].shift)
break;
}
@@ -281,6 +281,8 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32
flags, u32 tile_mode,
}
nvbo->page = vmm->page[pi].shift;
+ nouveau_bo_fixup_align(nvbo, flags, align, size);
+
return nvbo;
}
@@ -294,7 +296,6 @@ nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int
align, u32 flags,
acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
- nouveau_bo_fixup_align(nvbo, flags, , );
nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
nouveau_bo_placement_set(nvbo, flags, 0);
@@ -318,7 +319,8 @@ nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
struct nouveau_bo *nvbo;
int ret;
- nvbo = nouveau_bo_alloc(cli, size, flags, tile_mode, tile_flags);
+ nvbo = nouveau_bo_alloc(cli, , , flags, tile_mode,
+ tile_flags);
if (IS_ERR(nvbo))
return PTR_ERR(nvbo);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h
b/drivers/gpu/drm/nouveau/nouveau_bo.h
index 62930d834fba..38f9d8350963 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.h
@@ -71,8 +71,8 @@ nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo
**pnvbo)
extern struct ttm_bo_driver nouveau_bo_driver;
void nouveau_bo_move_init(struct nouveau_drm *);
-struct nouveau_bo *nouveau_bo_alloc(struct nouveau_cli *, u64 size, u32 flags,
- u32 tile_mode, u32 tile_flags);
+struct nouveau_bo *nouveau_bo_alloc(struct nouveau_cli *, u64 *size, int
*align,
+ u32 flags, u32 tile_mode, u32 tile_flags);
int nouveau_bo_init(struct nouveau_bo *, u64 size, int align, u32 flags,
struct sg_table *sg, struct dma_resv *robj);
int nouveau_bo_new(struct nouveau_cli *, u64 size, int align, u32 flags,
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c
b/drivers/gpu/drm/nouveau/nouveau_gem.c
index c2bfc0591909..1bdffd714456 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -188,7 +188,8 @@ nouveau_gem_new(struct nouveau_cli *cli, u64 size, int
align, uint32_t domain,
if (domain & NOUVEAU_GEM_DOMAIN_COHERENT)
flags |= TTM_PL_FLAG_UNCACHED;
- nvbo = nouveau_bo_alloc(cli, size, flags, tile_mode, tile_flags);
+ nvbo = nouveau_bo_alloc(cli, , , flags, tile_mode,
+ tile_flags);
if (IS_ERR(nvbo))
return PTR_ERR(nvbo);
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c
b/drivers/gpu/drm/nouveau/nouveau_prime.c
index 84658d434225..656c334ee7d9 100644
[Nouveau] [Bug 103217] Recent noveau causes errors with scilab 5.5.2 on NVIDIA G84GL [Quadro FX 570]
https://bugs.freedesktop.org/show_bug.cgi?id=103217 --- Comment #10 from sarataylor --- After years of not sleeping well and not finding the right guide for natural products online, she decided to do the research so others don’t suffer when buying a new mattress as she did. For the past 3 years, she studied everything about sleep and natural product to put the best natural mattress buying guide online. https://topnaturalmattresses.com/best-mattress-for-stomach-sleepers/# -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [PATCH CI 2/2] drm/connector: Allow max possible encoders to attach to a connector
On 9/13/19 6:28 PM, José Roberto de Souza wrote:
> Currently we restrict the number of encoders that can be linked to
> a connector to 3, increase it to match the maximum number of encoders
> that can be initialized(32).
>
> To more effiently do that lets switch from an array of encoder ids to
> bitmask.
Typo, s/effiently/efficiently/.
>
> v2: Fixing missed return on amdgpu_dm_connector_to_encoder()
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Cc: Alex Deucher
> Cc: dri-de...@lists.freedesktop.org
> Cc: intel-...@lists.freedesktop.org
> Cc: nouveau@lists.freedesktop.org
> Cc: amd-...@lists.freedesktop.org
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +-
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 5 ++-
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 -
> drivers/gpu/drm/drm_client_modeset.c | 3 +-
> drivers/gpu/drm/drm_connector.c | 31 +--
> drivers/gpu/drm/drm_crtc_helper.c | 9 --
> drivers/gpu/drm/drm_probe_helper.c| 3 +-
> drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
> drivers/gpu/drm/nouveau/nouveau_connector.c | 7 ++---
> drivers/gpu/drm/radeon/radeon_connectors.c| 27 ++--
> include/drm/drm_connector.h | 18 +--
> 12 files changed, 55 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> index ece55c8fa673..d8729285f731 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> @@ -217,11 +217,10 @@ amdgpu_connector_update_scratch_regs(struct
> drm_connector *connector,
> struct drm_encoder *encoder;
> const struct drm_connector_helper_funcs *connector_funcs =
> connector->helper_private;
> bool connected;
> - int i;
>
> best_encoder = connector_funcs->best_encoder(connector);
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if ((encoder == best_encoder) && (status ==
> connector_status_connected))
> connected = true;
> else
> @@ -236,9 +235,8 @@ amdgpu_connector_find_encoder(struct drm_connector
> *connector,
> int encoder_type)
> {
> struct drm_encoder *encoder;
> - int i;
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if (encoder->encoder_type == encoder_type)
> return encoder;
> }
> @@ -347,10 +345,9 @@ static struct drm_encoder *
> amdgpu_connector_best_single_encoder(struct drm_connector *connector)
> {
> struct drm_encoder *encoder;
> - int i;
>
> /* pick the first one */
> - drm_connector_for_each_possible_encoder(connector, encoder, i)
> + drm_connector_for_each_possible_encoder(connector, encoder)
> return encoder;
>
> return NULL;
> @@ -1065,9 +1062,8 @@ amdgpu_connector_dvi_detect(struct drm_connector
> *connector, bool force)
> /* find analog encoder */
> if (amdgpu_connector->dac_load_detect) {
> struct drm_encoder *encoder;
> - int i;
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
> encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
> continue;
> @@ -1117,9 +1113,8 @@ amdgpu_connector_dvi_encoder(struct drm_connector
> *connector)
> {
> struct amdgpu_connector *amdgpu_connector =
> to_amdgpu_connector(connector);
> struct drm_encoder *encoder;
> - int i;
>
> - drm_connector_for_each_possible_encoder(connector, encoder, i) {
> + drm_connector_for_each_possible_encoder(connector, encoder) {
> if (amdgpu_connector->use_digital == true) {
> if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
> return encoder;
> @@ -1134,7 +1129,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector
> *connector)
>
> /* then check use digitial */
> /* pick the first one */
> - drm_connector_for_each_possible_encoder(connector, encoder, i)
> + drm_connector_for_each_possible_encoder(connector, encoder)
> return encoder;
>
> return NULL;
> @@ -1271,9 +1266,8 @@ u16
> amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
> {
>
[Nouveau] [Bug 108857] display becomes unresponsive and keyboard input fails
https://bugs.freedesktop.org/show_bug.cgi?id=108857 --- Comment #10 from Vasili Pupkin --- I am experiencing a similar behaviour and a crash with a similar callstack on a much older hardware, see bug 111642 -- You are receiving this mail because: You are the assignee for the bug.___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 107016] Gpio error only from kernel higher as 4.x (k2000m; 0x0e73b0a2; version 80.07.40.00.02)
https://bugs.freedesktop.org/show_bug.cgi?id=107016 --- Comment #25 from atirage21 --- Created attachment 145371 --> https://bugs.freedesktop.org/attachment.cgi?id=145371=edit Valgrind-mmt log from glxgears with driver nvidia 390.116ubuntu0.18.04.1 -- You are receiving this mail because: You are the assignee for the bug.___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau
