On Mon, Dec 9, 2019 at 12:39 PM Rafael J. Wysocki wrote:
>
> On Mon, Dec 9, 2019 at 12:17 PM Karol Herbst wrote:
> >
> > anybody any other ideas?
>
> Not yet, but I'm trying to collect some more information.
>
> > It seems that both patches don't really fix
> > the issue and I have no idea left
From: Thierry Reding
There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.
Signed-off-by: Thierry Reding
---
Changes in v2:
- remove IOMMU_API protection to
From: Thierry Reding
gp10b uses the new engine enumeration mechanism introduced in the Pascal
architecture. As a result, the copy engine, which used to be at index 2
for prior Tegra GPU instantiations, has now moved to index 0. Fix up the
index and also use the gp100 variant of the copy engine
From: Thierry Reding
The GPUs found on Tegra SoCs have registers that can be used to read the
WPR configuration. Use these registers instead of reaching into the
memory controller's register space to read the same information.
Signed-off-by: Thierry Reding
---
From: Thierry Reding
Hi Ben,
here's a revised subset of the patches I had sent out a couple of weeks
ago. I've reworked the BAR2 accesses in the way that you had suggested,
which at least for GP10B turned out to be fairly trivial to do. I have
not looked in detail at this for GV11B yet, but a
From: Thierry Reding
When Nouveau is instantiated on top of a platform device, the dev->pdev
field will be NULL and calling pci_disable_device() will crash. Move the
PCI disabling code to the PCI specific driver removal code.
Signed-off-by: Thierry Reding
---
From: Thierry Reding
When the GPU powergate is controlled by a generic power domain provider,
the reset will automatically be asserted and deasserted as part of the
power-ungating procedure.
On some Jetson TX2 boards, doing an additional assert and deassert of
the GPU outside of the
From: Thierry Reding
If the GPU clock has not had a rate set, initialize it to the maximum
clock rate to make sure it does run.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12
1 file changed, 12 insertions(+)
diff --git
From: Thierry Reding
When this field was added in commit 5702ee24182f ("ACPI/IORT: Check ATS
capability in root complex nodes"), the kerneldoc comment wasn't updated
at the same time.
Acked-by: Joerg Roedel
Signed-off-by: Thierry Reding
---
include/linux/iommu.h | 1 +
1 file changed, 1
From: Thierry Reding
There is no BAR2 on GP10B and there is no need to map through BAR2
because all memory is shared between the GPU and the CPU. Add a custom
implementation of the fault sub-device that uses nvkm_memory_addr()
instead of nvkm_memory_bar2() to return the address of a pinned fault
From: Thierry Reding
This dummy implementation is useful to avoid a dependency on the
IOMMU_API Kconfig symbol in drivers that can optionally use the IOMMU
API.
In order to fully use this, also move the struct iommu_fwspec definition
out of the IOMMU_API protected region.
Acked-by: Joerg
On Mon, Dec 9, 2019 at 12:17 PM Karol Herbst wrote:
>
> anybody any other ideas?
Not yet, but I'm trying to collect some more information.
> It seems that both patches don't really fix
> the issue and I have no idea left on my side to try out. The only
> thing left I could do to further
anybody any other ideas? It seems that both patches don't really fix
the issue and I have no idea left on my side to try out. The only
thing left I could do to further investigate would be to reverse
engineer the Nvidia driver as they support runpm on Turing+ GPUs now,
but I've heard users having
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