Use abstracted resource query functions to allow FB core to handle
both PCI and platform devices.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev
devices.
Commonly-used PCI functions include resource range query and page
mapping. These functions are abstracted so the correct bus type is used
to perform them. Some PCI-dependent code is also disabled when probing a
non-PCI device.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers
Memory was always allocated for 4096 channels. Change this to allocate
what we actually need according to the number of channels we use.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
pm_runtime_get*() may return -EACCESS to indicate a device does not have
runtime PM enabled. This is the case when the nouveau.runpm parameter is
set to 0, and is not an error in that context. Handle this case without
failure.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply neither.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Remove PCI-dependent code so the FIFO engine can also handle platform
devices.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/fifo/base.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo
of a large,
contiguous pool.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core/include/subdev/fb.h | 1 +
drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c| 28 ++
drivers/gpu/drm/nouveau/core/subdev
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h| 1 +
drivers/gpu/drm/nouveau/core/engine
Use abstracted resource query functions, and obtain the IRQ from the
correct bus.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/include/subdev/mc.h | 1 +
drivers/gpu/drm/nouveau/core/subdev/mc/base.c| 43 +++-
2 files changed, 29
Add a nouveau_drm_platform_probe() function that probes a Nouveau
platform device and registers it using drm_platform_init().
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/device/base.c | 34 ++
.../gpu/drm/nouveau/core/include
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0
On Sun, Feb 2, 2014 at 3:35 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
Some very trivial comments below:
On Fri, Jan 31, 2014 at 10:16 PM, Alexandre Courbot acour...@nvidia.com
wrote:
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs
On 02/03/2014 04:10 AM, Ilia Mirkin wrote:
Hi Alexandre,
On Fri, Jan 31, 2014 at 10:16 PM, Alexandre Courbot acour...@nvidia.com wrote:
I guess my email address might surprise some of you, so let me anticipate some
questions you might have. :P Yes, this work is endorsed by NVIDIA. Several
On 02/03/2014 08:25 PM, David Herrmann wrote:
Hi
[..snip..]
Finally, support for probing GK20A is added in the last 2 patches. It should be
noted that contrary to what Nouveau currently expects, GK20A does not embed any
display hardware (that part being handled by tegradrm). So this driver
On 02/04/2014 12:54 PM, Ben Skeggs wrote:
On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot acour...@nvidia.com wrote:
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions
On 02/04/2014 12:55 PM, Ben Skeggs wrote:
On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot acour...@nvidia.com wrote:
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Just
On 02/04/2014 12:53 PM, Ben Skeggs wrote:
On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot acour...@nvidia.com wrote:
Hello everyone,
Hey Alex,
The series looks pretty good to me. I'll reply to the relevant
patches with any minor nit-picks on top of what's already been said by
others
Hi Daniel,
On 02/04/2014 06:15 PM, Daniel Vetter wrote:
On Sat, Feb 01, 2014 at 12:16:54PM +0900, Alexandre Courbot wrote:
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau
Address of the ENG_RUNLIST register should be 0x002284 + (engine * 8),
not 0x002284 + (engine * 4).
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
Stumbled upon this one and I'm quite certain the offset was not correct.
This is inconsequential for GK20A which only features one runlist
On Sun, Feb 2, 2014 at 10:43 PM, Alexandre Courbot gnu...@gmail.com wrote:
On Sun, Feb 2, 2014 at 8:58 AM, Lucas Stach d...@lynxeye.de wrote:
Am Samstag, den 01.02.2014, 18:28 -0500 schrieb Ilia Mirkin:
On Sat, Feb 1, 2014 at 8:40 AM, Lucas Stach d...@lynxeye.de wrote:
Am Samstag, den
Memory was always allocated for 4096 channels. Change this to allocate
what we actually need according to the number of channels we use.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
pm_runtime_get*() may return -EACCESS to indicate a device does not have
runtime PM enabled. This is the case when the nouveau.runpm parameter is
set to 0, and is not an error in that context. Handle this case without
failure.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu
On Mon, Feb 10, 2014 at 9:34 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Feb 10, 2014 at 02:58:12PM +0900, Alexandre Courbot wrote:
pm_runtime_get*() may return -EACCESS to indicate a device does not have
s/-EACCESS/-EACCES/
Oops.
runtime PM enabled. This is the case when
On Mon, Feb 10, 2014 at 8:50 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Feb 10, 2014 at 02:53:00PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c
b/drivers/gpu/drm/nouveau/core/engine/device/base.c
[...]
+resource_size_t
pm_runtime_get*() may return -EACCES to indicate a device does not have
runtime PM enabled. This is currently the case with platform devices
on Nouveau, and is not an error in that context. Handle this case
without failure.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
Changes since v1
drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
Changes since v1:
- Refactored nouveau_device_create_() to take an additional bus
Hi Emil,
On 02/12/2014 11:18 PM, Emil Velikov wrote:
On 12/02/14 05:38, Alexandre Courbot wrote:
Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead
of PCI to which Nouveau is tightly dependent. This patch allows Nouveau
to handle platform devices by:
- abstracting PCI
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Add a missing newline at the end of a DRM_INFO message.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau
and relying on BAR mappings for kernel access and exposure to
user-space, as it fits better with existing code and keeps us safe from most of
the CPU/GPU memory coherency issues (at the cost of some performance).
Looking forward to your review of these few patches! :)
Cheers,
Alex.
Alexandre Courbot (12
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h| 1 +
drivers/gpu/drm/nouveau/core/engine
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0
to also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0
Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply neither.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers
Hi Lucas,
On Mon, Mar 24, 2014 at 10:19 PM, Lucas Stach l.st...@pengutronix.de wrote:
Hi Alexandre,
Am Montag, den 24.03.2014, 17:42 +0900 schrieb Alexandre Courbot:
Hi everyone,
[...]
A few lines of hacks (not included here) are still needed to deal with cached
mappings triggering
On Wed, Mar 26, 2014 at 7:33 PM, Lucas Stach l.st...@pengutronix.de wrote:
It does so by doing the necessary manual cache flushes/invalidates on
buffer access, so costs some performance. To avoid this you really want
to get writecombined mappings into the kernel-userspace interface.
Simply
On Tue, Mar 25, 2014 at 7:10 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05:42:26PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
[...]
static int
On Tue, Mar 25, 2014 at 7:34 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
[...]
+#include subdev
On Wed, Mar 26, 2014 at 1:21 PM, Ben Skeggs skeg...@gmail.com wrote:
On Tue, Mar 25, 2014 at 8:58 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05:42:30PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b
On Wed, Mar 26, 2014 at 1:22 PM, Ben Skeggs skeg...@gmail.com wrote:
On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot acour...@nvidia.com
wrote:
Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
On Wed, Mar 26, 2014 at 1:24 PM, Ben Skeggs skeg...@gmail.com wrote:
On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot acour...@nvidia.com
wrote:
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used
On Wed, Mar 26, 2014 at 1:27 PM, Ben Skeggs skeg...@gmail.com wrote:
On Tue, Mar 25, 2014 at 9:10 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
GK20A does not embed a dedicated COPY engine and thus cannot allocate
On Wed, Mar 26, 2014 at 1:28 PM, Ben Skeggs skeg...@gmail.com wrote:
On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot acour...@nvidia.com
wrote:
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm
On Wed, Apr 2, 2014 at 11:18 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Wed, Apr 2, 2014 at 9:52 AM, Alexandre Courbot gnu...@gmail.com wrote:
On Tue, Mar 25, 2014 at 7:34 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote
On Wed, Mar 26, 2014 at 1:19 PM, Ben Skeggs skeg...@gmail.com wrote:
On Tue, Mar 25, 2014 at 7:54 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05:42:24PM +0900, Alexandre Courbot wrote:
GK20A's timer is directly attached to the system timer and cannot
On 04/11/2014 04:31 PM, Ben Skeggs wrote:
On Fri, Apr 11, 2014 at 12:46 PM, Alexandre Courbot gnu...@gmail.com wrote:
On Wed, Mar 26, 2014 at 1:19 PM, Ben Skeggs skeg...@gmail.com wrote:
On Tue, Mar 25, 2014 at 7:54 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05
On Mon, Apr 14, 2014 at 5:35 PM, Ben Skeggs skeg...@gmail.com wrote:
On Fri, Apr 11, 2014 at 5:34 PM, Alexandre Courbot acour...@nvidia.com
wrote:
On 04/11/2014 04:31 PM, Ben Skeggs wrote:
On Fri, Apr 11, 2014 at 12:46 PM, Alexandre Courbot gnu...@gmail.com
wrote:
On Wed, Mar 26, 2014
On Wed, Mar 26, 2014 at 1:27 PM, Ben Skeggs skeg...@gmail.com wrote:
On Tue, Mar 25, 2014 at 9:10 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
GK20A does not embed a dedicated COPY engine and thus cannot allocate
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
BAR initialization code factorization
- Removed non-essential code which only purpose was to avoid warnings
- Use nv_wait in ibus driver
Alexandre Courbot (10):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A support
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev
to also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0
Skip the creation of a software channel for GK20A as software methods
are not yet supported.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers
On 04/22/2014 08:48 AM, Ben Skeggs wrote:
On Tue, Apr 22, 2014 at 4:03 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot acour...@nvidia.com wrote:
Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
bytes or u32's? From
On 04/22/2014 03:07 AM, Ilia Mirkin wrote:
On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot acour...@nvidia.com wrote:
Skip the creation of a software channel for GK20A as software methods
are not yet supported.
How is GK20A different from a nvc0+ card that lacks PDISPLAY (like all
the 3D
On 04/22/2014 07:40 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Apr 21, 2014 at 03:02:16PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
On Wed, Apr 23, 2014 at 11:07 AM, Alexandre Courbot acour...@nvidia.com wrote:
On 04/22/2014 07:40 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Apr 21, 2014 at 03:02:16PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm
Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev
to also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph
this looks good! Once this gets merged the next set will be to use this
driver on Jetson and Venice2 boards.
Cheers,
Alexandre Courbot (9):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A support
drm/nouveau/fb: add
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
On Mon, Apr 28, 2014 at 8:44 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Wed, Apr 23, 2014 at 03:11:01PM +0900, Alexandre Courbot wrote:
On Wed, Apr 23, 2014 at 11:07 AM, Alexandre Courbot acour...@nvidia.com
wrote:
On 04/22/2014 07:40 PM, Thierry Reding wrote:
* PGP Signed
On Mon, Apr 28, 2014 at 11:10 AM, Ben Skeggs skeg...@gmail.com wrote:
On Fri, Apr 25, 2014 at 5:19 PM, Alexandre Courbot acour...@nvidia.com
wrote:
nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
On 05/01/2014 04:11 PM, Ben Skeggs wrote:
On Fri, Apr 25, 2014 at 5:19 PM, Alexandre Courbot acour...@nvidia.com wrote:
Changes since v2:
- Enabled software class
- Removed unneeded changes to nouveau_accel_init()
- Replaced use of architecture-private pfn_to_dma() and dma_to_pfn
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev
Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed
(instead of only relying on the NvGrUseFW parameter).
Alexandre Courbot (9):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A support
drm/nouveau/fb: add GK20A support
drm/nouveau/fifo: add GK20A support
drm
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred...@nvidia.com
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
to also include the case
where an external firmware has also been loaded.
Also switch to external firmware if the graph class has no microcode
linked to it.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 10 +++---
1 file changed, 7
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
Reviewed-by: Thierry Reding tred
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
gk20a_ram_put() can be called with a NULL nouveau_mem in case of error.
Handle that case the way is it done in other RAM drivers.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 74 ++-
1 file changed, 46 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
b/drivers/gpu/drm/nouveau/core/subdev/fb
situation
(compile error).
Alexandre Courbot (2):
drm/gk20a/fb: fix huge memory leak
drm/gk20a/fb: fix compile error whith CMA and module
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 95 ---
1 file changed, 67 insertions(+), 28 deletions(-)
--
1.9.2
, but at least won't produce a compile
error.
This is a temporary fix until a better memory allocation scheme is
devised.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 25 +--
1 file changed, 23 insertions(+), 2
From: Lucas Stach d...@lynxeye.de
On arches with non-coherent PCI, we need to flush caches ourselfes at
the appropriate places. Introduce two small helpers to make things easy
for TTM based drivers.
Signed-off-by: Lucas Stach d...@lynxeye.de
Signed-off-by: Alexandre Courbot acour...@nvidia.com
architectures, and uses it when
writing to in-memory BOs. It will also be useful for implementations of
instmem that access shared memory directly instead of going through
PRAMIN.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau/core/os.h| 17 +
drivers
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