On Mon, May 19, 2014 at 7:03 PM, Thierry Reding
wrote:
> On Mon, May 19, 2014 at 11:22:11AM +0200, Lucas Stach wrote:
>> Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding:
>> > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote:
>> > > Some
On Mon, May 19, 2014 at 6:31 PM, Lucas Stach wrote:
> Am Montag, den 19.05.2014, 16:10 +0900 schrieb Alexandre Courbot:
>> From: Lucas Stach
>>
>> Signed-off-by: Lucas Stach
>> [acour...@nvidia.com: make conditional and platform-friendly]
>> Signed-off-by: Alex
On Mon, May 19, 2014 at 5:46 PM, Thierry Reding
wrote:
> On Mon, May 19, 2014 at 04:10:57PM +0900, Alexandre Courbot wrote:
>> From: Lucas Stach
>>
>> Signed-off-by: Lucas Stach
>> [acour...@nvidia.com: make conditional and platform-friendly]
>> Signed-off-b
On Mon, May 19, 2014 at 5:33 PM, Thierry Reding
wrote:
> On Mon, May 19, 2014 at 04:10:56PM +0900, Alexandre Courbot wrote:
>> From: Lucas Stach
>>
>> On arches with non-coherent PCI,
>
> I guess since this applies to gk20a
>
>> we need to flush caches ours
On 05/19/2014 06:57 PM, Lucas Stach wrote:
Am Montag, den 19.05.2014, 18:46 +0900 schrieb Alexandre Courbot:
This patch is not meant to be merged, but rather to try and understand
why this is needed and what a more suitable solution could be.
Allowing BOs to be write-cached results in the
through the BAR.
Any idea about the origin of this behavior? Does ARM forbid cached
mappings over IO regions?
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/drm
From: Thierry Reding
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124-venice2.dts | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
b/arch/arm/boot/dts/tegra124-venice2.dts
index
From: Thierry Reding
Add the GK20A device node to Tegra124's device tree.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm
Add the device tree binding documentation for the GK20A GPU used in
Tegra K1 SoCs.
Signed-off-by: Alexandre Courbot
---
.../devicetree/bindings/gpu/nvidia,gk20a.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu
Signed-off-by: Alexandre Courbot
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index e31fb61a81d3..15a194d1277f 100644
--- a/arch/arm
really needs to do is to make sure the module is powered and
its clocks active before calling nouveau_drm_platform_probe().
Heavily based on work done by Thierry Reding.
Signed-off-by: Thierry Reding
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Kconfig| 8
rather intended for Tegra.
Alexandre Courbot (3):
drm/nouveau: support for probing platform devices
ARM: tegra: of: add GK20A device tree binding
ARM: tegra: jetson-tk1: enable GK20A GPU
Thierry Reding (2):
ARM: tegra: add GK20A GPU to Tegra124 DT
ARM: tegra: venice2: enable GK20A GPU
From: Lucas Stach
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 1df856f78568..30e5d90cb7bc
From: Lucas Stach
Signed-off-by: Lucas Stach
[acour...@nvidia.com: make conditional and platform-friendly]
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 32
drivers/gpu/drm/nouveau/nouveau_bo.h | 20
drivers
architectures, and uses it when
writing to in-memory BOs. It will also be useful for implementations of
instmem that access shared memory directly instead of going through
PRAMIN.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/os.h| 17 +
drivers/gpu/drm/nouveau
/nouveau/2013-August/014026.html
Another patch takes care of flushing the CPU write-buffer when writing BOs
through a non-BAR path.
Alexandre Courbot (1):
drm/nouveau: introduce CPU cache flushing macro
Lucas Stach (3):
drm/ttm: recognize ARM arch in ioprot handler
drm/ttm: introduce dma
From: Lucas Stach
On arches with non-coherent PCI, we need to flush caches ourselfes at
the appropriate places. Introduce two small helpers to make things easy
for TTM based drivers.
Signed-off-by: Lucas Stach
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/ttm/ttm_tt.c| 25
situation
(compile error).
Alexandre Courbot (2):
drm/gk20a/fb: fix huge memory leak
drm/gk20a/fb: fix compile error whith CMA and module
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 95 ---
1 file changed, 67 insertions(+), 28 deletions(-)
--
1.9.2
, but at least won't produce a compile
error.
This is a temporary fix until a better memory allocation scheme is
devised.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 25 +--
1 file changed, 23 insertions(+), 2 deletions(-)
diff
.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 74 ++-
1 file changed, 46 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
index
gk20a_ram_put() can be called with a NULL nouveau_mem in case of error.
Handle that case the way is it done in other RAM drivers.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/nouveau
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu/drm
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
also include the case
where an external firmware has also been loaded.
Also switch to external firmware if the graph class has no microcode
linked to it.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 10 +++---
1 file changed, 7 insertions(+), 3
class (instead of only relying on the NvGrUseFW parameter).
Alexandre Courbot (9):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A support
drm/nouveau/fb: add GK20A support
drm/nouveau/fifo: add GK20A support
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
On 05/01/2014 04:11 PM, Ben Skeggs wrote:
On Fri, Apr 25, 2014 at 5:19 PM, Alexandre Courbot wrote:
Changes since v2:
- Enabled software class
- Removed unneeded changes to nouveau_accel_init()
- Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with
the portable
On Mon, Apr 28, 2014 at 11:10 AM, Ben Skeggs wrote:
> On Fri, Apr 25, 2014 at 5:19 PM, Alexandre Courbot
> wrote:
>> nvc0_graph_ctor() would only let the graphics engine be enabled if its
>> oclass has a proper microcode linked to it. This prevents GR from being
>> enab
On Mon, Apr 28, 2014 at 8:44 PM, Thierry Reding
wrote:
> On Wed, Apr 23, 2014 at 03:11:01PM +0900, Alexandre Courbot wrote:
>> On Wed, Apr 23, 2014 at 11:07 AM, Alexandre Courbot
>> wrote:
>> > On 04/22/2014 07:40 PM, Thierry Reding wrote:
>> >>
also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
looks good! Once this gets merged the next set will be to use this
driver on Jetson and Venice2 boards.
Cheers,
Alexandre Courbot (9):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A support
drm/nouveau/fb: add
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu/drm
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
On Wed, Apr 23, 2014 at 11:07 AM, Alexandre Courbot wrote:
> On 04/22/2014 07:40 PM, Thierry Reding wrote:
>>
>> * PGP Signed by an unknown key
>>
>>
>> On Mon, Apr 21, 2014 at 03:02:16PM +0900, Alexandre Courbot wrote:
>> [...]
>>>
>>
On 04/22/2014 07:40 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Apr 21, 2014 at 03:02:16PM +0900, Alexandre Courbot wrote:
[...]
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c
On 04/22/2014 03:07 AM, Ilia Mirkin wrote:
On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot wrote:
Skip the creation of a software channel for GK20A as software methods
are not yet supported.
How is GK20A different from a nvc0+ card that lacks PDISPLAY (like all
the 3D Controller ones, and
On 04/22/2014 08:48 AM, Ben Skeggs wrote:
On Tue, Apr 22, 2014 at 4:03 AM, Ilia Mirkin wrote:
On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot wrote:
Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
bytes or u32's? From the code, I'm guessing the latter
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu
Skip the creation of a software channel for GK20A as software methods
are not yet supported.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will
fail to run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
Reviewed-by: Thierry Reding
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c
also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
about BAR initialization code factorization
- Removed non-essential code which only purpose was to avoid warnings
- Use nv_wait in ibus driver
Alexandre Courbot (10):
drm/nouveau/bar: only ioremap BAR3 if it exists
drm/nouveau/bar/nvc0: support chips without BAR3
drm/nouveau/ibus: add GK20A su
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
On Wed, Mar 26, 2014 at 1:27 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 9:10 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
>>> GK20A does not embed a dedicated COPY engine and thus cannot allocate
>
On Mon, Apr 14, 2014 at 5:35 PM, Ben Skeggs wrote:
> On Fri, Apr 11, 2014 at 5:34 PM, Alexandre Courbot
> wrote:
>> On 04/11/2014 04:31 PM, Ben Skeggs wrote:
>>>
>>> On Fri, Apr 11, 2014 at 12:46 PM, Alexandre Courbot
>>> wrote:
>>>>
>
On 04/11/2014 04:31 PM, Ben Skeggs wrote:
On Fri, Apr 11, 2014 at 12:46 PM, Alexandre Courbot wrote:
On Wed, Mar 26, 2014 at 1:19 PM, Ben Skeggs wrote:
On Tue, Mar 25, 2014 at 7:54 AM, Thierry Reding
wrote:
On Mon, Mar 24, 2014 at 05:42:24PM +0900, Alexandre Courbot wrote:
GK20A's
On Wed, Mar 26, 2014 at 1:19 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 7:54 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:24PM +0900, Alexandre Courbot wrote:
>>> GK20A's timer is directly attached to the system timer and cannot be
>>> cal
On Wed, Apr 2, 2014 at 11:18 PM, Ilia Mirkin wrote:
> On Wed, Apr 2, 2014 at 9:52 AM, Alexandre Courbot wrote:
>> On Tue, Mar 25, 2014 at 7:34 AM, Thierry Reding
>> wrote:
>>> On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote:
>>> [...]
>>
On Wed, Mar 26, 2014 at 1:28 PM, Ben Skeggs wrote:
> On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot
> wrote:
>> Set the correct subdev/engine classes when GK20A (0xea) is probed.
>>
>> Signed-off-by: Alexandre Courbot
>> ---
>> drivers/gpu/drm/no
On Wed, Mar 26, 2014 at 1:27 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 9:10 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
>>> GK20A does not embed a dedicated COPY engine and thus cannot allocate
>
On Wed, Mar 26, 2014 at 1:24 PM, Ben Skeggs wrote:
> On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot
> wrote:
>> Add a GR device for GK20A based on NVE4, with the correct classes
>> definitions (GK20A's 3D class is 0xa297).
>>
>> Most of the NVE4 code can
On Wed, Mar 26, 2014 at 1:22 PM, Ben Skeggs wrote:
> On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot
> wrote:
>> Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
>> run from non-prepadded firmware files.
>>
>> Signed-off-by: Alexandre C
On Wed, Mar 26, 2014 at 1:21 PM, Ben Skeggs wrote:
> On Tue, Mar 25, 2014 at 8:58 AM, Thierry Reding
> wrote:
>> On Mon, Mar 24, 2014 at 05:42:30PM +0900, Alexandre Courbot wrote:
>> [...]
>>> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
>>
On Tue, Mar 25, 2014 at 7:34 AM, Thierry Reding
wrote:
> On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote:
> [...]
>> diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
>> b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
> [...]
>>
On Tue, Mar 25, 2014 at 7:10 AM, Thierry Reding
wrote:
> On Mon, Mar 24, 2014 at 05:42:26PM +0900, Alexandre Courbot wrote:
> [...]
>> diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
>> b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
> [...]
>> static i
On Wed, Mar 26, 2014 at 7:33 PM, Lucas Stach wrote:
>> > It does so by doing the necessary manual cache flushes/invalidates on
>> > buffer access, so costs some performance. To avoid this you really want
>> > to get writecombined mappings into the kernel<->userspace interface.
>> > Simply mapping
Hi Lucas,
On Mon, Mar 24, 2014 at 10:19 PM, Lucas Stach wrote:
> Hi Alexandre,
>
> Am Montag, den 24.03.2014, 17:42 +0900 schrieb Alexandre Courbot:
>> Hi everyone,
> [...]
>>
>> A few lines of hacks (not included here) are still needed to deal with cached
>>
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply neither.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/include/subdev/ibus.h | 1
also include the case
where an external firmware has also been loaded.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
b/drivers/gpu
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).
Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
Set the correct subdev/engine classes when GK20A (0xea) is probed.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
b/drivers/gpu
Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
run from non-prepadded firmware files.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 2 +
drivers/gpu/drm/nouveau/core
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Makefile | 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h| 1 +
drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c
Add a missing newline at the end of a DRM_INFO message.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.
Signed-off-by: Alexandre
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19 +--
1 file ch
s and relying on BAR mappings for kernel access and exposure to
user-space, as it fits better with existing code and keeps us safe from most of
the CPU/GPU memory coherency issues (at the cost of some performance).
Looking forward to your review of these few patches! :)
Cheers,
Alex.
Alexandre Courbo
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 7
drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot
---
Changes since v2:
- Moved MSI code under PCI-conditioned blocks in mc/base.c, as suggested by
Emil
Hi Emil,
On 02/12/2014 11:18 PM, Emil Velikov wrote:
On 12/02/14 05:38, Alexandre Courbot wrote:
Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead
of PCI to which Nouveau is tightly dependent. This patch allows Nouveau
to handle platform devices by:
- abstracting PCI
drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
- Refactored nouveau_device_create_() to take an additional bus type
argument
pm_runtime_get*() may return -EACCES to indicate a device does not have
runtime PM enabled. This is currently the case with platform devices
on Nouveau, and is not an error in that context. Handle this case
without failure.
Signed-off-by: Alexandre Courbot
---
Changes since v1:
- Fixed typo and
On Mon, Feb 10, 2014 at 8:50 PM, Thierry Reding
wrote:
> On Mon, Feb 10, 2014 at 02:53:00PM +0900, Alexandre Courbot wrote:
> [...]
>> diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c
>> b/drivers/gpu/drm/nouveau/core/engine/device/base.c
> [...
On Mon, Feb 10, 2014 at 9:34 PM, Thierry Reding
wrote:
> On Mon, Feb 10, 2014 at 02:58:12PM +0900, Alexandre Courbot wrote:
>> pm_runtime_get*() may return -EACCESS to indicate a device does not have
>
> s/-EACCESS/-EACCES/
Oops.
>> runtime PM enabled. This is the case w
pm_runtime_get*() may return -EACCESS to indicate a device does not have
runtime PM enabled. This is the case when the nouveau.runpm parameter is
set to 0, and is not an error in that context. Handle this case without
failure.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau
Memory was always allocated for 4096 channels. Change this to allocate
what we actually need according to the number of channels we use.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should now at least be runnable with platform devices.
Signed-off-by: Alexandre Courbot
---
Sending this ahead since this has received no objections in the RFC and
should be a no-op for PCI
On Sun, Feb 2, 2014 at 10:43 PM, Alexandre Courbot wrote:
> On Sun, Feb 2, 2014 at 8:58 AM, Lucas Stach wrote:
>> Am Samstag, den 01.02.2014, 18:28 -0500 schrieb Ilia Mirkin:
>>> On Sat, Feb 1, 2014 at 8:40 AM, Lucas Stach wrote:
>>> > Am Samstag, den 01.02.2014,
Address of the ENG_RUNLIST register should be 0x002284 + (engine * 8),
not 0x002284 + (engine * 4).
Signed-off-by: Alexandre Courbot
---
Stumbled upon this one and I'm quite certain the offset was not correct.
This is inconsequential for GK20A which only features one runlist, but
other
Hi Daniel,
On 02/04/2014 06:15 PM, Daniel Vetter wrote:
On Sat, Feb 01, 2014 at 12:16:54PM +0900, Alexandre Courbot wrote:
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/drm/nouveau/Mak
On 02/04/2014 12:53 PM, Ben Skeggs wrote:
On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot wrote:
Hello everyone,
Hey Alex,
The series looks pretty good to me. I'll reply to the relevant
patches with any minor nit-picks on top of what's already been said by
others.
Thanks for
On 02/04/2014 12:55 PM, Ben Skeggs wrote:
On Sat, Feb 1, 2014 at 1:16 PM, Alexandre Courbot wrote:
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.
Just a curiosity:
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