is broken now
(how do you distinguish a long gpu job from a stuck one?). In many
cases, a channel needs to be shut down completely when it breaks (e.g.,
mmu fault).
Signed-off-by: Konsta Hölttä khol...@nvidia.com
---
drm/nouveau/include/nvif/event.h | 1 +
drm/nouveau/include/nvkm/engine/fifo.h
currently signals idle timeout, sw notify, mmu fault and
illegal pbdma error conditions.
Signed-off-by: Konsta Hölttä khol...@nvidia.com
---
drm/nouveau/include/nvif/class.h | 2 ++
drm/nouveau/include/nvif/event.h | 11 +++
drm/nouveau/include/nvkm/engine/fifo.h | 3 ++
drm/nouveau
on a version of gnurou/staging.
Thanks!
Konsta (sooda in IRC)
Konsta Hölttä (5):
notify channel errors to userspace
HACK don't verify route == owner in nvkm ioctl
gk104: channel priority/timeslice support
channel timeout using repeated sched timeouts
force fences updated in error conditions
, and then
enable the channel again. The shift bit in the timeslice register is
left untouched (3) as is the enable bit.
Signed-off-by: Konsta Hölttä khol...@nvidia.com
---
drm/nouveau/include/nvif/class.h | 10 +++
drm/nouveau/nvkm/engine/fifo/gk104.c | 58
is broken now
(how do you distinguish a too long gpu job from a stuck one?). In many
cases, a channel needs to be shut down completely when it breaks (e.g.,
mmu fault).
Signed-off-by: Konsta Hölttä <khol...@nvidia.com>
---
drm/nouveau/include/nvif/event.h | 1 +
drm/nouveau/include/nvkm/
by the same client.
This will need to be fixed in some proper way. Will these objects be
managed by userspace at some point?
Signed-off-by: Konsta Hölttä <khol...@nvidia.com>
---
drm/nouveau/nvkm/core/ioctl.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drm/nouvea
of-concept on Jetson TK1, and the
code is adapted from the latest nvgpu.
The patches can also be found in http://github.com/sooda/nouveau and are based
on a version of gnurou/staging.
Thanks!
Konsta (sooda in IRC)
Konsta Hölttä (5):
notify channel errors to userspace
don't verify route == owner in
handler is cleaned up too.
Signed-off-by: Konsta Hölttä <khol...@nvidia.com>
---
drm/nouveau/include/nvif/class.h | 8
drm/nouveau/nvkm/engine/fifo/gk104.c | 92 +---
2 files changed, 84 insertions(+), 16 deletions(-)
diff --git a/drm/nouveau/i
mpt it out, change the timeslice, and then
enable the channel again. The shift bit in the timeslice register is
left untouched (i.e., 3) as is the enable bit.
Signed-off-by: Konsta Hölttä <khol...@nvidia.com>
---
drm/nouveau/include/nvif/class.h | 10 ++
drm/nouveau/nvkm/engine/f
currently signals idle timeout, sw notify, mmu fault and
illegal pbdma error conditions.
Signed-off-by: Konsta Hölttä <khol...@nvidia.com>
---
drm/nouveau/include/nvif/class.h | 2 +
drm/nouveau/include/nvif/event.h | 11
drm/nouveau/include/nvkm/engine/fifo.h | 3 ++
drm/n
On 01/09/15 16:26, Ben Skeggs wrote:
On 31 August 2015 at 21:38, Konsta Hölttä <khol...@nvidia.com> wrote:
Hi there,
Resending these now that they've had some more polish and testing, and I heard
that Ben's vacation is over :-)
These patches work as a starting point for more explicit
On 02/09/15 13:01, Konsta Hölttä wrote:
On 01/09/15 16:26, Ben Skeggs wrote:
On 31 August 2015 at 21:38, Konsta Hölttä <khol...@nvidia.com> wrote:
Hi there,
Resending these now that they've had some more polish and testing,
and I heard
that Ben's vacation is over :-)
These patche
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