Re: [Nouveau] Add pause/unpause methods for PFIFO PGRAPH. Use them to get stable clock changes
Le 07/10/2010 03:33, Martin Peres a écrit :
Hi,
Here is an updated version, all in one patch. When we agree on the
code, I'll split it into 3 patches.
Sorry, I forgot to attach it. Here it is.
From 86e7dd89810b37a12ae189633de41aacf07355cb Mon Sep 17 00:00:00 2001
From: Martin Peres martin.pe...@ensi-bourges.fr
Date: Thu, 7 Oct 2010 05:20:38 +0200
Subject: [PATCH] Pause the card before reclocking
Signed-off-by: Martin Peres martin.pe...@ensi-bourges.fr
---
drivers/gpu/drm/nouveau/nouveau_drv.h | 10 ++
drivers/gpu/drm/nouveau/nouveau_pm.c| 50 +-
drivers/gpu/drm/nouveau/nouveau_reg.h |3 ++
drivers/gpu/drm/nouveau/nouveau_state.c | 35 +-
drivers/gpu/drm/nouveau/nv50_fifo.c | 17 ++
drivers/gpu/drm/nouveau/nv50_graph.c| 48 +
6 files changed, 160 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 591254e..9317bc3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -304,6 +304,9 @@ struct nouveau_fifo_engine {
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
int (*unload_context)(struct drm_device *);
+
+ int (*pause)(struct drm_device *);
+ void (*unpause)(struct drm_device *);
};
struct nouveau_pgraph_object_method {
@@ -339,6 +342,9 @@ struct nouveau_pgraph_engine {
void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
uint32_t size, uint32_t pitch);
+
+ int (*pause)(struct drm_device *);
+ void (*unpause)(struct drm_device *);
};
struct nouveau_display_engine {
@@ -1036,6 +1042,8 @@ extern int nv50_fifo_create_context(struct nouveau_channel *);
extern void nv50_fifo_destroy_context(struct nouveau_channel *);
extern int nv50_fifo_load_context(struct nouveau_channel *);
extern int nv50_fifo_unload_context(struct drm_device *);
+extern int nv50_fifo_pause(struct drm_device *);
+extern void nv50_fifo_unpause(struct drm_device *);
/* nvc0_fifo.c */
extern int nvc0_fifo_init(struct drm_device *);
@@ -1113,6 +1121,8 @@ extern int nv50_graph_load_context(struct nouveau_channel *);
extern int nv50_graph_unload_context(struct drm_device *);
extern void nv50_graph_context_switch(struct drm_device *);
extern int nv50_grctx_init(struct nouveau_grctx *);
+extern int nv50_graph_pause(struct drm_device *dev);
+extern void nv50_graph_unpause(struct drm_device *dev);
/* nvc0_graph.c */
extern int nvc0_graph_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c
index 1c99c55..b546a4d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -55,6 +55,7 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
struct drm_nouveau_private *dev_priv = dev-dev_private;
struct nouveau_pm_engine *pm = dev_priv-engine.pm;
+ uint32_t status;
int ret;
if (perflvl == pm-cur)
@@ -68,13 +69,58 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
}
}
+ /* TODO: Wait for vblank */
+
+ /* Disable interrupts */
+ nv_wr32(dev, 0x140, 0);
+
+ /* Pause the engines, if possible */
+ if (dev_priv-engine.fifo.pause(dev)) {
+ ret = -EIO;
+ goto out;
+ }
+ if (dev_priv-engine.graph.pause(dev)) {
+ ret = -EIO;
+ goto out;
+ }
+
+ /* Disable the PFIFO cache pulling */
+ status = nv_rd32(dev, 0x003250);
+ nv_wr32(dev, 0x003250, status0xfffe);
+
+ /* Disable the PFIFO cache dma push */
+ status = nv_rd32(dev, 0x003220);
+ nv_wr32(dev, 0x003220, status0xfffe);
+
+ /* Change the clocks */
nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl-core);
nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl-shader);
nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl-memory);
nouveau_pm_clock_set(dev, perflvl, PLL_UNK05, perflvl-unk05);
+ /* Wait for PLLs to stabilize */
+ udelay(100);
+
pm-cur = perflvl;
- return 0;
+ ret = 0;
+
+out:
+ /* Re-enable the PFIFO cache dma push */
+ status = nv_rd32(dev, 0x003220);
+ nv_wr32(dev, 0x003220, status|0x1);
+
+ /* Re-enable the PFIFO cache pulling */
+ status = nv_rd32(dev, 0x003250);
+ nv_wr32(dev, 0x003250, status|0x1);
+
+ /* Un-pause the engines */
+ dev_priv-engine.fifo.unpause(dev);
+ dev_priv-engine.graph.unpause(dev);
+
+ /* Re-enable interrupts */
+ nv_wr32(dev, 0x140, 1);
+
+ return ret;
}
static int
@@ -108,7 +154,7 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile)
return -EINVAL;
}
- NV_INFO(dev, setting performance level: %s\n, profile);
+ NV_INFO(dev, setting performance level: %s, profile);
return nouveau_pm_perflvl_set(dev, perflvl);
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 1b42541..346b77a 100644
--- a/drivers/gpu/drm/nouveau
Re: [Nouveau] Add pause/unpause methods for PFIFO PGRAPH. Use them to get stable clock changes
Hi, Here is an updated version, all in one patch. When we agree on the code, I'll split it into 3 patches. The new code is way better. As suggested on IRC, I also disable IRQs and PFIFO cache pull and push. Please have a look and test it. This patch needs to get upstream as it gives a reliable way to change the clock even in the middle of a game. It is not perfect yet, changing the clocks too often (like several thousand of times) lead to an hung card :) Regards, Martin ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] Add pause/unpause methods for PFIFO PGRAPH. Use them to get stable clock changes
Hi,
Here is an updated set of patches (in regards on comments got on IRC and
an handling error when using several channels).
These updated patch allow me to run 5 glxgears at the same time and
reclock the card almost 100 times per second without crashing.
Don't panic if you get theses in your logs:
PGRAPH: wait for idle fail: 0103!
PGRAPH: PGRAPH paused while running a ctxprog, NV40_PGRAPH_CTXCTL_0310 =
0x11
It means that we tried to reclock during a context switch. It would be
safe to continue as when the program is at 0x11, it means it waits for
another process (which is stopped because we stopped PFIFO before). I
could allow to get this value (ie continue and clock), but if someone
changes the ctxprog, he would have to update it here.
For the moment, I don't mind if from time to time, setting the clocks fail.
Waiting for your comments.
Regards,
Martin
From a219259d5ea46fb18f8e36c6c5a2f9e9e63fe53e Mon Sep 17 00:00:00 2001
From: Martin Peres martin.pe...@ensi-bourges.fr
Date: Wed, 29 Sep 2010 14:56:37 +0200
Subject: [PATCH 1/3] Add pause/unpause methods to the PFIFO engine
---
drivers/gpu/drm/nouveau/nouveau_drv.h |8
drivers/gpu/drm/nouveau/nouveau_reg.h |1 +
drivers/gpu/drm/nouveau/nouveau_state.c | 14 ++
drivers/gpu/drm/nouveau/nv50_fifo.c | 18 ++
4 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 591254e..c256c0a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -304,6 +304,9 @@ struct nouveau_fifo_engine {
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
int (*unload_context)(struct drm_device *);
+
+ int (*pause)(struct drm_device *);
+ int (*unpause)(struct drm_device *);
};
struct nouveau_pgraph_object_method {
@@ -339,6 +342,9 @@ struct nouveau_pgraph_engine {
void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
uint32_t size, uint32_t pitch);
+
+ int (*pause)(struct drm_device *);
+ int (*unpause)(struct drm_device *);
};
struct nouveau_display_engine {
@@ -1036,6 +1042,8 @@ extern int nv50_fifo_create_context(struct nouveau_channel *);
extern void nv50_fifo_destroy_context(struct nouveau_channel *);
extern int nv50_fifo_load_context(struct nouveau_channel *);
extern int nv50_fifo_unload_context(struct drm_device *);
+extern int nv50_fifo_pause(struct drm_device *);
+extern int nv50_fifo_unpause(struct drm_device *);
/* nvc0_fifo.c */
extern int nvc0_fifo_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 1b42541..ee6dae1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -701,6 +701,7 @@
#define NV50_PGRAPH 0x0040
#define NV50_PGRAPH__LEN 0x1
#define NV50_PGRAPH__ESIZE 0x1
+#define NV50_PFIFO_FREEZE 0x2504
#define NV50_PDISPLAY0x0061
#define NV50_PDISPLAY_OBJECTS0x00610010
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 75bce91..cfc34f5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -86,6 +86,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine-fifo.destroy_context = nv04_fifo_destroy_context;
engine-fifo.load_context = nv04_fifo_load_context;
engine-fifo.unload_context = nv04_fifo_unload_context;
+ engine-fifo.pause = NULL;
+ engine-fifo.unpause = NULL;
engine-display.early_init = nv04_display_early_init;
engine-display.late_takedown = nv04_display_late_takedown;
engine-display.create = nv04_display_create;
@@ -140,6 +142,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine-fifo.destroy_context = nv10_fifo_destroy_context;
engine-fifo.load_context = nv10_fifo_load_context;
engine-fifo.unload_context = nv10_fifo_unload_context;
+ engine-fifo.pause = NULL;
+ engine-fifo.unpause = NULL;
engine-display.early_init = nv04_display_early_init;
engine-display.late_takedown = nv04_display_late_takedown;
engine-display.create = nv04_display_create;
@@ -194,6 +198,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine-fifo.destroy_context = nv10_fifo_destroy_context;
engine-fifo.load_context = nv10_fifo_load_context;
engine-fifo.unload_context = nv10_fifo_unload_context;
+ engine-fifo.pause = NULL;
+ engine-fifo.unpause = NULL;
engine-display.early_init = nv04_display_early_init;
engine-display.late_takedown = nv04_display_late_takedown
[Nouveau] Add pause/unpause methods for PFIFO PGRAPH. Use them to get stable clock changes
Hi,
With these patches, I get reliable clock changes on my nv86. It should
work from nv50 to nvc0 (non-included).
Now, we need to wait for vblank. This is on my TODO but if someone knows
how to do so, please send me pointers to it or implement it yourself :)
Regards,
Martin
From a219259d5ea46fb18f8e36c6c5a2f9e9e63fe53e Mon Sep 17 00:00:00 2001
From: Martin Peres martin.pe...@ensi-bourges.fr
Date: Wed, 29 Sep 2010 14:56:37 +0200
Subject: [PATCH 1/3] Add pause/unpause methods to the PFIFO engine
Signed-off-by: Martin Peres martin.pe...@ensi-bourges.fr
---
drivers/gpu/drm/nouveau/nouveau_drv.h |8
drivers/gpu/drm/nouveau/nouveau_reg.h |1 +
drivers/gpu/drm/nouveau/nouveau_state.c | 14 ++
drivers/gpu/drm/nouveau/nv50_fifo.c | 18 ++
4 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 591254e..c256c0a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -304,6 +304,9 @@ struct nouveau_fifo_engine {
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
int (*unload_context)(struct drm_device *);
+
+ int (*pause)(struct drm_device *);
+ int (*unpause)(struct drm_device *);
};
struct nouveau_pgraph_object_method {
@@ -339,6 +342,9 @@ struct nouveau_pgraph_engine {
void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
uint32_t size, uint32_t pitch);
+
+ int (*pause)(struct drm_device *);
+ int (*unpause)(struct drm_device *);
};
struct nouveau_display_engine {
@@ -1036,6 +1042,8 @@ extern int nv50_fifo_create_context(struct nouveau_channel *);
extern void nv50_fifo_destroy_context(struct nouveau_channel *);
extern int nv50_fifo_load_context(struct nouveau_channel *);
extern int nv50_fifo_unload_context(struct drm_device *);
+extern int nv50_fifo_pause(struct drm_device *);
+extern int nv50_fifo_unpause(struct drm_device *);
/* nvc0_fifo.c */
extern int nvc0_fifo_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 1b42541..ee6dae1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -701,6 +701,7 @@
#define NV50_PGRAPH 0x0040
#define NV50_PGRAPH__LEN 0x1
#define NV50_PGRAPH__ESIZE 0x1
+#define NV50_PFIFO_FREEZE 0x2504
#define NV50_PDISPLAY0x0061
#define NV50_PDISPLAY_OBJECTS0x00610010
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 75bce91..cfc34f5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -86,6 +86,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine-fifo.destroy_context = nv04_fifo_destroy_context;
engine-fifo.load_context = nv04_fifo_load_context;
engine-fifo.unload_context = nv04_fifo_unload_context;
+ engine-fifo.pause = NULL;
+ engine-fifo.unpause = NULL;
engine-display.early_init = nv04_display_early_init;
engine-display.late_takedown = nv04_display_late_takedown;
engine-display.create = nv04_display_create;
@@ -140,6 +142,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine-fifo.destroy_context = nv10_fifo_destroy_context;
engine-fifo.load_context = nv10_fifo_load_context;
engine-fifo.unload_context = nv10_fifo_unload_context;
+ engine-fifo.pause = NULL;
+ engine-fifo.unpause = NULL;
engine-display.early_init = nv04_display_early_init;
engine-display.late_takedown = nv04_display_late_takedown;
engine-display.create = nv04_display_create;
@@ -194,6 +198,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine-fifo.destroy_context = nv10_fifo_destroy_context;
engine-fifo.load_context = nv10_fifo_load_context;
engine-fifo.unload_context = nv10_fifo_unload_context;
+ engine-fifo.pause = NULL;
+ engine-fifo.unpause = NULL;
engine-display.early_init = nv04_display_early_init;
engine-display.late_takedown = nv04_display_late_takedown;
engine-display.create = nv04_display_create;
@@ -248,6 +254,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine-fifo.destroy_context = nv10_fifo_destroy_context;
engine-fifo.load_context = nv10_fifo_load_context;
engine-fifo.unload_context = nv10_fifo_unload_context;
+ engine-fifo.pause = NULL;
+ engine-fifo.unpause = NULL;
engine-display.early_init = nv04_display_early_init;
engine-display.late_takedown = nv04_display_late_takedown;
engine-display.create = nv04_display_create;
@@ -305,6 +313,8 @@ static int
Re: [Nouveau] [RFC] Initial power management vbios parsing, voltage clock setting to nouveau.
Le 15/09/2010 14:58, Robert Kaiser a écrit : On an only slightly related note, what's the recommended way to read out the temperature of the GPU when using nouveau? (I have a NV4B card, but I think I read this is mostly the same for all NVidias, right?) There is no way to get the temperature using nouveau at the moment. This feature should land in nouveau git some time this week. Reading the temperature is not as straightforward as just reading a register. It works that way on nv84+, for earlier cards, you need to parse the vbios to set-up the sensor and then read the temperature (and change the value with some additional little calcultations). The documentation should be available soon, I'm working on merging all the doc we have. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [RFC] Initial power management vbios parsing, voltage clock setting to nouveau.
Le 15/09/2010 14:33, C. Bergström a écrit : If you're an end users also feel free to pull the branch directly.. http://github.com/pathscale/pscnv/tree/pm-wip We're in #pathscale if you need more help or hit bugs.. It is not a good idea as libpdrm isn't mainstream yet. As Ben said, it should be developped in nouveau. Pscnv isn't ready for X users yet even though we are working on it. If people want to, I'll upload a complete kernel somewhere for end users to test. As for the moment, I only need developpers people who know what they are doing, not end-users. Anyway, count on me to keep pscnv nouveau in sync as for power management. thanks ./C ps (Have a great trip Martin and good luck at the conference!) Thanks :) ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [RFC] Initial power management vbios parsing, voltage clock setting to nouveau.
Hi folks, I've been messing with PM management for a few days and I've accumulated an interesting volume of code. I am now interested in comments on the overall architecture. For example, in this patch, I implement a proposition on how to split nouveau_bios.c I would really like you to comment. I have also introduced nouveau_pm.[hc] along with vbios/vbios_pm.[ch]. Another thing I would be interested in is the vbios parsing testing. At the moment, it should work from nv40 to at least nv96 but it has really been tested only on an nv86 and an nv96. I'm expecting a lot of bug report. Power mode setting is _not recommended for anything other than dev testing_. There is still work to be done: - Clock voltage: It needs testing. - Memory timings: It is being REed by RSpliet (please help him, he should be able to provide directions). - Fan control: I have no information on this. Despite these lacks, you should be able to safely try to downclock your card though. That's good news for laptop users, isn't it? Please acknowledge that this work is almost entirely based on others's RE work and documentation work. Xexaxo's work has been impressive. RSpliet is also to be thanked as he is working on getting memory timing support. Darktama has also done some nice RE, we'll see how to merge his work. My work here has just been to implement the docs. On a side note, I would like to say I will be out for 5 days to the XDS 2010. So, if you have questions I should discuss with some devs there, feel free to ask. Best regards, Martin Peres (aka mupuf), an happy new nouveau dev How to help for the vbios parsing ? Thanks for wanting to help :) First, grab the patch I've joined to this mail. It should cleanly apply on nouveau's master branch. Compile, Install Reboot. $ cat /sys/class/drm/card0/device/pm_status and compare the values to # nvclock -i If it differs, please follow the instructions here: http://nouveau.freedesktop.org/wiki/PowerManagementDumps If it works, then, you may want to try changing the clocks. How to test clock/voltage setting ? Do not attempt anything if the vbios parsing is wrong, really. If it did work as intended, you can continue. ** Warning ** Do not try to upclock your card, nothing good will happen. While playing with clocks, always check the current temperature First, kill X (for safety reasons). Then look for the wanted mode by doing: $ cat /sys/class/drm/card0/device/pm_mode It should give you a result like: --- PM Modes --- 0: core 169 MHz/shader 338 MHz/memory 100 MHz/1150 mV *1: core 275 MHz/shader 550 MHz/memory 301 MHz/1150 mV 2: core 400 MHz/shader 800 MHz/memory 600 MHz/1200 mV The * means it is the currently used mode (it may also not be detected). In this example, you should only stay between mode 0 and 1. To set the wanted PM mode, please do so: # echo 0 /sys/class/drm/card0/device/pm_mode The command above will change the mode to the first mode. There is another file for voltage control at /sys/class/drm/card0/device/pm_voltage that works the exact same way as pm_mode. The other sysfs entries (temperature related) should be useless to you as they are just here for future work). You're done, have fun. From 38aba214268ecd0263b2a49af0698d84f6a364e6 Mon Sep 17 00:00:00 2001 From: Martin Peres martin.pe...@ensi-bourges.fr Date: Wed, 15 Sep 2010 12:59:00 +0200 Subject: [PATCH] Add initial power management vbios parsing, voltage clock setting to nouveau. It is not intented to be used by end-users (if it should be used at all), this commit is meant for devs to check the actual work and comment on it. So, you may wondering what I'm asking you. I simply ask you to check the code and see if you could improve this design. Also, you can try: $ cat /sys/class/drm/card0/device/pm_status and comparing it to # nvclock -i. If it doesn't match, please provide us with power management dumps kernel logs: http://nouveau.freedesktop.org/wiki/PowerManagementDumps If it does match, report your success story also :) Known issues: As no memory timing parsing/get/set is implemented yet (RSPliet has been working on it but it is not complete yet), your card will likely hang if you upclock the memory. Lowering the clocks should work fine though: echo 0 /sys/class/drm/card0/device/pm_mode WARNING: Use at your own risks. Please stop your machine after having fun with this and reboot it after a minute in order to flush everything in the card. Keep in mind how experimental it is ;) Ack: Most of this work is based on xexaxo's documentation work and useful advices. --- drivers/gpu/drm/nouveau/Makefile |2 +- drivers/gpu/drm/nouveau/nouveau_bios.c | 67 +++- drivers/gpu/drm/nouveau/nouveau_bios.h | 41 ++ drivers/gpu/drm/nouveau/nouveau_biosP.h | 44 ++ drivers/gpu/drm/nouveau/nouveau_drv.h|2 + drivers/gpu/drm/nouveau/nouveau_pm.c | 677 ++ drivers/gpu
Re: [Nouveau] Re-enable dithering after commit a7b9f9e5adef276c25584e28ce9e520045ff048b
Le 16/06/2010 09:38, Martin Peres a écrit : Hi everyone, After commit a7b9f9e5adef276c25584e28ce9e520045ff048b, dithering has disappeared on LVDS (for those who needed it). ThibG on IRC has bisected this behaviour to a7b9f9e5adef276c25584e28ce9e520045ff048b. Here is a patch that re-enables it. Please comment on it. Martin Well, too late, Jerez already pushed a patch to do that :) Do you have any idea of why it took almost 10 hours between the moment I sent this mail and the moment I actually received it from the list ? Is there a manual approbation somewhere to get rid of the spam ? Thanks to Jerez for the patch anyway :) It works just as great and is better designed. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] Gart to vram/vram to gart transfers broken on NVS 140M
Le 22/04/2010 12:20, Stephane Marchesin a écrit : On Thu, Apr 22, 2010 at 03:13, Martin Peresmartin.pe...@free.fr wrote: Hi Nouveau folks, I've been encountering some corruption on pixmaps for a while now, and it seems like the problem comes from the DFS/UTS (Download From Screen / Upload To Screen). In fact, I'm pretty sure the problem comes from there as screenshots are garbled and so does a few more things. I may have time to dig this up, where should I start, is there some documentation on the NVS 140M ? Where is the gart2vram code located ? Do you have any idea of where could be the problem ? If you really think that's UTS/DFS, edit nouveau_exa.c and disable them (change the UTS/DFS functions to return FALSE, that'll trigger fallbacks to sw copying). Stephane In fact, following your advice triggers a lot more corruption. So, the problem comes from elsewhere. My corruption problem seems like there is a codepath that copy a pixmap with wrong height and width. I'll dig into it. I'll keep in touch. Martin ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] Gart to vram/vram to gart transfers broken on NVS 140M
Hi Nouveau folks, I've been encountering some corruption on pixmaps for a while now, and it seems like the problem comes from the DFS/UTS (Download From Screen / Upload To Screen). In fact, I'm pretty sure the problem comes from there as screenshots are garbled and so does a few more things. I may have time to dig this up, where should I start, is there some documentation on the NVS 140M ? Where is the gart2vram code located ? Do you have any idea of where could be the problem ? Thanks, Martin ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] GtkPerf: Non linear Add text execution time
Hello everyone, I am a daily tester of the nouveau driver on my (nVidia Corporation Quadro NVS 140M (rev a1)). Today, when trying to make compiz crash, I have tried to execute a lot of tests at the same time with both 2D and 3D. Well, I didn't bump into any crashes but I have discovered a really annoying performance issue. Indeed, the gtkTextView - Add Text of gtkperf has non-linear execution times: GtkPerf 0.40 - Starting testing: Fri Mar 12 13:57:19 2010 GtkTextView - Add text - time: 0,03 -- 10 executions --- Total time: 0,04 GtkPerf 0.40 - Starting testing: Fri Mar 12 13:57:28 2010 GtkTextView - Add text - time: 0,99 -- 100 executions --- Total time: 0,99 GtkPerf 0.40 - Starting testing: Fri Mar 12 13:57:34 2010 GtkTextView - Add text - time: 88,19 -- 1000 executions --- Total time: 88,19 So, if results were linear, we would have had a 3 seconds execution time with 1000 executions while we got 88.19s. Just to give you an idea. I was testing with even more iterations and adding just one single text can take more than one second. I don't know if it is a performance regression or if it has always been here but this could explain some slow code-path I sometime encounter using nouveau on lengthy webpages. What do you think about it ? Also, one last question, do you have any idea why KWin doesn't let me activate the composite. Do you think the problem is from KWin or does Nouveau misses a few features to get it working ? Anyway, I am an happy tester of the nouveau stack and I would be glad to help you in running tests/applying patches on my card. Martin ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [TEST REQUEST] NV50/NV8x/NV9x/NVAx ctxprog and ctxvals generator
Le 24/02/2010 09:22, Marcin Kościelnicki a écrit : Aiii... ok, I accidentally introduced a bug in pre-NVA0 branch during last- minute cleanups... I just uploaded a new version at the same address that should fix that issue. Btw, to anyone reporting success/failure with the generator: please include your chipset code number [NV50, NV96, NVA5, etc.]. If you don't know what it is, just report the hex number in Detected an NV50 generation card (0x086900a2) line Sorry for that screwup Marcin Kościelnicki It works better now, I could not spot any regression. Thanks, Martin ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [TEST REQUEST] NV50/NV8x/NV9x/NVAx ctxprog and ctxvals generator
Hello, Sorry for not answering to the right message, I've just joined the mailing list. I've tried this patch on my Quadro NVS 140M and it fails to load KDM. It shows the background but fails to show the credential edit boxes. It seems like the computer is locked up though the mouse can still move (can't do any VT switches) and I still can ssh on it. Needless to say this works without the patch ;) Martin dmesg: [drm] Initialized drm 1.1.0 20060810 nouveau :01:00.0: power state changed by ACPI to D0 nouveau :01:00.0: PCI INT A - GSI 16 (level, low) - IRQ 16 nouveau :01:00.0: setting latency timer to 64 [drm] nouveau :01:00.0: failed to evaluate _DSM: 5 [drm] nouveau :01:00.0: Detected an NV50 generation card (0x086900a2) [drm] nouveau :01:00.0: Attempting to load BIOS image from PRAMIN [drm] nouveau :01:00.0: ... appears to be valid [drm] nouveau :01:00.0: BIT BIOS found [drm] nouveau :01:00.0: Bios version 60.86.3e.00 [drm] nouveau :01:00.0: TMDS table revision 2.0 not currently supported [drm] nouveau :01:00.0: BIT table 'd' not found [drm] nouveau :01:00.0: Found Display Configuration Block version 4.0 [drm] nouveau :01:00.0: DCB connector table: VHER 0x40 5 14 2 [drm] nouveau :01:00.0: 0: 0x0040: type 0x40 idx 0 tag 0xff [drm] nouveau :01:00.0: 1: 0x0100: type 0x00 idx 1 tag 0xff [drm] nouveau :01:00.0: 2: 0x1231: type 0x31 idx 2 tag 0x07 [drm] nouveau :01:00.0: 3: 0x0311: type 0x11 idx 3 tag 0xff [drm] nouveau :01:00.0: Raw DCB entry 0: 01000323 00010034 [drm] nouveau :01:00.0: Raw DCB entry 1: 02811300 0028 [drm] nouveau :01:00.0: Raw DCB entry 2: 02822312 00010030 [drm] nouveau :01:00.0: Raw DCB entry 3: 014333f1 0080c080 [drm] nouveau :01:00.0: Raw DCB entry 4: 000e [drm] nouveau :01:00.0: Parsing VBIOS init table 0 at offset 0xDD0F [drm] nouveau :01:00.0: Parsing VBIOS init table 1 at offset 0xE04F [drm] nouveau :01:00.0: Parsing VBIOS init table 2 at offset 0xEAA4 [drm] nouveau :01:00.0: Parsing VBIOS init table 3 at offset 0xEB96 [drm] nouveau :01:00.0: Parsing VBIOS init table 4 at offset 0xED83 [drm] nouveau :01:00.0: Parsing VBIOS init table at offset 0xEDE8 [drm] nouveau :01:00.0: 0xEDE8: Condition still not met after 20ms, skipping following opcodes [drm] nouveau :01:00.0: 0xCE7E: parsing output script 0 [drm] nouveau :01:00.0: 0xCFF4: parsing output script 0 [drm] nouveau :01:00.0: 0xC66A: parsing output script 0 [TTM] Zone kernel: Available graphics memory: 443326 kiB. [TTM] Zone highmem: Available graphics memory: 1036578 kiB. [drm] nouveau :01:00.0: 128 MiB VRAM [drm] nouveau :01:00.0: 512 MiB GART (aperture) [drm] nouveau :01:00.0: Allocating FIFO number 1 [drm] nouveau :01:00.0: nouveau_channel_alloc: initialised FIFO 1 [drm] nouveau :01:00.0: Detected a LVDS output [drm] nouveau :01:00.0: Detected a DAC output [drm] nouveau :01:00.0: Detected a TMDS output [drm] nouveau :01:00.0: DCB encoder 1 unknown [drm] nouveau :01:00.0: Detected a LVDS connector [drm] nouveau :01:00.0: Detected a VGA connector [drm] nouveau :01:00.0: Detected a DVI-D connector [drm] nouveau :01:00.0: allocated 1280x800 fb: 0x4025, bo f6813200 [drm] LVDS-7: set mode 1280x800 1a [drm] nouveau :01:00.0: 0xCE82: parsing output script 1 [drm] nouveau :01:00.0: 0xCCE3: parsing clock script 0 Console: switching to colour frame buffer device 160x50 fb0: nouveaufb frame buffer device registered panic notifier [drm] Initialized nouveau 0.0.16 20090420 for :01:00.0 on minor 0 [drm] nouveau :01:00.0: 0xCE41: parsing clock script 1 ... # When loading KDM [drm] nouveau :01:00.0: Allocating FIFO number 2 [drm] nouveau :01:00.0: nouveau_channel_alloc: initialised FIFO 2 [drm] nouveau :01:00.0: Allocating FIFO number 3 [drm] nouveau :01:00.0: nouveau_channel_alloc: initialised FIFO 3 # Stuck ! ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
