from:"Samuel Pitoiset"

[Nouveau] [PATCH] perfmon: do not forget to destroy the engine context

2014-07-21 Thread Samuel Pitoiset

This fixes a crash when we reload Nouveau DRM.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 nvkm/engine/perfmon/base.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/nvkm/engine/perfmon/base.c b/nvkm/engine/perfmon/base.c
index e9c5e51..7481003 100644
--- a/nvkm/engine/perfmon/base.c
+++ b/nvkm/engine/perfmon/base.c
@@ -303,6 +303,7 @@ nouveau_perfctx_dtor(struct nouveau_object *object)
 {
struct nouveau_perfmon *ppm = (void *)object-engine;
mutex_lock(nv_subdev(ppm)-mutex);
+   nouveau_engctx_destroy(ppm-context-base);
ppm-context = NULL;
mutex_unlock(nv_subdev(ppm)-mutex);
 }
-- 
2.0.0

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[Nouveau] Prepare the way for performance counters in perfmon

2014-09-15 Thread Samuel Pitoiset

Hi folks,

This set of patches is just for clearing the way before introducing
the infrastructure for performance counters in perfmon.

I'll try to publish a new version of my kernel interface based on nvif
in a couple of days.

See you.

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[Nouveau] [PATCH 3/3] perfmon: remove PDAEMON signals

2014-09-15 Thread Samuel Pitoiset

As discussed with Martin Peres, PDAEMON signals should be exposed
through sysfs and not managed by the perfmon engine which is only
used for performance counters.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/Kbuild   |   1 -
 drm/core/engine/perfmon/daemon.c |   1 -
 nvkm/engine/perfmon/Makefile.am  |   1 -
 nvkm/engine/perfmon/daemon.c | 109 ---
 nvkm/engine/perfmon/nva3.c   |  20 +--
 nvkm/engine/perfmon/nvc0.c   |   6 ---
 nvkm/engine/perfmon/nve0.c   |   7 ---
 nvkm/engine/perfmon/nvf0.c   |   5 --
 nvkm/engine/perfmon/priv.h   |   4 --
 nvkm/include/engine/perfmon.h|   4 --
 10 files changed, 1 insertion(+), 157 deletions(-)
 delete mode 12 drm/core/engine/perfmon/daemon.c
 delete mode 100644 nvkm/engine/perfmon/daemon.c

diff --git a/drm/Kbuild b/drm/Kbuild
index 949a034..b63c0ed 100644
--- a/drm/Kbuild
+++ b/drm/Kbuild
@@ -319,7 +319,6 @@ nouveau-y += core/engine/mpeg/nv44.o
 nouveau-y += core/engine/mpeg/nv50.o
 nouveau-y += core/engine/mpeg/nv84.o
 nouveau-y += core/engine/perfmon/base.o
-nouveau-y += core/engine/perfmon/daemon.o
 nouveau-y += core/engine/perfmon/nv40.o
 nouveau-y += core/engine/perfmon/nv50.o
 nouveau-y += core/engine/perfmon/nv84.o
diff --git a/drm/core/engine/perfmon/daemon.c b/drm/core/engine/perfmon/daemon.c
deleted file mode 12
index 3351142..000
--- a/drm/core/engine/perfmon/daemon.c
+++ /dev/null
@@ -1 +0,0 @@
-../../../../nvkm/engine/perfmon/daemon.c
\ No newline at end of file
diff --git a/nvkm/engine/perfmon/Makefile.am b/nvkm/engine/perfmon/Makefile.am
index f6e2279..48e3801 100644
--- a/nvkm/engine/perfmon/Makefile.am
+++ b/nvkm/engine/perfmon/Makefile.am
@@ -1,7 +1,6 @@
 noinst_LTLIBRARIES = libperfmon.la
 
 libperfmon_la_SOURCES = base.c \
-   daemon.c \
nv40.c \
nv50.c \
nv84.c \
diff --git a/nvkm/engine/perfmon/daemon.c b/nvkm/engine/perfmon/daemon.c
deleted file mode 100644
index 50696cc..000
--- a/nvkm/engine/perfmon/daemon.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the Software),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include priv.h
-
-static void
-pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-struct nouveau_perfctr *ctr)
-{
-   u32 mask = 0x;
-   u32 ctrl = 0x0001;
-   int i;
-
-   for (i = 0; i  ARRAY_SIZE(ctr-signal)  ctr-signal[i]; i++)
-   mask |= 1  (ctr-signal[i] - dom-signal);
-
-   nv_wr32(ppm, 0x10a504 + (ctr-slot * 0x10), mask);
-   nv_wr32(ppm, 0x10a50c + (ctr-slot * 0x10), ctrl);
-   nv_wr32(ppm, 0x10a50c + (ppm-last * 0x10), 0x0003);
-}
-
-static void
-pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
-struct nouveau_perfctr *ctr)
-{
-   ctr-ctr = ppm-pwr[ctr-slot];
-   ctr-clk = ppm-pwr[ppm-last];
-}
-
-static void
-pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
-{
-   int i;
-
-   for (i = 0; i = ppm-last; i++) {
-   ppm-pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
-   nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x8000);
-   }
-}
-
-static const struct nouveau_funcdom
-pwr_perfctr_func = {
-   .init = pwr_perfctr_init,
-   .read = pwr_perfctr_read,
-   .next = pwr_perfctr_next,
-};
-
-const struct nouveau_specdom
-nva3_perfmon_pwr[] = {
-   { 0x20, (const struct nouveau_specsig[]) {
-   { 0x00, pwr_gr_idle },
-   { 0x04, pwr_bsp_idle },
-   { 0x05, pwr_vp_idle },
-   { 0x06, pwr_ppp_idle },
-   { 0x13, pwr_ce0_idle },
-   {}
-   }, pwr_perfctr_func },
-   {}
-};
-
-const struct

[Nouveau] [PATCH 2/3] perfmon: remove unused nouveau_perfsig_wrap() function

2014-09-15 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 nvkm/engine/perfmon/base.c | 20 
 nvkm/engine/perfmon/priv.h |  3 ---
 2 files changed, 23 deletions(-)

diff --git a/nvkm/engine/perfmon/base.c b/nvkm/engine/perfmon/base.c
index 5fa45e1..b74734e 100644
--- a/nvkm/engine/perfmon/base.c
+++ b/nvkm/engine/perfmon/base.c
@@ -80,26 +80,6 @@ nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char 
*name, u32 size,
return nouveau_perfsig_find_(dom, name, size);
 }
 
-struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name,
-struct nouveau_perfdom **pdom)
-{
-   struct nouveau_perfsig *sig;
-   struct nouveau_perfctr *ctr;
-
-   sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom);
-   if (!sig)
-   return NULL;
-
-   ctr = kzalloc(sizeof(*ctr), GFP_KERNEL);
-   if (ctr) {
-   ctr-signal[0] = sig;
-   ctr-logic_op = 0x;
-   }
-
-   return ctr;
-}
-
 
/***
  * Perfmon object classes
  
**/
diff --git a/nvkm/engine/perfmon/priv.h b/nvkm/engine/perfmon/priv.h
index 0ac8714..9e27ff5 100644
--- a/nvkm/engine/perfmon/priv.h
+++ b/nvkm/engine/perfmon/priv.h
@@ -31,9 +31,6 @@ struct nouveau_perfsig {
 };
 
 struct nouveau_perfdom;
-struct nouveau_perfctr *
-nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *,
-struct nouveau_perfdom **);
 
 struct nouveau_specdom {
u16 signal_nr;
-- 
2.0.0

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[Nouveau] [PATCH 1/3] lib: fix devices selection using -a

2014-09-15 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 lib/kern.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/kern.c b/lib/kern.c
index 930cd35..7e8f3e9 100644
--- a/lib/kern.c
+++ b/lib/kern.c
@@ -173,7 +173,7 @@ drm_client_init(const char *name, u64 device, const char 
*cfg,
if (ret = -ENOMEM, !(drm = *ppriv = malloc(sizeof(*drm
goto fail;
 
-   for (minor = DRM_RENDER_MIN; minor = DRM_RENDER_MAX; minor++) {
+   for (minor = DRM_RENDER_MIN + device; minor = DRM_RENDER_MAX; minor++) 
{
snprintf(path, sizeof(path), /dev/dri/renderD%d, minor);
if ((drm-fd = open(path, O_RDWR, 0))  0)
continue;
-- 
2.0.0

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Re: [Nouveau] [RFC PATCH 2/3] dvfs: add support for GK20A

2014-12-18 Thread Samuel Pitoiset


On 12/18/2014 11:25 AM, Ben Skeggs wrote:

On Thu, Dec 18, 2014 at 8:13 PM, Vince Hsu vin...@nvidia.com wrote:

Hello Ben,

On 12/18/2014 05:34 PM, Ben Skeggs wrote:

On Thu, Dec 18, 2014 at 4:28 PM, Vince Hsu vin...@nvidia.com wrote:

This patch creates a subdev for DVFS (Dynamic Voltage and Frequency
Scaling)
support in Nouveau. This subdev refers to the status information provided
by
the NVIDIA hardware and tries to adjust the performance level based on
the
calculated target. Only the GK20A is supported right now.

Hey Vince,

I'd not make a new subdev, but implement this in the PMU (PWR
currently) subdev.  The ucode that's supposed to be running there can
do the performance monitoring in a more complex implementation, and
it's PMU counters you're touching to get the usage stats :)  But the
simpler on-host implementation is totally fine.

Yeah, I know we have the counters defined in daemon.c. Martin reminded me
that Roy had a patch to remove that, sorry that I could not find the link
now. Another reason I did not use the nouveau_specsig is because I had to
create some nvif structures to access the counters and that's not
straightforward. I'm happy to hear you're fine with the on-host
implementation. :)


Hey Vince,

It's not Roy but me who had submitted a patch which removes PDAEMON 
signals. :-)


However, the patch is not ready to be upstream because we don't have any 
other ways to expose these performance counters.


Currently, I'm working on perfmon and nvif to expose hardware events to 
the userspace for NV50. I hope to submit the bunch of patches as soon as 
possible but unfortunately,

I don't have my full time on this, so it takes more time than expected.



I will move all to PWR subdev in the next version.


The current base PMU implementation tries to do a lot of stuff that
you don't need, just override the implementation entirely for GK20A
for now if that's easier than reworking it.

So currently there is no dGPU using the PMU? I just don't want to break any
dGPU functions. ;)

We upload a custom firmware to it, which we (currently) only use as a
script interpreter for memory clock changes.  But for your needs right
now, it'd be fine to ignore all the common code there for GK20A.



Aside from the subdev move, it looks good so far to me.  Glad to see
the CLK stuff isn't totally useless, despite it needing a *lot* of
work.

BTW, can we add some execution time information for pstate? I mean something
like /sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state. I know we
don't want to change the user space ABI though.

Thanks,
Vince



Thanks,
Ben.


Signed-off-by: Vince Hsu vin...@nvidia.com
---
   drm/Kbuild |   2 +
   drm/core/include/subdev/dvfs.h |   1 +
   drm/core/subdev/dvfs/base.c|   1 +
   drm/core/subdev/dvfs/gk20a.c   |   1 +
   drm/core/subdev/dvfs/priv.h|   1 +
   nvkm/engine/device/nve0.c  |   2 +
   nvkm/include/core/device.h |   1 +
   nvkm/include/subdev/dvfs.h |  30 
   nvkm/subdev/Makefile.am|   5 +-
   nvkm/subdev/dvfs/Makefile.am   |   6 ++
   nvkm/subdev/dvfs/base.c| 129 ++
   nvkm/subdev/dvfs/gk20a.c   | 156
+
   nvkm/subdev/dvfs/priv.h|  43 
   13 files changed, 376 insertions(+), 2 deletions(-)
   create mode 12 drm/core/include/subdev/dvfs.h
   create mode 12 drm/core/subdev/dvfs/base.c
   create mode 12 drm/core/subdev/dvfs/gk20a.c
   create mode 12 drm/core/subdev/dvfs/priv.h
   create mode 100644 nvkm/include/subdev/dvfs.h
   create mode 100644 nvkm/subdev/dvfs/Makefile.am
   create mode 100644 nvkm/subdev/dvfs/base.c
   create mode 100644 nvkm/subdev/dvfs/gk20a.c
   create mode 100644 nvkm/subdev/dvfs/priv.h

diff --git a/drm/Kbuild b/drm/Kbuild
index 061d9faef836..e7eb05e666a0 100644
--- a/drm/Kbuild
+++ b/drm/Kbuild
@@ -227,6 +227,8 @@ nouveau-y += core/subdev/volt/base.o
   nouveau-y += core/subdev/volt/gpio.o
   nouveau-y += core/subdev/volt/nv40.o
   nouveau-y += core/subdev/volt/gk20a.o
+nouveau-y += core/subdev/dvfs/base.o
+nouveau-y += core/subdev/dvfs/gk20a.o

   nouveau-y += core/engine/falcon.o
   nouveau-y += core/engine/xtensa.o
diff --git a/drm/core/include/subdev/dvfs.h
b/drm/core/include/subdev/dvfs.h
new file mode 12
index ..553a6968350b
--- /dev/null
+++ b/drm/core/include/subdev/dvfs.h
@@ -0,0 +1 @@
+../../../../nvkm/include/subdev/dvfs.h
\ No newline at end of file
diff --git a/drm/core/subdev/dvfs/base.c b/drm/core/subdev/dvfs/base.c
new file mode 12
index ..296334ee52d1
--- /dev/null
+++ b/drm/core/subdev/dvfs/base.c
@@ -0,0 +1 @@
+../../../../nvkm/subdev/dvfs/base.c
\ No newline at end of file
diff --git a/drm/core/subdev/dvfs/gk20a.c b/drm/core/subdev/dvfs/gk20a.c
new file mode 12
index ..d05d493e3fc9
--- /dev/null
+++ b/drm/core/subdev/dvfs/gk20a.c
@@ -0,0 +1 @@
+../../../../nvkm/subdev/dvfs/gk20a.c
\ No newline at

Re: [Nouveau] [PATCH 2/2] pm: fix a potential race condition when creating an engine context

2015-05-10 Thread Samuel Pitoiset


* bump *

Ben, could you take a look at the series ?

On 04/14/2015 10:43 PM, Samuel Pitoiset wrote:

There is always the possiblity that the ppm-context pointer would get
partially updated and accidentally would equal ctx. This would allow two
contexts to co-exist, which is not acceptable. Moving the test to the
critical section takes care of this problem.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
Signed-off-by: Martin Peres martin.pe...@free.fr
---
  drm/nouveau/nvkm/engine/pm/base.c | 7 +++
  1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 274457c..4cf36a3 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -358,12 +358,11 @@ nvkm_perfctx_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
mutex_lock(nv_subdev(ppm)-mutex);
if (ppm-context == NULL)
ppm-context = ctx;
-   mutex_unlock(nv_subdev(ppm)-mutex);
-
if (ctx != ppm-context)
-   return -EBUSY;
+   ret = -EBUSY;
+   mutex_unlock(nv_subdev(ppm)-mutex);
  
-	return 0;

+   return ret;
  }
  
  struct nvkm_oclass


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[Nouveau] [PATCH 1/2] pm: prevent freeing the wrong engine context

2015-04-14 Thread Samuel Pitoiset

This fixes a crash when multiple PM engine contexts are created.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
Reviewed-by: Martin Peres martin.pe...@free.fr
---
 drm/nouveau/nvkm/engine/pm/base.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 2006c44..274457c 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -332,9 +332,12 @@ static void
 nvkm_perfctx_dtor(struct nvkm_object *object)
 {
struct nvkm_pm *ppm = (void *)object-engine;
+   struct nvkm_perfctx *ctx = (void *)object;
+
mutex_lock(nv_subdev(ppm)-mutex);
-   nvkm_engctx_destroy(ppm-context-base);
-   ppm-context = NULL;
+   nvkm_engctx_destroy(ctx-base);
+   if (ppm-context == ctx)
+   ppm-context = NULL;
mutex_unlock(nv_subdev(ppm)-mutex);
 }
 
-- 
2.3.5

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[Nouveau] [PATCH 2/2] pm: fix a potential race condition when creating an engine context

2015-04-14 Thread Samuel Pitoiset

There is always the possiblity that the ppm-context pointer would get
partially updated and accidentally would equal ctx. This would allow two
contexts to co-exist, which is not acceptable. Moving the test to the
critical section takes care of this problem.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
Signed-off-by: Martin Peres martin.pe...@free.fr
---
 drm/nouveau/nvkm/engine/pm/base.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 274457c..4cf36a3 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -358,12 +358,11 @@ nvkm_perfctx_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
mutex_lock(nv_subdev(ppm)-mutex);
if (ppm-context == NULL)
ppm-context = ctx;
-   mutex_unlock(nv_subdev(ppm)-mutex);
-
if (ctx != ppm-context)
-   return -EBUSY;
+   ret = -EBUSY;
+   mutex_unlock(nv_subdev(ppm)-mutex);
 
-   return 0;
+   return ret;
 }
 
 struct nvkm_oclass
-- 
2.3.5

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Re: [Nouveau] [Mesa-dev] [PATCH] nv50: allocate more offset space for occlusion queries

2015-04-04 Thread Samuel Pitoiset


Reviewed-by: Samuel Pitoiset samuel.pitoi...@gmail.com

But please, fix the comment in the nv50_query struct, now it is /* base 
+ i * 32 */.


On 04/04/2015 06:00 AM, Ilia Mirkin wrote:

Commit 1a170980a09 started writing to q-data[4]/[5] but kept the
per-query space at 16, which meant that in some cases we would write
past the end of the buffer. Rotate by 32, like nvc0 does.

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Tested-by: Nick Tenney nick.ten...@gmail.com
Cc: 10.4 10.5 mesa-sta...@lists.freedesktop.org
---
  src/gallium/drivers/nouveau/nv50/nv50_query.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c 
b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index e81ac5a..6a23de4 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -116,8 +116,8 @@ nv50_query_create(struct pipe_context *pipe, unsigned type, 
unsigned index)
 q-type = type;
  
 if (q-type == PIPE_QUERY_OCCLUSION_COUNTER) {

-  q-offset -= 16;
-  q-data -= 16 / sizeof(*q-data); /* we advance before query_begin ! */
+  q-offset -= 32;
+  q-data -= 32 / sizeof(*q-data); /* we advance before query_begin ! */
 }
  
 return (struct pipe_query *)q;

@@ -150,8 +150,8 @@ nv50_query_begin(struct pipe_context *pipe, struct 
pipe_query *pq)
  * initialized it to TRUE.
  */
 if (q-type == PIPE_QUERY_OCCLUSION_COUNTER) {
-  q-offset += 16;
-  q-data += 16 / sizeof(*q-data);
+  q-offset += 32;
+  q-data += 32 / sizeof(*q-data);
if (q-offset - q-base == NV50_QUERY_ALLOC_SPACE)
   nv50_query_allocate(nv50, q, NV50_QUERY_ALLOC_SPACE);
  


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Re: [Nouveau] [PATCH] fix a wrong use of a logical operator in drmmode_output_dpms()

2015-05-20 Thread Samuel Pitoiset




On 05/20/2015 07:13 PM, Ilia Mirkin wrote:

This is obviously a bug, but one that has been there for some time.
Please figure out what this is guarding, and confirm that the feature
continues to work.


Sure, but do you have any ideas how to test this part of the DDX ?
It's the first time I play with it...



On Wed, May 20, 2015 at 1:11 PM, Tobias Klausmann
tobias.johannes.klausm...@mni.thm.de wrote:

looks good to me! :)

Feel free to add my R-b.

On 20.05.2015 17:08, Samuel Pitoiset wrote:

This is probably a typo error which has been introduced in 2009...
This fixes the following warning detected by Clang :

drmmode_display.c:907:30: warning: use of logical '' with constant
operand [-Wconstant-logical-operand]
  if (props  (props-flags  DRM_MODE_PROP_ENUM)) {

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
   src/drmmode_display.c | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 7c1d2bb..161bccd 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -904,7 +904,7 @@ drmmode_output_dpms(xf86OutputPtr output, int mode)
 for (i = 0; i  koutput-count_props; i++) {
 props = drmModeGetProperty(drmmode-fd,
koutput-props[i]);
-   if (props  (props-flags  DRM_MODE_PROP_ENUM)) {
+   if (props  (props-flags  DRM_MODE_PROP_ENUM)) {
 if (!strcmp(props-name, DPMS)) {
 mode_id = koutput-props[i];
 drmModeFreeProperty(props);


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[Nouveau] [PATCH RFC 19/20] sw/nv50: add some private functions to factorize code

2015-06-07 Thread Samuel Pitoiset

These functions will be also used by the interface for controlling
performance counters.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/sw/nv50.c | 56 ++-
 1 file changed, 38 insertions(+), 18 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/sw/nv50.c 
b/drm/nouveau/nvkm/engine/sw/nv50.c
index 401fcd7..b7c0227 100644
--- a/drm/nouveau/nvkm/engine/sw/nv50.c
+++ b/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -36,27 +36,58 @@
  
**/
 
 static int
-nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
-   void *args, u32 size)
+nv50_priv_ctxdma_get(struct nv50_sw_chan *chan, u32 name, u32 *ctxdma)
 {
-   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)-parent;
struct nvkm_handle *handle;
int ret = -EINVAL;
 
-   handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args);
+   handle = nvkm_namedb_get(nv_namedb(fifo), name);
if (!handle)
return -ENOENT;
 
if (nv_iclass(handle-object, NV_GPUOBJ_CLASS)) {
struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle-object);
-   chan-vblank.ctxdma = gpuobj-node-offset  4;
+   *ctxdma = gpuobj-node-offset  4;
ret = 0;
}
nvkm_namedb_put(handle);
return ret;
 }
 
+static void
+nv50_priv_ctxdma_flush(struct nv50_sw_chan *chan, u32 channel, u32 ctxdma)
+{
+   struct nv50_sw_priv *priv = (void *)nv_object(chan)-engine;
+   struct nvkm_bar *bar = nvkm_bar(priv);
+
+   nv_wr32(priv, 0x001704, channel);
+   nv_wr32(priv, 0x001710, 0x8000 | ctxdma);
+   bar-flush(bar);
+}
+
+static void
+nv50_priv_ctxdma_wr32(struct nv50_sw_chan *chan, u64 offset, u32 value)
+{
+   struct nv50_sw_priv *priv = (void *)nv_object(chan)-engine;
+
+   if (nv_device(priv)-chipset == 0x50) {
+   nv_wr32(priv, 0x001570, offset);
+   nv_wr32(priv, 0x001574, value);
+   } else {
+   nv_wr32(priv, 0x060010, offset);
+   nv_wr32(priv, 0x060014, value);
+   }
+}
+
+static int
+nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
+   void *args, u32 size)
+{
+   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
+   return nv50_priv_ctxdma_get(chan, *(u32 *)args, chan-vblank.ctxdma);
+}
+
 static int
 nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
   void *args, u32 size)
@@ -122,20 +153,9 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
 {
struct nv50_sw_chan *chan =
container_of(notify, typeof(*chan), 
vblank.notify[notify-index]);
-   struct nv50_sw_priv *priv = (void *)nv_object(chan)-engine;
-   struct nvkm_bar *bar = nvkm_bar(priv);
-
-   nv_wr32(priv, 0x001704, chan-vblank.channel);
-   nv_wr32(priv, 0x001710, 0x8000 | chan-vblank.ctxdma);
-   bar-flush(bar);
 
-   if (nv_device(priv)-chipset == 0x50) {
-   nv_wr32(priv, 0x001570, chan-vblank.offset);
-   nv_wr32(priv, 0x001574, chan-vblank.value);
-   } else {
-   nv_wr32(priv, 0x060010, chan-vblank.offset);
-   nv_wr32(priv, 0x060014, chan-vblank.value);
-   }
+   nv50_priv_ctxdma_flush(chan, chan-vblank.channel, chan-vblank.ctxdma);
+   nv50_priv_ctxdma_wr32(chan, chan-vblank.offset, chan-vblank.value);
 
return NVKM_NOTIFY_DROP;
 }
-- 
2.4.2

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[Nouveau] [PATCH RFC 09/20] pm: change signal iter to u16

2015-06-07 Thread Samuel Pitoiset

16 bits is large enough to store the maximum number of signals available
for one domain (i.e. 256).

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 bin/nv_perfmon.c  |  4 ++--
 drm/nouveau/include/nvif/class.h  |  7 ---
 drm/nouveau/nvkm/engine/pm/base.c | 10 +-
 drm/nouveau/nvkm/engine/pm/priv.h |  2 +-
 4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/bin/nv_perfmon.c b/bin/nv_perfmon.c
index 958520e..043d864 100644
--- a/bin/nv_perfmon.c
+++ b/bin/nv_perfmon.c
@@ -289,7 +289,7 @@ ui_perfmon_query_signals(struct nvif_object *perfmon,
 
args.domain = dom-id;
do {
-   u32 prev_iter = args.iter;
+   u16 prev_iter = args.iter;
 
args.name[0] = '\0';
ret = nvif_mthd(perfmon, NVIF_PERFMON_V0_QUERY_SIGNAL,
@@ -308,7 +308,7 @@ ui_perfmon_query_signals(struct nvif_object *perfmon,
args, sizeof(args));
assert(ret == 0);
}
-   } while (args.iter != 0x);
+   } while (args.iter != 0x);
 }
 
 static void
diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index cf2af89..871247c 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -259,14 +259,15 @@ struct nvif_perfmon_query_domain_v0 {
__u8  id;
__u8  counter_nr;
__u8  iter;
-   __u32 signal_nr;
+   __u16 signal_nr;
+   __u8  pad05[2];
 };
 
 struct nvif_perfmon_query_signal_v0 {
__u8  version;
__u8  domain;
-   __u8  pad02[2];
-   __u32 iter;
+   __u16 iter;
+   __u8  pad03[4];
char  name[64];
 };
 
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index d61beff..fab0598 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -45,10 +45,10 @@ nvkm_pm_count_perfdom(struct nvkm_pm *ppm)
return domain_nr;
 }
 
-static u32
+static u16
 nvkm_perfdom_count_perfsig(struct nvkm_perfdom *dom)
 {
-   u32 signal_nr = 0;
+   u16 signal_nr = 0;
int i;
 
if (dom) {
@@ -183,9 +183,9 @@ nvkm_perfmon_mthd_query_signal(struct nvkm_object *object, 
void *data, u32 size)
nv_ioctl(object, perfmon query signal size %d\n, size);
if (nvif_unpack(args-v0, 0, 0, false)) {
nv_ioctl(object,
-perfmon query signal vers %d dom %d iter %08x\n,
+perfmon query signal vers %d dom %d iter %04x\n,
 args-v0.version, args-v0.domain, args-v0.iter);
-   si = (args-v0.iter  0x) - 1;
+   si = (args-v0.iter  0x) - 1;
} else
return ret;
 
@@ -209,7 +209,7 @@ nvkm_perfmon_mthd_query_signal(struct nvkm_object *object, 
void *data, u32 size)
}
}
 
-   args-v0.iter = 0x;
+   args-v0.iter = 0x;
return 0;
 }
 
diff --git a/drm/nouveau/nvkm/engine/pm/priv.h 
b/drm/nouveau/nvkm/engine/pm/priv.h
index 06a6e60..71667fc 100644
--- a/drm/nouveau/nvkm/engine/pm/priv.h
+++ b/drm/nouveau/nvkm/engine/pm/priv.h
@@ -44,7 +44,7 @@ struct nvkm_perfdom {
char name[32];
u32 addr;
u8  quad;
-   u32 signal_nr;
+   u16 signal_nr;
struct nvkm_perfsig signal[];
 };
 
-- 
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[Nouveau] [PATCH RFC 17/20] pm: allow the userspace to configure sources

2015-06-07 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoiset at gmail.com
---
 drm/nouveau/include/nvif/class.h  |   1 +
 drm/nouveau/nvkm/engine/pm/base.c | 102 ++
 drm/nouveau/nvkm/engine/pm/priv.h |   2 +
 3 files changed, 95 insertions(+), 10 deletions(-)

diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index 1a76a7f..3b7f49f 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -297,6 +297,7 @@ struct nvif_perfdom_v0 {
__u8  pad03[1];
struct {
__u8  signal[4];
+   __u64 source[4][8];
__u16 logic_op;
} ctr[4];
 };
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 8960bf4..a4bb6fe 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -125,6 +125,66 @@ nvkm_perfsrc_find(struct nvkm_pm *ppm, struct nvkm_perfsig 
*sig, int si)
return NULL;
 }
 
+static int
+nvkm_perfsrc_enable(struct nvkm_pm *ppm, struct nvkm_perfctr *ctr)
+{
+   struct nvkm_perfdom *dom = NULL;
+   struct nvkm_perfsig *sig;
+   struct nvkm_perfsrc *src;
+   u32 mask, value;
+   int i, j;
+
+   for (i = 0; i  4  ctr-signal[i]; i++) {
+   for (j = 0; j  8  ctr-source[i][j]; j++) {
+   sig = nvkm_perfsig_find(ppm, ctr-domain,
+   ctr-signal[i], dom);
+   if (!sig)
+   return -EINVAL;
+
+   src = nvkm_perfsrc_find(ppm, sig, ctr-source[i][j]);
+   if (!src)
+   return -EINVAL;
+
+   /* set enable bit if needed */
+   mask = value = 0x;
+   if (src-enable)
+   mask = value = 0x8000;
+   mask  |= (src-mask  src-shift);
+   value |= ((ctr-source[i][j]  32)  src-shift);
+
+   /* enable the source */
+   nv_mask(ppm, src-addr, mask, value);
+   }
+   }
+   return 0;
+}
+
+static int
+nvkm_perfsrc_disable(struct nvkm_pm *ppm, struct nvkm_perfctr *ctr)
+{
+   struct nvkm_perfdom *dom = NULL;
+   struct nvkm_perfsig *sig;
+   struct nvkm_perfsrc *src;
+   int i, j;
+
+   for (i = 0; i  4  ctr-signal[i]; i++) {
+   for (j = 0; j  8  ctr-source[i][j]; j++) {
+   sig = nvkm_perfsig_find(ppm, ctr-domain,
+   ctr-signal[i], dom);
+   if (!sig)
+   return -EINVAL;
+
+   src = nvkm_perfsrc_find(ppm, sig, ctr-source[i][j]);
+   if (!src)
+   return -EINVAL;
+
+   /* disable the source */
+   nv_mask(ppm, src-addr, src-mask  src-shift, 0);
+   }
+   }
+   return 0;
+}
+
 
/***
  * Perfmon object classes
  
**/
@@ -319,10 +379,15 @@ nvkm_perfdom_init(struct nvkm_object *object, void *data, 
u32 size)
} else
return ret;
 
-   for (i = 0; i  4; i++)
-   if (dom-ctr[i])
+   for (i = 0; i  4; i++) {
+   if (dom-ctr[i]) {
dom-func-init(ppm, dom, dom-ctr[i]);
 
+   /* enable sources */
+   nvkm_perfsrc_enable(ppm, dom-ctr[i]);
+   }
+   }
+
/* start next batch of counters for sampling */
dom-func-next(ppm, dom);
return 0;
@@ -402,13 +467,17 @@ nvkm_perfdom_mthd(struct nvkm_object *object, u32 mthd, 
void *data, u32 size)
 static void
 nvkm_perfdom_dtor(struct nvkm_object *object)
 {
+   struct nvkm_pm *ppm = (void *)object-engine;
struct nvkm_perfdom *dom = (void *)object;
int i;
 
for (i = 0; i  4; i++) {
struct nvkm_perfctr *ctr = dom-ctr[i];
-   if (ctr  ctr-head.next)
-   list_del(ctr-head);
+   if (ctr) {
+   nvkm_perfsrc_disable(ppm, ctr);
+   if (ctr-head.next)
+   list_del(ctr-head);
+   }
kfree(ctr);
}
nvkm_object_destroy(dom-base);
@@ -416,11 +485,11 @@ nvkm_perfdom_dtor(struct nvkm_object *object)
 
 static int
 nvkm_perfctr_new(struct nvkm_perfdom *dom, int slot,
-struct nvkm_perfsig *signal[4], uint16_t logic_op,
-struct nvkm_perfctr **pctr)
+struct nvkm_perfsig *signal[4], uint64_t source[4][8],
+uint16_t logic_op, struct nvkm_perfctr **pctr)
 {
struct nvkm_perfctr

[Nouveau] [PATCH RFC 13/20] pm: allow to query the number of sources for a signal

2015-06-07 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvif/class.h  |  3 ++-
 drm/nouveau/nvkm/engine/pm/base.c | 22 +++---
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index 9e4db3a..caae193 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -268,7 +268,8 @@ struct nvif_perfmon_query_signal_v0 {
__u8  domain;
__u16 iter;
__u8  signal;
-   __u8  pad04[3];
+   __u8  source_nr;
+   __u8  pad05[2];
char  name[64];
 };
 
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index dfafefd..a9c57a2 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -91,6 +91,18 @@ nvkm_perfsig_find(struct nvkm_pm *ppm, uint8_t di, uint8_t 
si,
return dom-signal[si];
 }
 
+static u8
+nvkm_perfsig_count_perfsrc(struct nvkm_perfsig *sig)
+{
+   u8 source_nr = 0, i;
+
+   for (i = 0; i  ARRAY_SIZE(sig-source); i++) {
+   if (sig-source[i])
+   source_nr++;
+   }
+   return source_nr;
+}
+
 
/***
  * Perfmon object classes
  
**/
@@ -148,9 +160,9 @@ nvkm_perfmon_mthd_query_signal(struct nvkm_object *object, 
void *data, u32 size)
struct nvkm_device *device = nv_device(object);
struct nvkm_pm *ppm = (void *)object-engine;
struct nvkm_perfdom *dom;
+   struct nvkm_perfsig *sig;
const bool all = nvkm_boolopt(device-cfgopt, NvPmShowAll, false);
const bool raw = nvkm_boolopt(device-cfgopt, NvPmUnnamed, all);
-   const char *name;
int ret, si;
 
nv_ioctl(object, perfmon query signal size %d\n, size);
@@ -167,13 +179,17 @@ nvkm_perfmon_mthd_query_signal(struct nvkm_object 
*object, void *data, u32 size)
return -EINVAL;
 
if (si = 0) {
-   if (raw || !(name = dom-signal[si].name)) {
+   sig = dom-signal[si];
+   if (raw || !sig-name) {
snprintf(args-v0.name, sizeof(args-v0.name),
 /%s/%02x, dom-name, si);
} else {
-   strncpy(args-v0.name, name, sizeof(args-v0.name));
+   strncpy(args-v0.name, sig-name,
+   sizeof(args-v0.name));
}
+
args-v0.signal = si;
+   args-v0.source_nr = nvkm_perfsig_count_perfsrc(sig);
}
 
while (++si  dom-signal_nr) {
-- 
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[Nouveau] [PATCH RFC 14/20] pm: implement NVIF_PERFMON_V0_QUERY_SOURCE method

2015-06-07 Thread Samuel Pitoiset

This allows to query the ID, the mask and the user-readable name of
sources for each signal.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvif/class.h  | 12 ++
 drm/nouveau/nvkm/engine/pm/base.c | 77 +++
 2 files changed, 89 insertions(+)

diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index caae193..d85fb0d 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -253,6 +253,7 @@ struct gf110_dma_v0 {
 
 #define NVIF_PERFMON_V0_QUERY_DOMAIN   0x00
 #define NVIF_PERFMON_V0_QUERY_SIGNAL   0x01
+#define NVIF_PERFMON_V0_QUERY_SOURCE   0x02
 
 struct nvif_perfmon_query_domain_v0 {
__u8  version;
@@ -273,6 +274,17 @@ struct nvif_perfmon_query_signal_v0 {
char  name[64];
 };
 
+struct nvif_perfmon_query_source_v0 {
+   __u8  version;
+   __u8  domain;
+   __u8  signal;
+   __u8  iter;
+   __u8  pad04[4];
+   __u32 source;
+   __u32 mask;
+   char  name[64];
+};
+
 
 
/***
  * perfctr
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index a9c57a2..ec02abf 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -103,6 +103,31 @@ nvkm_perfsig_count_perfsrc(struct nvkm_perfsig *sig)
return source_nr;
 }
 
+static struct nvkm_perfsrc *
+nvkm_perfsrc_find(struct nvkm_pm *ppm, struct nvkm_perfsig *sig, int si)
+{
+   struct nvkm_perfsrc *src;
+   bool found = false;
+   int tmp = 1; /* Sources ID start from 1 */
+   u8 i;
+
+   for (i = 0; i  ARRAY_SIZE(sig-source)  sig-source[i]; i++) {
+   if (sig-source[i] == si) {
+   found = true;
+   break;
+   }
+   }
+
+   if (found) {
+   list_for_each_entry(src, ppm-sources, head) {
+   if (tmp++ == si)
+   return src;
+   }
+   }
+
+   return NULL;
+}
+
 
/***
  * Perfmon object classes
  
**/
@@ -204,6 +229,56 @@ nvkm_perfmon_mthd_query_signal(struct nvkm_object *object, 
void *data, u32 size)
 }
 
 static int
+nvkm_perfmon_mthd_query_source(struct nvkm_object *object, void *data, u32 
size)
+{
+   union {
+   struct nvif_perfmon_query_source_v0 v0;
+   } *args = data;
+   struct nvkm_pm *ppm = (void *)object-engine;
+   struct nvkm_perfdom *dom = NULL;
+   struct nvkm_perfsig *sig;
+   struct nvkm_perfsrc *src;
+   u8 source_nr = 0;
+   int si, ret;
+
+   nv_ioctl(object, perfmon query source size %d\n, size);
+   if (nvif_unpack(args-v0, 0, 0, false)) {
+   nv_ioctl(object,
+perfmon source vers %d dom %d sig %02x iter %02x\n,
+args-v0.version, args-v0.domain, args-v0.signal,
+args-v0.iter);
+   si = (args-v0.iter  0xff) - 1;
+   } else
+   return ret;
+
+   sig = nvkm_perfsig_find(ppm, args-v0.domain, args-v0.signal, dom);
+   if (!sig)
+   return -EINVAL;
+
+   source_nr = nvkm_perfsig_count_perfsrc(sig);
+   if (si = (int)source_nr)
+   return -EINVAL;
+
+   if (si = 0) {
+   src = nvkm_perfsrc_find(ppm, sig, sig-source[si]);
+   if (!src)
+   return -EINVAL;
+
+   args-v0.source = sig-source[si];
+   args-v0.mask   = src-mask;
+   strncpy(args-v0.name, src-name, sizeof(args-v0.name));
+   }
+
+   if (++si  source_nr) {
+   args-v0.iter = ++si;
+   return 0;
+   }
+
+   args-v0.iter = 0xff;
+   return 0;
+}
+
+static int
 nvkm_perfmon_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 {
switch (mthd) {
@@ -211,6 +286,8 @@ nvkm_perfmon_mthd(struct nvkm_object *object, u32 mthd, 
void *data, u32 size)
return nvkm_perfmon_mthd_query_domain(object, data, size);
case NVIF_PERFMON_V0_QUERY_SIGNAL:
return nvkm_perfmon_mthd_query_signal(object, data, size);
+   case NVIF_PERFMON_V0_QUERY_SOURCE:
+   return nvkm_perfmon_mthd_query_source(object, data, size);
default:
break;
}
-- 
2.4.2

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[Nouveau] [PATCH RFC 15/20] pm: allow the userspace to schedule hardware counters

2015-06-07 Thread Samuel Pitoiset

This adds a new method NVIF_PERFCTR_V0_INIT which starts a batch of
hardware counters for sampling. This will allow the userspace to start
a monitoring session using the INIT method and to stop it with SAMPLE,
for example before and after a frame is rendered.

This commit temporarily breaks nv_perfmon but this is going to be fixed
with the upcoming patch.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvif/class.h  |  8 +++--
 drm/nouveau/nvkm/engine/pm/base.c | 64 +--
 drm/nouveau/nvkm/engine/pm/priv.h |  1 +
 3 files changed, 48 insertions(+), 25 deletions(-)

diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index d85fb0d..528eac8 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -300,8 +300,12 @@ struct nvif_perfctr_v0 {
__u8  pad06[4];
 };
 
-#define NVIF_PERFCTR_V0_SAMPLE 0x00
-#define NVIF_PERFCTR_V0_READ   0x01
+#define NVIF_PERFCTR_V0_INIT   0x00
+#define NVIF_PERFCTR_V0_SAMPLE 0x01
+#define NVIF_PERFCTR_V0_READ   0x02
+
+struct nvif_perfctr_init {
+};
 
 struct nvif_perfctr_sample {
 };
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index ec02abf..5dbb3b4 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -307,13 +307,43 @@ nvkm_perfmon_ofuncs = {
  * Perfctr object classes
  
**/
 static int
+nvkm_perfctr_init(struct nvkm_object *object, void *data, u32 size)
+{
+   union {
+   struct nvif_perfctr_init none;
+   } *args = data;
+   struct nvkm_pm *ppm = (void *)object-engine;
+   struct nvkm_perfctr *ctr = (void *)object;
+   struct nvkm_perfdom *dom = ctr-dom;
+   int ret;
+
+   nv_ioctl(object, perfctr init size %d\n, size);
+   if (nvif_unvers(args-none)) {
+   nv_ioctl(object, perfctr init\n);
+   } else
+   return ret;
+
+   ctr-slot = ffs(dom-quad) - 1;
+   if (ctr-slot  0) {
+   /* no free slots are available */
+   return -EINVAL;
+   }
+   dom-quad = ~(QUAD_FREE  ctr-slot);
+   dom-func-init(ppm, dom, ctr);
+
+   /* start next batch of counters for sampling */
+   dom-func-next(ppm, dom);
+   return 0;
+}
+
+static int
 nvkm_perfctr_sample(struct nvkm_object *object, void *data, u32 size)
 {
union {
struct nvif_perfctr_sample none;
} *args = data;
struct nvkm_pm *ppm = (void *)object-engine;
-   struct nvkm_perfctr *ctr, *tmp;
+   struct nvkm_perfctr *ctr;
struct nvkm_perfdom *dom;
int ret;
 
@@ -328,32 +358,15 @@ nvkm_perfctr_sample(struct nvkm_object *object, void 
*data, u32 size)
/* sample previous batch of counters */
if (dom-quad != QUAD_MASK) {
dom-func-next(ppm, dom);
-   tmp = NULL;
-   while (!list_empty(dom-list)) {
-   ctr = list_first_entry(dom-list,
-  typeof(*ctr), head);
-   if (ctr-slot  0) break;
-   if ( tmp  tmp == ctr) break;
-   if (!tmp) tmp = ctr;
+
+   /* read counter values */
+   list_for_each_entry(ctr, dom-list, head) {
dom-func-read(ppm, dom, ctr);
-   ctr-slot  = -1;
-   list_move_tail(ctr-head, dom-list);
+   ctr-slot = -1;
}
-   }
-
-   dom-quad = QUAD_MASK;
 
-   /* setup next batch of counters for sampling */
-   list_for_each_entry(ctr, dom-list, head) {
-   ctr-slot = ffs(dom-quad) - 1;
-   if (ctr-slot  0)
-   break;
-   dom-quad = ~(QUAD_FREE  ctr-slot);
-   dom-func-init(ppm, dom, ctr);
+   dom-quad = QUAD_MASK;
}
-
-   if (dom-quad != QUAD_MASK)
-   dom-func-next(ppm, dom);
}
 
return 0;
@@ -386,6 +399,8 @@ static int
 nvkm_perfctr_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 {
switch (mthd) {
+   case NVIF_PERFCTR_V0_INIT:
+   return nvkm_perfctr_init(object, data, size);
case NVIF_PERFCTR_V0_SAMPLE:
return nvkm_perfctr_sample(object, data, size);
case NVIF_PERFCTR_V0_READ:
@@ -400,6 +415,8 @@ static

[Nouveau] [PATCH RFC 05/20] pm: reorganize the nvif interface

2015-06-07 Thread Samuel Pitoiset

This commit introduces the NVIF_IOCTL_NEW_V0_PERFMON class which will be
used in order to query domains, signals and sources. This separates the
querying and the counting interface.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 bin/nv_perfmon.c  | 12 ++--
 drm/nouveau/include/nvif/class.h  | 26 --
 drm/nouveau/include/nvif/ioctl.h  |  5 +++--
 drm/nouveau/nvkm/engine/pm/base.c | 38 --
 4 files changed, 57 insertions(+), 24 deletions(-)

diff --git a/bin/nv_perfmon.c b/bin/nv_perfmon.c
index a8c5838..30a3138 100644
--- a/bin/nv_perfmon.c
+++ b/bin/nv_perfmon.c
@@ -600,7 +600,7 @@ main(int argc, char **argv)
const char *cfg = NULL;
const char *dbg = error;
u64 dev = ~0ULL;
-   struct nvif_perfctr_query_v0 args = {};
+   struct nvif_perfmon_query_signal_v0 args = {};
struct nvif_client *client;
struct nvif_object object;
int ret, c, k;
@@ -644,15 +644,14 @@ main(int argc, char **argv)
}
 
ret = nvif_object_init(nvif_object(device), NULL, 0xdeadbeef,
-  NVIF_IOCTL_NEW_V0_PERFCTR,
-  (struct nvif_perfctr_v0) {
-  }, sizeof(struct nvif_perfctr_v0), object);
+  NVIF_IOCTL_NEW_V0_PERFMON, NULL, 0, object);
assert(ret == 0);
do {
u32 prev_iter = args.iter;
 
args.name[0] = '\0';
-   ret = nvif_mthd(object, NVIF_PERFCTR_V0_QUERY, args, 
sizeof(args));
+   ret = nvif_mthd(object, NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
assert(ret == 0);
 
if (prev_iter) {
@@ -663,7 +662,8 @@ main(int argc, char **argv)
args.iter = prev_iter;
strncpy(signals[nr_signals - 1], args.name,
sizeof(args.name));
-   ret = nvif_mthd(object, NVIF_PERFCTR_V0_QUERY, args, 
sizeof(args));
+   ret = nvif_mthd(object, NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
assert(ret == 0);
}
} while (args.iter != 0x);
diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index 64f8b2f..11935a0 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -251,6 +251,20 @@ struct gf110_dma_v0 {
  * perfmon
  
**/
 
+#define NVIF_PERFMON_V0_QUERY_SIGNAL   0x00
+
+struct nvif_perfmon_query_signal_v0 {
+   __u8  version;
+   __u8  pad01[3];
+   __u32 iter;
+   char  name[64];
+};
+
+
+/***
+ * perfctr
+ 
**/
+
 struct nvif_perfctr_v0 {
__u8  version;
__u8  pad01[1];
@@ -259,16 +273,8 @@ struct nvif_perfctr_v0 {
char  name[4][64];
 };
 
-#define NVIF_PERFCTR_V0_QUERY  0x00
-#define NVIF_PERFCTR_V0_SAMPLE 0x01
-#define NVIF_PERFCTR_V0_READ   0x02
-
-struct nvif_perfctr_query_v0 {
-   __u8  version;
-   __u8  pad01[3];
-   __u32 iter;
-   char  name[64];
-};
+#define NVIF_PERFCTR_V0_SAMPLE 0x00
+#define NVIF_PERFCTR_V0_READ   0x01
 
 struct nvif_perfctr_sample {
 };
diff --git a/drm/nouveau/include/nvif/ioctl.h b/drm/nouveau/include/nvif/ioctl.h
index 4cd8e32..517cd27 100644
--- a/drm/nouveau/include/nvif/ioctl.h
+++ b/drm/nouveau/include/nvif/ioctl.h
@@ -49,8 +49,9 @@ struct nvif_ioctl_new_v0 {
__u64 token;
__u32 handle;
 /* these class numbers are made up by us, and not nvidia-assigned */
-#define NVIF_IOCTL_NEW_V0_PERFCTR0x
-#define NVIF_IOCTL_NEW_V0_CONTROL0xfffe
+#define NVIF_IOCTL_NEW_V0_PERFMON0x
+#define NVIF_IOCTL_NEW_V0_PERFCTR0xfffe
+#define NVIF_IOCTL_NEW_V0_CONTROL0xfffd
__u32 oclass;
__u8  data[];   /* class data (class.h) */
 };
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 7b07e8b..cb88170 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -83,10 +83,10 @@ nvkm_perfsig_find(struct nvkm_pm *ppm, const char *name, 
u32 size,
  * Perfmon object classes

[Nouveau] [PATCH RFC 08/20] pm: allow to query signals by domain

2015-06-07 Thread Samuel Pitoiset

This will allow to configure performance counters with hardware signal
indexes instead of user-readable names in an upcoming patch.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 bin/nv_perfmon.c  | 185 --
 drm/nouveau/include/nvif/class.h  |   3 +-
 drm/nouveau/nvkm/engine/pm/base.c |  36 +++-
 3 files changed, 150 insertions(+), 74 deletions(-)

diff --git a/bin/nv_perfmon.c b/bin/nv_perfmon.c
index 30a3138..958520e 100644
--- a/bin/nv_perfmon.c
+++ b/bin/nv_perfmon.c
@@ -36,8 +36,7 @@
 #include sys/time.h
 
 static struct nvif_device *device;
-static char **signals;
-static int nr_signals;
+static int nr_signals; /* number of signals for all domains */
 
 #define SEC_US  100
 #define REFRESH_PERIOD SEC_US
@@ -247,6 +246,17 @@ ui_menu_win = {
  *
  
**/
 
+struct ui_perfmon_dom {
+   struct list_head head;
+   struct list_head list;
+   u8 id;
+};
+
+struct ui_perfmon_sig {
+   struct list_head head;
+   char *name;
+};
+
 struct ui_main {
struct list_head head;
u32 handle;
@@ -258,6 +268,7 @@ struct ui_main {
 };
 
 static struct list_head ui_main_list = LIST_HEAD_INIT(ui_main_list);
+static struct list_head ui_doms_list = LIST_HEAD_INIT(ui_doms_list);
 static u32 ui_main_handle = 0xc000;
 
 static void
@@ -269,32 +280,134 @@ ui_main_remove(struct ui_main *item)
 }
 
 static void
+ui_perfmon_query_signals(struct nvif_object *perfmon,
+struct ui_perfmon_dom *dom)
+{
+   struct nvif_perfmon_query_signal_v0 args = {};
+   struct ui_perfmon_sig *sig;
+   int ret;
+
+   args.domain = dom-id;
+   do {
+   u32 prev_iter = args.iter;
+
+   args.name[0] = '\0';
+   ret = nvif_mthd(perfmon, NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
+   assert(ret == 0);
+
+   if (prev_iter) {
+   nr_signals++;
+   sig = calloc(1, sizeof(*sig));
+   sig-name = malloc(sizeof(args.name));
+   strncpy(sig-name, args.name, sizeof(args.name));
+   list_add_tail(sig-head, dom-list);
+
+   args.iter = prev_iter;
+   ret = nvif_mthd(perfmon, NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
+   assert(ret == 0);
+   }
+   } while (args.iter != 0x);
+}
+
+static void
+ui_perfmon_query_domains(struct nvif_object *perfmon)
+{
+   struct nvif_perfmon_query_domain_v0 args = {};
+   struct ui_perfmon_dom *dom;
+   int ret;
+
+   assert(ret == 0);
+   do {
+   u8 prev_iter = args.iter;
+
+   ret = nvif_mthd(perfmon, NVIF_PERFMON_V0_QUERY_DOMAIN,
+   args, sizeof(args));
+   assert(ret == 0);
+
+   if (prev_iter) {
+   dom = calloc(1, sizeof(*dom));
+   dom-id = args.id;
+   INIT_LIST_HEAD(dom-list);
+   list_add_tail(dom-head, ui_doms_list);
+
+   args.iter = prev_iter;
+   ret = nvif_mthd(perfmon, NVIF_PERFMON_V0_QUERY_DOMAIN,
+   args, sizeof(args));
+   assert(ret == 0);
+
+   /* query available signals for the domain */
+   ui_perfmon_query_signals(perfmon, dom);
+   }
+   } while (args.iter != 0xff);
+}
+
+static void
+ui_perfmon_init(void)
+{
+   struct nvif_object perfmon;
+   int ret;
+
+   ret = nvif_object_init(nvif_object(device), NULL, 0xdeadbeef,
+  NVIF_IOCTL_NEW_V0_PERFMON, NULL, 0, perfmon);
+   assert(ret == 0);
+
+   /* query available domains for the device */
+   ui_perfmon_query_domains(perfmon);
+
+   nvif_object_fini(perfmon);
+}
+
+static void
+ui_perfmon_fini(void)
+{
+   struct ui_perfmon_dom *dom, *next_dom;
+   struct ui_perfmon_sig *sig, *next_sig;
+
+   list_for_each_entry_safe(dom, next_dom, ui_doms_list, head) {
+   list_for_each_entry_safe(sig, next_sig, dom-list, head) {
+   list_del(sig-head);
+   free(sig-name);
+   free(sig);
+   }
+   list_del(dom-head);
+   free(dom);
+   }
+}
+
+static void
 ui_main_select(void)
 {
struct ui_main *item, *temp;
-   int ret, i;
+   struct ui_perfmon_dom *dom;
+   struct ui_perfmon_sig *sig;
+   int ret;
 
list_for_each_entry_safe(item, temp, ui_main_list, head) {
ui_main_remove(item);
}
 
-   for (i = 0; i  nr_signals; i++) {
-   struct nvif_perfctr_v0

[Nouveau] [PATCH RFC 07/20] pm: implement NVIF_PERFMON_V0_QUERY_DOMAIN method

2015-06-07 Thread Samuel Pitoiset

This allows to query the number of available domains, including the
number of hardware counter and the number of signals per domain.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvif/class.h  | 11 -
 drm/nouveau/nvkm/engine/pm/base.c | 86 +++
 2 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index 11935a0..0b28929 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -251,7 +251,16 @@ struct gf110_dma_v0 {
  * perfmon
  
**/
 
-#define NVIF_PERFMON_V0_QUERY_SIGNAL   0x00
+#define NVIF_PERFMON_V0_QUERY_DOMAIN   0x00
+#define NVIF_PERFMON_V0_QUERY_SIGNAL   0x01
+
+struct nvif_perfmon_query_domain_v0 {
+   __u8  version;
+   __u8  id;
+   __u8  counter_nr;
+   __u8  iter;
+   __u32 signal_nr;
+};
 
 struct nvif_perfmon_query_signal_v0 {
__u8  version;
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 2f85147..3d9bcbc 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -34,6 +34,45 @@
 #define QUAD_MASK 0x0f
 #define QUAD_FREE 0x01
 
+static u8
+nvkm_pm_count_perfdom(struct nvkm_pm *ppm)
+{
+   struct nvkm_perfdom *dom;
+   u8 domain_nr = 0;
+
+   list_for_each_entry(dom, ppm-domains, head)
+   domain_nr++;
+   return domain_nr;
+}
+
+static u32
+nvkm_perfdom_count_perfsig(struct nvkm_perfdom *dom)
+{
+   u32 signal_nr = 0;
+   int i;
+
+   if (dom) {
+   for (i = 0; i  dom-signal_nr; i++) {
+   if (dom-signal[i].name)
+   signal_nr++;
+   }
+   }
+   return signal_nr;
+}
+
+static struct nvkm_perfdom *
+nvkm_perfdom_find(struct nvkm_pm *ppm, int di)
+{
+   struct nvkm_perfdom *dom;
+   int tmp = 0;
+
+   list_for_each_entry(dom, ppm-domains, head) {
+   if (tmp++ == di)
+   return dom;
+   }
+   return NULL;
+}
+
 static struct nvkm_perfsig *
 nvkm_perfsig_find_(struct nvkm_perfdom *dom, const char *name, u32 size)
 {
@@ -83,6 +122,51 @@ nvkm_perfsig_find(struct nvkm_pm *ppm, const char *name, 
u32 size,
  * Perfmon object classes
  
**/
 static int
+nvkm_perfmon_mthd_query_domain(struct nvkm_object *object, void *data, u32 
size)
+{
+   union {
+   struct nvif_perfmon_query_domain_v0 v0;
+   } *args = data;
+   struct nvkm_pm *ppm = (void *)object-engine;
+   struct nvkm_perfdom *dom;
+   u8 domain_nr;
+   int di, ret;
+
+   nv_ioctl(object, perfmon query domain size %d\n, size);
+   if (nvif_unpack(args-v0, 0, 0, false)) {
+   nv_ioctl(object, perfmon domain vers %d iter %02x\n,
+args-v0.version, args-v0.iter);
+   di = (args-v0.iter  0xff) - 1;
+   } else
+   return ret;
+
+   domain_nr = nvkm_pm_count_perfdom(ppm);
+   if (di = (int)domain_nr)
+   return -EINVAL;
+
+   if (di = 0) {
+   dom = nvkm_perfdom_find(ppm, di);
+   if (dom == NULL)
+   return -EINVAL;
+
+   args-v0.id = di;
+   args-v0.signal_nr  = nvkm_perfdom_count_perfsig(dom);
+
+   /* Currently only global counters (PCOUNTER) are implemented
+* but this will be different for local counters (MP). */
+   args-v0.counter_nr = 4;
+   }
+
+   if (++di  domain_nr) {
+   args-v0.iter = ++di;
+   return 0;
+   }
+
+   args-v0.iter = 0xff;
+   return 0;
+}
+
+static int
 nvkm_perfmon_mthd_query_signal(struct nvkm_object *object, void *data, u32 
size)
 {
union {
@@ -145,6 +229,8 @@ static int
 nvkm_perfmon_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 {
switch (mthd) {
+   case NVIF_PERFMON_V0_QUERY_DOMAIN:
+   return nvkm_perfmon_mthd_query_domain(object, data, size);
case NVIF_PERFMON_V0_QUERY_SIGNAL:
return nvkm_perfmon_mthd_query_signal(object, data, size);
default:
-- 
2.4.2

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[Nouveau] [PATCH RFC 03/20] pm: remove pmu signals

2015-06-07 Thread Samuel Pitoiset

PDAEMON signals don't have to be exposed by the perfmon engine.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
Reviewed-by: Martin Peres martin.pe...@free.fr
---
 drm/nouveau/include/nvkm/engine/pm.h |   4 --
 drm/nouveau/nvkm/engine/pm/Kbuild|   1 -
 drm/nouveau/nvkm/engine/pm/daemon.c  | 108 ---
 drm/nouveau/nvkm/engine/pm/gf100.c   |   5 --
 drm/nouveau/nvkm/engine/pm/gk104.c   |   6 --
 drm/nouveau/nvkm/engine/pm/gk110.c   |   4 --
 drm/nouveau/nvkm/engine/pm/gt215.c   |  20 +--
 drm/nouveau/nvkm/engine/pm/priv.h|   4 --
 8 files changed, 1 insertion(+), 151 deletions(-)
 delete mode 100644 drm/nouveau/nvkm/engine/pm/daemon.c

diff --git a/drm/nouveau/include/nvkm/engine/pm.h 
b/drm/nouveau/include/nvkm/engine/pm.h
index 93181bb..6c2d057 100644
--- a/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drm/nouveau/include/nvkm/engine/pm.h
@@ -12,10 +12,6 @@ struct nvkm_pm {
 
struct list_head domains;
u32 sequence;
-
-   /*XXX: temp for daemon backend */
-   u32 pwr[8];
-   u32 last;
 };
 
 static inline struct nvkm_pm *
diff --git a/drm/nouveau/nvkm/engine/pm/Kbuild 
b/drm/nouveau/nvkm/engine/pm/Kbuild
index 413b609..c5ee8d5 100644
--- a/drm/nouveau/nvkm/engine/pm/Kbuild
+++ b/drm/nouveau/nvkm/engine/pm/Kbuild
@@ -1,5 +1,4 @@
 nvkm-y += nvkm/engine/pm/base.o
-nvkm-y += nvkm/engine/pm/daemon.o
 nvkm-y += nvkm/engine/pm/nv40.o
 nvkm-y += nvkm/engine/pm/nv50.o
 nvkm-y += nvkm/engine/pm/g84.o
diff --git a/drm/nouveau/nvkm/engine/pm/daemon.c 
b/drm/nouveau/nvkm/engine/pm/daemon.c
deleted file mode 100644
index a7a5f3a..000
--- a/drm/nouveau/nvkm/engine/pm/daemon.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the Software),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include priv.h
-
-static void
-pwr_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
-struct nvkm_perfctr *ctr)
-{
-   u32 mask = 0x;
-   u32 ctrl = 0x0001;
-   int i;
-
-   for (i = 0; i  ARRAY_SIZE(ctr-signal)  ctr-signal[i]; i++)
-   mask |= 1  (ctr-signal[i] - dom-signal);
-
-   nv_wr32(ppm, 0x10a504 + (ctr-slot * 0x10), mask);
-   nv_wr32(ppm, 0x10a50c + (ctr-slot * 0x10), ctrl);
-   nv_wr32(ppm, 0x10a50c + (ppm-last * 0x10), 0x0003);
-}
-
-static void
-pwr_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
-struct nvkm_perfctr *ctr)
-{
-   ctr-ctr = ppm-pwr[ctr-slot];
-   ctr-clk = ppm-pwr[ppm-last];
-}
-
-static void
-pwr_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
-{
-   int i;
-
-   for (i = 0; i = ppm-last; i++) {
-   ppm-pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
-   nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x8000);
-   }
-}
-
-static const struct nvkm_funcdom
-pwr_perfctr_func = {
-   .init = pwr_perfctr_init,
-   .read = pwr_perfctr_read,
-   .next = pwr_perfctr_next,
-};
-
-const struct nvkm_specdom
-gt215_pm_pwr[] = {
-   { 0x20, (const struct nvkm_specsig[]) {
-   { 0x00, pwr_gr_idle },
-   { 0x04, pwr_bsp_idle },
-   { 0x05, pwr_vp_idle },
-   { 0x06, pwr_ppp_idle },
-   { 0x13, pwr_ce0_idle },
-   {}
-   }, pwr_perfctr_func },
-   {}
-};
-
-const struct nvkm_specdom
-gf100_pm_pwr[] = {
-   { 0x20, (const struct nvkm_specsig[]) {
-   { 0x00, pwr_gr_idle },
-   { 0x04, pwr_bsp_idle },
-   { 0x05, pwr_vp_idle },
-   { 0x06, pwr_ppp_idle },
-   { 0x13, pwr_ce0_idle },
-   { 0x14, pwr_ce1_idle },
-   {}
-   }, pwr_perfctr_func },
-   {}
-};
-
-const struct nvkm_specdom
-gk104_pm_pwr[] = {
-   { 0x20, (const

[Nouveau] [PATCH RFC 20/20] sw/nv50: add and interface for controlling performance counters

2015-06-07 Thread Samuel Pitoiset

This software methods interface will allow the userspace to tie
monitoring of performance counters to the command stream.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/sw/nv50.c | 160 ++
 drm/nouveau/nvkm/engine/sw/nv50.h |   6 ++
 2 files changed, 166 insertions(+)

diff --git a/drm/nouveau/nvkm/engine/sw/nv50.c 
b/drm/nouveau/nvkm/engine/sw/nv50.c
index b7c0227..b5f8263 100644
--- a/drm/nouveau/nvkm/engine/sw/nv50.c
+++ b/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -29,7 +29,9 @@
 #include engine/disp.h
 #include subdev/bar.h
 
+#include nvif/class.h
 #include nvif/event.h
+#include nvif/ioctl.h
 
 
/***
  * software object classes
@@ -80,6 +82,14 @@ nv50_priv_ctxdma_wr32(struct nv50_sw_chan *chan, u64 offset, 
u32 value)
}
 }
 
+static u64
+nv50_priv_pm_get_offset(struct nv50_sw_chan *chan, u32 sequence)
+{
+   u32 max_queries = chan-pm.max_queries;
+   u32 ring_size = chan-pm.ring_size;
+   return (1 + (sequence % ring_size) * max_queries * 3) * 4;
+}
+
 static int
 nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
void *args, u32 size)
@@ -128,13 +138,163 @@ nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, 
void *args, u32 size)
return -EINVAL;
 }
 
+static int
+nv50_sw_mthd_dma_pm(struct nvkm_object *object, u32 mthd,
+   void *args, u32 size)
+{
+   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
+   return nv50_priv_ctxdma_get(chan, *(u32 *)args, chan-pm.ctxdma);
+}
+
+static int
+nv50_sw_mthd_pm_ring_size(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
+   chan-pm.ring_size = *(u32 *)args;
+   return 0;
+}
+
+static int
+nv50_sw_mthd_pm_max_queries(struct nvkm_object *object, u32 mthd,
+   void *args, u32 size)
+{
+   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
+   chan-pm.max_queries = *(u32 *)args;
+   return 0;
+}
+
+static int
+nv50_sw_mthd_pm_mthd_init(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
+   struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)-parent;
+   struct nvkm_handle *handle;
+   struct nvkm_object *namedb;
+   int ret = -EINVAL;
+
+   namedb = nv_object(fifo)-parent;
+   while (!nv_iclass(namedb, NV_NAMEDB_CLASS))
+   namedb = namedb-parent;
+
+   handle = nvkm_namedb_get(nv_namedb(namedb), *(u32 *)args);
+   if (!handle)
+   return -ENOENT;
+
+   if (nv_iclass(handle-object, NVIF_IOCTL_NEW_V0_PERFMON)) {
+   struct nvkm_object *object = handle-object;
+   struct nvkm_ofuncs *ofuncs = object-oclass-ofuncs;
+   struct nvif_perfdom_init args = {};
+
+   ret = ofuncs-mthd(object, NVIF_PERFDOM_V0_INIT,
+  args, sizeof(args));
+   }
+   nvkm_namedb_put(handle);
+   return ret;
+}
+
+static int
+nv50_sw_mthd_pm_mthd_sample(struct nvkm_object *object, u32 mthd,
+   void *args, u32 size)
+{
+   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
+   struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)-parent;
+   struct nvkm_handle *handle;
+   struct nvkm_object *namedb;
+   int ret = -EINVAL;
+
+   namedb = nv_object(fifo)-parent;
+   while (!nv_iclass(namedb, NV_NAMEDB_CLASS))
+   namedb = namedb-parent;
+
+   handle = nvkm_namedb_get(nv_namedb(namedb), *(u32 *)args);
+   if (!handle)
+   return -ENOENT;
+
+   if (nv_iclass(handle-object, NVIF_IOCTL_NEW_V0_PERFMON)) {
+   struct nvkm_object *object = handle-object;
+   struct nvkm_ofuncs *ofuncs = object-oclass-ofuncs;
+   struct nvif_perfdom_sample args = {};
+
+   ret = ofuncs-mthd(object, NVIF_PERFDOM_V0_SAMPLE,
+  args, sizeof(args));
+   }
+   nvkm_namedb_put(handle);
+   return ret;
+}
+
+static int
+nv50_sw_mthd_pm_mthd_read(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+   struct nv50_sw_chan *chan = (void *)nv_engctx(object-parent);
+   struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)-parent;
+   struct nvkm_handle *handle;
+   struct nvkm_object *namedb;
+   u32 seq = *(u32 *)args;
+   int ret = -ENOENT;
+   u64 offset;
+   int i;
+
+   nv50_priv_ctxdma_flush(chan, chan-vblank.channel, chan-pm.ctxdma);
+   offset = nv50_priv_pm_get_offset(chan, seq);
+
+   namedb = nv_object(fifo)-parent;
+   while (!nv_iclass(namedb, NV_NAMEDB_CLASS

[Nouveau] [PATCH RFC 18/20] pm/nv50: add compute and graphics signals/sources

2015-06-07 Thread Samuel Pitoiset

These signals and sources have been reverse engineered from NVIDIA
PerfKit (Windows) and CUPTI (Linux), they will be used to build complex
hardware events from the userspace.

This commit also adds a new class for GT200.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvkm/engine/pm.h  |   1 +
 drm/nouveau/nvkm/engine/device/nv50.c |   2 +-
 drm/nouveau/nvkm/engine/pm/Kbuild |   1 +
 drm/nouveau/nvkm/engine/pm/g84.c  | 101 -
 drm/nouveau/nvkm/engine/pm/gt200.c| 163 ++
 drm/nouveau/nvkm/engine/pm/gt215.c|  84 +-
 drm/nouveau/nvkm/engine/pm/nv50.c | 136 ++--
 drm/nouveau/nvkm/engine/pm/priv.h |   8 ++
 8 files changed, 485 insertions(+), 11 deletions(-)
 create mode 100644 drm/nouveau/nvkm/engine/pm/gt200.c

diff --git a/drm/nouveau/include/nvkm/engine/pm.h 
b/drm/nouveau/include/nvkm/engine/pm.h
index 130b545..82f1c7f 100644
--- a/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drm/nouveau/include/nvkm/engine/pm.h
@@ -24,6 +24,7 @@ nvkm_pm(void *obj)
 extern struct nvkm_oclass *nv40_pm_oclass;
 extern struct nvkm_oclass *nv50_pm_oclass;
 extern struct nvkm_oclass *g84_pm_oclass;
+extern struct nvkm_oclass *gt200_pm_oclass;
 extern struct nvkm_oclass *gt215_pm_oclass;
 extern struct nvkm_oclass gf100_pm_oclass;
 extern struct nvkm_oclass gk104_pm_oclass;
diff --git a/drm/nouveau/nvkm/engine/device/nv50.c 
b/drm/nouveau/nvkm/engine/device/nv50.c
index 249b844..a2627ec 100644
--- a/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drm/nouveau/nvkm/engine/device/nv50.c
@@ -288,7 +288,7 @@ nv50_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_CIPHER ] = g84_cipher_oclass;
device-oclass[NVDEV_ENGINE_BSP] = g84_bsp_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] =  g84_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] =  gt200_pm_oclass;
break;
case 0xaa:
device-cname = MCP77/MCP78;
diff --git a/drm/nouveau/nvkm/engine/pm/Kbuild 
b/drm/nouveau/nvkm/engine/pm/Kbuild
index c5ee8d5..cc01048 100644
--- a/drm/nouveau/nvkm/engine/pm/Kbuild
+++ b/drm/nouveau/nvkm/engine/pm/Kbuild
@@ -2,6 +2,7 @@ nvkm-y += nvkm/engine/pm/base.o
 nvkm-y += nvkm/engine/pm/nv40.o
 nvkm-y += nvkm/engine/pm/nv50.o
 nvkm-y += nvkm/engine/pm/g84.o
+nvkm-y += nvkm/engine/pm/gt200.o
 nvkm-y += nvkm/engine/pm/gt215.o
 nvkm-y += nvkm/engine/pm/gf100.o
 nvkm-y += nvkm/engine/pm/gk104.o
diff --git a/drm/nouveau/nvkm/engine/pm/g84.c b/drm/nouveau/nvkm/engine/pm/g84.c
index d54c670..dda539c 100644
--- a/drm/nouveau/nvkm/engine/pm/g84.c
+++ b/drm/nouveau/nvkm/engine/pm/g84.c
@@ -23,15 +23,112 @@
  */
 #include nv40.h
 
+const struct nvkm_specsrc
+g84_vfetch_sources[] = {
+   { 0x400c0c, (const struct nvkm_specmux[]) {
+   { 0x3, 0, unk0 },
+   {}
+   }, pgraph_vfetch_unk0c },
+   {}
+};
+
+static const struct nvkm_specsrc
+g84_crop_sources[] = {
+   { 0x407008, (const struct nvkm_specmux[]) {
+   { 0xf, 0, sel0, true },
+   { 0x7, 16, sel1, true },
+   {}
+   }, pgraph_rop0_crop_pm_mux },
+   {}
+};
+
+static const struct nvkm_specsrc
+g84_tex_sources[] = {
+   { 0x408808, (const struct nvkm_specmux[]) {
+   { 0xf, 0, unk0 },
+   {}
+   }, pgraph_tpc0_tex_unk08 },
+   {}
+};
+
 static const struct nvkm_specdom
 g84_pm[] = {
{ 0x20, (const struct nvkm_specsig[]) {
{}
}, nv40_perfctr_func },
-   { 0x20, (const struct nvkm_specsig[]) {
+   { 0xf0, (const struct nvkm_specsig[]) {
+   { 0xbd, pc01_gr_idle },
+   { 0x5e, pc01_strmout_00 },
+   { 0x5f, pc01_strmout_01 },
+   { 0xd2, pc01_trast_00 },
+   { 0xd3, pc01_trast_01 },
+   { 0xd4, pc01_trast_02 },
+   { 0xd5, pc01_trast_03 },
+   { 0xd8, pc01_trast_04 },
+   { 0xd9, pc01_trast_05 },
+   { 0x5c, pc01_vattr_00 },
+   { 0x5d, pc01_vattr_01 },
+   { 0x66, pc01_vfetch_00, g84_vfetch_sources },
+   { 0x67, pc01_vfetch_01, g84_vfetch_sources },
+   { 0x68, pc01_vfetch_02, g84_vfetch_sources },
+   { 0x69, pc01_vfetch_03, g84_vfetch_sources },
+   { 0x6a, pc01_vfetch_04, g84_vfetch_sources },
+   { 0x6b, pc01_vfetch_05, g84_vfetch_sources },
+   { 0x6c, pc01_vfetch_06, g84_vfetch_sources },
+   { 0x6d, pc01_vfetch_07, g84_vfetch_sources

[Nouveau] [PATCH RFC 12/20] pm: add concept of sources

2015-06-07 Thread Samuel Pitoiset

From: Samuel Pitoiset samuel.pitoisetÅgmail.com

A source (or multiplexer) is a tuple addr+mask+shift which allows to
control a block of signals. The maximum number of sources that a signal
can define is arbitrary limited to 8 and this should be large enough.
This patch allows to define multi-level of sources for a signal.

Each different sources are stored to a global list and will be exposed
to the userspace through the nvif interface in order to avoid conflicts.

Signed-off-by: Samuel Pitoiset samuel.pitoiset at gmail.com
---
 drm/nouveau/include/nvkm/engine/pm.h |  1 +
 drm/nouveau/nvkm/engine/pm/base.c| 82 ++--
 drm/nouveau/nvkm/engine/pm/priv.h| 24 +++
 3 files changed, 103 insertions(+), 4 deletions(-)

diff --git a/drm/nouveau/include/nvkm/engine/pm.h 
b/drm/nouveau/include/nvkm/engine/pm.h
index 6c2d057..130b545 100644
--- a/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drm/nouveau/include/nvkm/engine/pm.h
@@ -11,6 +11,7 @@ struct nvkm_pm {
void *profile_data;
 
struct list_head domains;
+   struct list_head sources;
u32 sequence;
 };
 
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 610c0ca..dfafefd 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -434,6 +434,67 @@ nvkm_pm_cclass = {
  * PPM engine/subdev functions
  
**/
 int
+nvkm_perfsrc_new(struct nvkm_pm *ppm, struct nvkm_perfsig *sig,
+const struct nvkm_specsrc *spec)
+{
+   const struct nvkm_specsrc *ssrc;
+   const struct nvkm_specmux *smux;
+   struct nvkm_perfsrc *src;
+   u8 source_nr = 0;
+
+   if (!spec) {
+   /* No sources are defined for this signal. */
+   return 0;
+   }
+
+   ssrc = spec;
+   while (ssrc-name) {
+   smux = ssrc-mux;
+   while (smux-name) {
+   bool found = false;
+   u8 source_id = 0;
+   u32 len;
+
+   list_for_each_entry(src, ppm-sources, head) {
+   if (src-addr == ssrc-addr 
+   src-shift == smux-shift) {
+   found = true;
+   break;
+   }
+   source_id++;
+   }
+
+   if (!found) {
+   src = kzalloc(sizeof(*src), GFP_KERNEL);
+   if (!src)
+   return -ENOMEM;
+
+   src-addr   = ssrc-addr;
+   src-mask   = smux-mask;
+   src-shift  = smux-shift;
+   src-enable = smux-enable;
+
+   len = strlen(ssrc-name) +
+ strlen(smux-name) + 2;
+   src-name = kzalloc(len, GFP_KERNEL);
+   if (!src-name)
+   return -ENOMEM;
+   snprintf(src-name, len, %s_%s, ssrc-name,
+smux-name);
+
+   list_add_tail(src-head, ppm-sources);
+   }
+
+   sig-source[source_nr++] = source_id + 1;
+   smux++;
+   }
+   ssrc++;
+   }
+
+   return 0;
+}
+
+int
 nvkm_perfdom_new(struct nvkm_pm *ppm, const char *name, u32 mask,
 u32 base, u32 size_unit, u32 size_domain,
 const struct nvkm_specdom *spec)
@@ -441,7 +502,7 @@ nvkm_perfdom_new(struct nvkm_pm *ppm, const char *name, u32 
mask,
const struct nvkm_specdom *sdom;
const struct nvkm_specsig *ssig;
struct nvkm_perfdom *dom;
-   int i;
+   int ret, i;
 
for (i = 0; i == 0 || mask; i++) {
u32 addr = base + (i * size_unit);
@@ -473,7 +534,12 @@ nvkm_perfdom_new(struct nvkm_pm *ppm, const char *name, 
u32 mask,
 
ssig = (sdom++)-signal;
while (ssig-name) {
-   dom-signal[ssig-signal].name = ssig-name;
+   struct nvkm_perfsig *sig =
+   dom-signal[ssig-signal];
+   sig-name = ssig-name;
+   ret = nvkm_perfsrc_new(ppm, sig, ssig-source);
+   if (ret)
+   return ret;
ssig++;
}
 
@@ -504,13 +570,20 @@ void
 _nvkm_pm_dtor(struct nvkm_object *object)
 {
struct nvkm_pm *ppm = (void *)object;
-   struct nvkm_perfdom *dom, *tmp

[Nouveau] [PATCH RFC 16/20] pm: allow to configure domains instead of simple counters

2015-06-07 Thread Samuel Pitoiset

Configuring counters from the userspace require the kernel to handle some
logic related to performance counters. Basically, it has to find a free
slot to assign a counter, to handle extra counting modes like B4/B6 and it
must return and error when it can't configure a counter.

In my opinion, the kernel should not handle all of that logic but it
should only write the configuration sent by the userspace without
checking anything. In other words, it should overwrite the configuration
even if it's already counting and do not return any errors.

This patch allows the userspace to configure a domain instead of
separate counters. This has the advantage to move all of the logic to
the userspace.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 bin/nv_perfmon.c   | 193 ++
 drm/nouveau/include/nvif/class.h   |  30 +++---
 drm/nouveau/include/nvif/ioctl.h   |   2 +-
 drm/nouveau/nvkm/engine/pm/base.c  | 208 +
 drm/nouveau/nvkm/engine/pm/gf100.c |  10 +-
 drm/nouveau/nvkm/engine/pm/nv40.c  |  10 +-
 drm/nouveau/nvkm/engine/pm/priv.h  |  10 +-
 7 files changed, 293 insertions(+), 170 deletions(-)

diff --git a/bin/nv_perfmon.c b/bin/nv_perfmon.c
index 50c..47b2fef 100644
--- a/bin/nv_perfmon.c
+++ b/bin/nv_perfmon.c
@@ -248,7 +248,8 @@ ui_menu_win = {
 
 struct ui_perfmon_dom {
struct list_head head;
-   struct list_head list;
+   struct list_head signals;
+   struct list_head perfdoms;
u8 id;
 };
 
@@ -260,22 +261,27 @@ struct ui_perfmon_sig {
 
 struct ui_main {
struct list_head head;
-   u32 handle;
-   struct nvif_object object;
-   const char *name;
+   struct ui_perfmon_sig *sig;
u32 clk;
u32 ctr;
u64 incr;
 };
 
+struct ui_perfdom {
+   struct nvif_object object;
+   struct list_head head;
+   struct ui_main *ctr[4];
+   u32 handle;
+};
+
 static struct list_head ui_main_list = LIST_HEAD_INIT(ui_main_list);
 static struct list_head ui_doms_list = LIST_HEAD_INIT(ui_doms_list);
+static struct list_head ui_perfdom_list = LIST_HEAD_INIT(ui_perfdom_list);
 static u32 ui_main_handle = 0xc000;
 
 static void
 ui_main_remove(struct ui_main *item)
 {
-   nvif_object_fini(item-object);
list_del(item-head);
free(item);
 }
@@ -303,7 +309,7 @@ ui_perfmon_query_signals(struct nvif_object *perfmon,
sig-signal = args.signal;
sig-name = malloc(sizeof(args.name));
strncpy(sig-name, args.name, sizeof(args.name));
-   list_add_tail(sig-head, dom-list);
+   list_add_tail(sig-head, dom-signals);
 
args.iter = prev_iter;
ret = nvif_mthd(perfmon, NVIF_PERFMON_V0_QUERY_SIGNAL,
@@ -331,7 +337,8 @@ ui_perfmon_query_domains(struct nvif_object *perfmon)
if (prev_iter) {
dom = calloc(1, sizeof(*dom));
dom-id = args.id;
-   INIT_LIST_HEAD(dom-list);
+   INIT_LIST_HEAD(dom-signals);
+   INIT_LIST_HEAD(dom-perfdoms);
list_add_tail(dom-head, ui_doms_list);
 
args.iter = prev_iter;
@@ -346,6 +353,49 @@ ui_perfmon_query_domains(struct nvif_object *perfmon)
 }
 
 static void
+ui_perfdom_init(struct ui_perfdom *dom)
+{
+   struct nvif_perfdom_init args = {};
+   int ret;
+
+   ret = nvif_mthd(dom-object, NVIF_PERFDOM_V0_INIT,
+   args, sizeof(args));
+   assert(ret == 0);
+}
+
+static void
+ui_perfdom_sample(struct ui_perfdom *dom)
+{
+   struct nvif_perfdom_sample args = {};
+   int ret;
+
+   ret = nvif_mthd(dom-object, NVIF_PERFDOM_V0_SAMPLE,
+   args, sizeof(args));
+   assert(ret == 0);
+}
+
+static void
+ui_perfdom_read(struct ui_perfdom *dom)
+{
+   struct nvif_perfdom_read_v0 args = {};
+   int ret, i;
+
+   ret = nvif_mthd(dom-object, NVIF_PERFDOM_V0_READ,
+   args, sizeof(args));
+   assert(ret == 0 || ret == -EAGAIN);
+
+   if (ret == 0) {
+   for (i = 0; i  4; i++) {
+   if (!dom-ctr[i])
+   continue;
+   dom-ctr[i]-ctr   = args.ctr[i];
+   dom-ctr[i]-incr += args.ctr[i];
+   dom-ctr[i]-clk   = args.clk;
+   }
+   }
+}
+
+static void
 ui_perfmon_init(void)
 {
struct nvif_object perfmon;
@@ -362,17 +412,37 @@ ui_perfmon_init(void)
 }
 
 static void
+ui_perfmon_free_signals(struct ui_perfmon_dom *dom)
+{
+   struct ui_perfmon_sig *sig, *next;
+
+   list_for_each_entry_safe(sig, next, dom-signals, head) {
+   list_del(sig-head);
+   free(sig-name);
+   free(sig);
+   }
+}
+
+static void

[Nouveau] [PATCH RFC 01/20] pm: prevent freeing the wrong engine context

2015-06-07 Thread Samuel Pitoiset

This fixes a crash when multiple PM engine contexts are created.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
Reviewed-by: Martin Peres martin.pe...@free.fr
---
 drm/nouveau/nvkm/engine/pm/base.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 2006c44..274457c 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -332,9 +332,12 @@ static void
 nvkm_perfctx_dtor(struct nvkm_object *object)
 {
struct nvkm_pm *ppm = (void *)object-engine;
+   struct nvkm_perfctx *ctx = (void *)object;
+
mutex_lock(nv_subdev(ppm)-mutex);
-   nvkm_engctx_destroy(ppm-context-base);
-   ppm-context = NULL;
+   nvkm_engctx_destroy(ctx-base);
+   if (ppm-context == ctx)
+   ppm-context = NULL;
mutex_unlock(nv_subdev(ppm)-mutex);
 }
 
-- 
2.4.2

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[Nouveau] [PATCH RFC 00/20] expose global performance counters

2015-06-07 Thread Samuel Pitoiset

Hello,

This series exposes global performance counters (PCOUNTER) to the userspace
through the nvif interface by reworking most of the code related to the PM
engine.

This interface will allow the userspace to control and monitor complex hardware
events like the proprietary driver already does, for example with CUPTI and
PerfKit.

For now, this series only exposes performance counters on NV50, but this is
going to be pretty similar for other families. My plan is to submit more
patches for Fermi and Kepler after this series will be reviewed.

The code of this series can be found here:

http://cgit.freedesktop.org/~hakzsam/nouveau/log/?h=nouveau_perfmon

And the corresponding libdrm branch can be found here:

http://cgit.freedesktop.org/~hakzsam/drm/log/?h=nouveau_perfmon

A full example which exposes both compute and graphics hardware events on NV50
can be found here:

http://cgit.freedesktop.org/~hakzsam/perfevent

Most of the code will be implemented in mesa once the kernel interface is
going to be upstream and stable.

Below, you can find a summary of the series:

Patches 1-2:fix a bug related to the PM engine context
Patches 3-4:remove useless PMU signals and unused functions
Patches 5-6:reorganize the nvif interface to expose more stuff
Patches 7-11:   expose PCOUNTER domains to the userspace
Patches 12-14:  implement concept of sources (ie. multiplexers)
Patches 15-17:  allow to monitor complex hardware events
Patches 18: add compute/graphics signals/sources
Patches 19-20:  expose a software methods interface for controlling PM

Feel free to make a review.
Thanks in advance!

Samuel Pitoiset (20):
  pm: prevent freeing the wrong engine context
  pm: fix a potential race condition when creating an engine context
  pm: remove pmu signals
  pm: remove unused nvkm_perfsig_wrap() function
  pm: reorganize the nvif interface
  pm: prevent creating a perfctr object when signals are not found
  pm: implement NVIF_PERFMON_V0_QUERY_DOMAIN method
  pm: allow to query signals by domain
  pm: change signal iter to u16
  pm: use hardware signals indexes instead of user-readable names
  pm: allow to monitor hardware signal index 0x00
  pm: add concept of sources
  pm: allow to query the number of sources for a signal
  pm: implement NVIF_PERFMON_V0_QUERY_SOURCE method
  pm: allow the userspace to schedule hardware counters
  pm: allow to configure domains instead of simple counters
  pm: allow the userspace to configure sources
  pm/nv50: add compute and graphics signals/sources
  sw/nv50: add some private functions to factorize code
  sw/nv50: add and interface for controlling performance counters

 bin/nv_perfmon.c  | 324 
 drm/nouveau/include/nvif/class.h  |  68 +++-
 drm/nouveau/include/nvif/ioctl.h  |   5 +-
 drm/nouveau/include/nvkm/engine/pm.h  |   6 +-
 drm/nouveau/nvkm/engine/device/nv50.c |   2 +-
 drm/nouveau/nvkm/engine/pm/Kbuild |   2 +-
 drm/nouveau/nvkm/engine/pm/base.c | 685 +-
 drm/nouveau/nvkm/engine/pm/daemon.c   | 108 --
 drm/nouveau/nvkm/engine/pm/g84.c  | 101 -
 drm/nouveau/nvkm/engine/pm/gf100.c|  13 +-
 drm/nouveau/nvkm/engine/pm/gk104.c|   6 -
 drm/nouveau/nvkm/engine/pm/gk110.c|   4 -
 drm/nouveau/nvkm/engine/pm/gt200.c| 163 
 drm/nouveau/nvkm/engine/pm/gt215.c| 104 --
 drm/nouveau/nvkm/engine/pm/nv40.c |   8 +-
 drm/nouveau/nvkm/engine/pm/nv50.c | 136 ++-
 drm/nouveau/nvkm/engine/pm/priv.h |  53 ++-
 drm/nouveau/nvkm/engine/sw/nv50.c | 216 ++-
 drm/nouveau/nvkm/engine/sw/nv50.h |   6 +
 19 files changed, 1561 insertions(+), 449 deletions(-)
 delete mode 100644 drm/nouveau/nvkm/engine/pm/daemon.c
 create mode 100644 drm/nouveau/nvkm/engine/pm/gt200.c

-- 
2.4.2

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[Nouveau] [PATCH RFC 02/20] pm: fix a potential race condition when creating an engine context

2015-06-07 Thread Samuel Pitoiset

There is always the possiblity that the ppm-context pointer would get
partially updated and accidentally would equal ctx. This would allow two
contexts to co-exist, which is not acceptable. Moving the test to the
critical section takes care of this problem.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
Signed-off-by: Martin Peres martin.pe...@free.fr
---
 drm/nouveau/nvkm/engine/pm/base.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 274457c..4cf36a3 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -358,12 +358,11 @@ nvkm_perfctx_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
mutex_lock(nv_subdev(ppm)-mutex);
if (ppm-context == NULL)
ppm-context = ctx;
-   mutex_unlock(nv_subdev(ppm)-mutex);
-
if (ctx != ppm-context)
-   return -EBUSY;
+   ret = -EBUSY;
+   mutex_unlock(nv_subdev(ppm)-mutex);
 
-   return 0;
+   return ret;
 }
 
 struct nvkm_oclass
-- 
2.4.2

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[Nouveau] [PATCH RFC 06/20] pm: prevent creating a perfctr object when signals are not found

2015-06-07 Thread Samuel Pitoiset

Since a new class has been introduced to query signals, we can now
return an error when the userspace wants to monitor unknown signals.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/pm/base.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index cb88170..2f85147 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -294,6 +294,9 @@ nvkm_perfctr_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
return -EINVAL;
}
 
+   if (!dom)
+   return -EINVAL;
+
ret = nvkm_object_create(parent, engine, oclass, 0, ctr);
*pobject = nv_object(ctr);
if (ret)
@@ -305,8 +308,7 @@ nvkm_perfctr_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
ctr-signal[1] = sig[1];
ctr-signal[2] = sig[2];
ctr-signal[3] = sig[3];
-   if (dom)
-   list_add_tail(ctr-head, dom-list);
+   list_add_tail(ctr-head, dom-list);
return 0;
 }
 
-- 
2.4.2

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[Nouveau] [PATCH RFC 04/20] pm: remove unused nvkm_perfsig_wrap() function

2015-06-07 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
Reviewed-by: Martin Peres martin.pe...@free.fr
---
 drm/nouveau/nvkm/engine/pm/base.c | 20 
 drm/nouveau/nvkm/engine/pm/priv.h |  4 
 2 files changed, 24 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 4cf36a3..7b07e8b 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -79,26 +79,6 @@ nvkm_perfsig_find(struct nvkm_pm *ppm, const char *name, u32 
size,
return nvkm_perfsig_find_(dom, name, size);
 }
 
-struct nvkm_perfctr *
-nvkm_perfsig_wrap(struct nvkm_pm *ppm, const char *name,
- struct nvkm_perfdom **pdom)
-{
-   struct nvkm_perfsig *sig;
-   struct nvkm_perfctr *ctr;
-
-   sig = nvkm_perfsig_find(ppm, name, strlen(name), pdom);
-   if (!sig)
-   return NULL;
-
-   ctr = kzalloc(sizeof(*ctr), GFP_KERNEL);
-   if (ctr) {
-   ctr-signal[0] = sig;
-   ctr-logic_op = 0x;
-   }
-
-   return ctr;
-}
-
 
/***
  * Perfmon object classes
  
**/
diff --git a/drm/nouveau/nvkm/engine/pm/priv.h 
b/drm/nouveau/nvkm/engine/pm/priv.h
index 95796c7..06a6e60 100644
--- a/drm/nouveau/nvkm/engine/pm/priv.h
+++ b/drm/nouveau/nvkm/engine/pm/priv.h
@@ -31,10 +31,6 @@ struct nvkm_perfsig {
const char *name;
 };
 
-struct nvkm_perfdom;
-struct nvkm_perfctr *
-nvkm_perfsig_wrap(struct nvkm_pm *, const char *, struct nvkm_perfdom **);
-
 struct nvkm_specdom {
u16 signal_nr;
const struct nvkm_specsig *signal;
-- 
2.4.2

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[Nouveau] [PATCH RFC 10/20] pm: use hardware signals indexes instead of user-readable names

2015-06-07 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 bin/nv_perfmon.c  |  6 +++--
 drm/nouveau/include/nvif/class.h  | 11 ++---
 drm/nouveau/nvkm/engine/pm/base.c | 52 +--
 3 files changed, 23 insertions(+), 46 deletions(-)

diff --git a/bin/nv_perfmon.c b/bin/nv_perfmon.c
index 043d864..50c 100644
--- a/bin/nv_perfmon.c
+++ b/bin/nv_perfmon.c
@@ -255,6 +255,7 @@ struct ui_perfmon_dom {
 struct ui_perfmon_sig {
struct list_head head;
char *name;
+   u8 signal;
 };
 
 struct ui_main {
@@ -299,6 +300,7 @@ ui_perfmon_query_signals(struct nvif_object *perfmon,
if (prev_iter) {
nr_signals++;
sig = calloc(1, sizeof(*sig));
+   sig-signal = args.signal;
sig-name = malloc(sizeof(args.name));
strncpy(sig-name, args.name, sizeof(args.name));
list_add_tail(sig-head, dom-list);
@@ -392,14 +394,14 @@ ui_main_select(void)
list_for_each_entry(sig, dom-list, head) {
struct nvif_perfctr_v0 args = {
.logic_op = 0x,
+   .domain = dom-id,
};
 
item = calloc(1, sizeof(*item));
item-handle = ui_main_handle++;
item-name = sig-name;
 
-   strncpy(args.name[0], item-name, sizeof(args.name[0]));
-
+   args.signal[0] = sig-signal;
ret = nvif_object_init(nvif_object(device), NULL,
   item-handle,
   NVIF_IOCTL_NEW_V0_PERFCTR,
diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index 871247c..9e4db3a 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -267,7 +267,8 @@ struct nvif_perfmon_query_signal_v0 {
__u8  version;
__u8  domain;
__u16 iter;
-   __u8  pad03[4];
+   __u8  signal;
+   __u8  pad04[3];
char  name[64];
 };
 
@@ -278,10 +279,12 @@ struct nvif_perfmon_query_signal_v0 {
 
 struct nvif_perfctr_v0 {
__u8  version;
-   __u8  pad01[1];
+   __u8  domain;
+   __u8  pad02[2];
__u16 logic_op;
-   __u8  pad04[4];
-   char  name[4][64];
+   __u8  pad04[2];
+   __u8  signal[4];
+   __u8  pad06[4];
 };
 
 #define NVIF_PERFCTR_V0_SAMPLE 0x00
diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index fab0598..71834b9 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -73,49 +73,22 @@ nvkm_perfdom_find(struct nvkm_pm *ppm, int di)
return NULL;
 }
 
-static struct nvkm_perfsig *
-nvkm_perfsig_find_(struct nvkm_perfdom *dom, const char *name, u32 size)
-{
-   char path[64];
-   int i;
-
-   if (name[0] != '/') {
-   for (i = 0; i  dom-signal_nr; i++) {
-   if ( dom-signal[i].name 
-   !strncmp(name, dom-signal[i].name, size))
-   return dom-signal[i];
-   }
-   } else {
-   for (i = 0; i  dom-signal_nr; i++) {
-   snprintf(path, sizeof(path), /%s/%02x, dom-name, i);
-   if (!strncmp(name, path, size))
-   return dom-signal[i];
-   }
-   }
-
-   return NULL;
-}
-
 struct nvkm_perfsig *
-nvkm_perfsig_find(struct nvkm_pm *ppm, const char *name, u32 size,
+nvkm_perfsig_find(struct nvkm_pm *ppm, uint8_t di, uint8_t si,
  struct nvkm_perfdom **pdom)
 {
struct nvkm_perfdom *dom = *pdom;
-   struct nvkm_perfsig *sig;
 
if (dom == NULL) {
-   list_for_each_entry(dom, ppm-domains, head) {
-   sig = nvkm_perfsig_find_(dom, name, size);
-   if (sig) {
-   *pdom = dom;
-   return sig;
-   }
-   }
-
-   return NULL;
+   dom = nvkm_perfdom_find(ppm, di);
+   if (dom == NULL)
+   return NULL;
+   *pdom = dom;
}
 
-   return nvkm_perfsig_find_(dom, name, size);
+   if (!dom-signal[si].name)
+   return NULL;
+   return dom-signal[si];
 }
 
 
/***
@@ -200,6 +173,7 @@ nvkm_perfmon_mthd_query_signal(struct nvkm_object *object, 
void *data, u32 size)
} else {
strncpy(args-v0.name, name, sizeof(args-v0.name));
}
+   args-v0.signal = si;
}
 
while (++si  dom

[Nouveau] [PATCH RFC 11/20] pm: allow to monitor hardware signal index 0x00

2015-06-07 Thread Samuel Pitoiset

This signal index must be always allowed even if it's not clearly
defined in a domain in order to monitor a counter like 0x03020100
because it's the default value of signals.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/pm/base.c  | 4 ++--
 drm/nouveau/nvkm/engine/pm/gf100.c | 6 --
 drm/nouveau/nvkm/engine/pm/nv40.c  | 6 --
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 71834b9..610c0ca 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -333,10 +333,10 @@ nvkm_perfctr_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
} else
return ret;
 
-   for (i = 0; i  ARRAY_SIZE(args-v0.signal)  args-v0.signal[i]; i++) 
{
+   for (i = 0; i  ARRAY_SIZE(args-v0.signal); i++) {
sig[i] = nvkm_perfsig_find(ppm, args-v0.domain,
   args-v0.signal[i], dom);
-   if (!sig[i])
+   if (args-v0.signal[i]  !sig[i])
return -EINVAL;
}
 
diff --git a/drm/nouveau/nvkm/engine/pm/gf100.c 
b/drm/nouveau/nvkm/engine/pm/gf100.c
index 69303b5..41350d6 100644
--- a/drm/nouveau/nvkm/engine/pm/gf100.c
+++ b/drm/nouveau/nvkm/engine/pm/gf100.c
@@ -48,8 +48,10 @@ gf100_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom 
*dom,
u32 src = 0x;
int i;
 
-   for (i = 0; i  4  ctr-signal[i]; i++)
-   src |= (ctr-signal[i] - dom-signal)  (i * 8);
+   for (i = 0; i  4; i++) {
+   if (ctr-signal[i])
+   src |= (ctr-signal[i] - dom-signal)  (i * 8);
+   }
 
nv_wr32(priv, dom-addr + 0x09c, 0x00040002);
nv_wr32(priv, dom-addr + 0x100, 0x);
diff --git a/drm/nouveau/nvkm/engine/pm/nv40.c 
b/drm/nouveau/nvkm/engine/pm/nv40.c
index ff22f06..603874e 100644
--- a/drm/nouveau/nvkm/engine/pm/nv40.c
+++ b/drm/nouveau/nvkm/engine/pm/nv40.c
@@ -33,8 +33,10 @@ nv40_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom 
*dom,
u32 src = 0x;
int i;
 
-   for (i = 0; i  4  ctr-signal[i]; i++)
-   src |= (ctr-signal[i] - dom-signal)  (i * 8);
+   for (i = 0; i  4; i++) {
+   if (ctr-signal[i])
+   src |= (ctr-signal[i] - dom-signal)  (i * 8);
+   }
 
nv_wr32(priv, 0x00a7c0 + dom-addr, 0x0001);
nv_wr32(priv, 0x00a400 + dom-addr + (cntr-base.slot * 0x40), src);
-- 
2.4.2

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[Nouveau] [RFC 2/3] util: add LIST_MOVE_TAIL to list.h

2015-06-02 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/util/list.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/util/list.h b/src/util/list.h
index fb566f5..c782ef5 100644
--- a/src/util/list.h
+++ b/src/util/list.h
@@ -116,12 +116,21 @@ static inline void list_validate(struct list_head *list)
   assert(node-next-prev == node  node-prev-next == node);
 }
 
+static inline void list_move_tail(struct list_head *list,
+  struct list_head *head)
+{
+list-next-prev = list-prev;
+list-prev-next = list-next;
+list_addtail(list, head);
+}
+
 #define LIST_INITHEAD(__item) list_inithead(__item)
 #define LIST_ADD(__item, __list) list_add(__item, __list)
 #define LIST_ADDTAIL(__item, __list) list_addtail(__item, __list)
 #define LIST_REPLACE(__from, __to) list_replace(__from, __to)
 #define LIST_DEL(__item) list_del(__item)
 #define LIST_DELINIT(__item) list_delinit(__item)
+#define LIST_MOVE_TAIL(__list, __head) list_move_tail(__list, __head)
 
 #define LIST_ENTRY(__type, __item, __field)   \
 ((__type *)(((char *)(__item)) - offsetof(__type, __field)))
-- 
2.4.2

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[Nouveau] [RFC 1/3] util: move LIST_FIRST_ENTRY from nv30_query.c to list.h

2015-06-02 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv30/nv30_query.c | 3 ---
 src/util/list.h   | 3 +++
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv30/nv30_query.c 
b/src/gallium/drivers/nouveau/nv30/nv30_query.c
index 516ee83..80a9755 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_query.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_query.c
@@ -28,9 +28,6 @@
 #include nv30/nv30_screen.h
 #include nv30/nv30_context.h
 
-#define LIST_FIRST_ENTRY(__type, __item, __field) \
-   LIST_ENTRY(__type, (__item)-next, __field)
-
 struct nv30_query_object {
struct list_head list;
struct nouveau_heap *hw;
diff --git a/src/util/list.h b/src/util/list.h
index 9460347..fb566f5 100644
--- a/src/util/list.h
+++ b/src/util/list.h
@@ -126,6 +126,9 @@ static inline void list_validate(struct list_head *list)
 #define LIST_ENTRY(__type, __item, __field)   \
 ((__type *)(((char *)(__item)) - offsetof(__type, __field)))
 
+#define LIST_FIRST_ENTRY(__type, __item, __field) \
+   LIST_ENTRY(__type, (__item)-next, __field)
+
 #define LIST_IS_EMPTY(__list)   \
 ((__list)-next == (__list))
 
-- 
2.4.2

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[Nouveau] [RFC 3/3] st/perfkit: add a state tracker for NVIDIA PerfKit

2015-06-02 Thread Samuel Pitoiset

This state tracker implements NVIDIA PerfKit 3.0.1 which is currently
only available on Windows 7+ for desktop graphics cards. A Linux/Android
implementation is provided by NVIDIA but only for NVIDIA Tegra K1.

This Gallium state tracker is loosely based on the VDPAU tracker and since
it uses the pipe_query interface, other drivers which expose performance
counters should be also able to expose them easily through PerfKit.

Unlike GL_AMD_performance_monitor, NVIDIA PerfKit allows to monitor
multi-passes events and the API supports different types of performance
counters (GPU, CPU, OpenGL).

Currently, only MP counters for NVC0:NVE4 Nouveau drivers are exposed.

To be able to use NVIDIA PerfKit from your OpenGL applications, you will
need to install the wrapper library which includes the headers of the API.

You can download this library from:
http://cgit.freedesktop.org/~hakzsam/libperfkit/

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 configure.ac   |  30 ++
 src/gallium/Makefile.am|   4 +
 src/gallium/state_trackers/perfkit/Makefile.am |  41 ++
 .../state_trackers/perfkit/Makefile.sources|   8 +
 src/gallium/state_trackers/perfkit/context.c   | 186 
 src/gallium/state_trackers/perfkit/counter.c   | 522 +
 src/gallium/state_trackers/perfkit/device.c|  91 
 src/gallium/state_trackers/perfkit/entrypoint.c|  78 +++
 src/gallium/state_trackers/perfkit/monitoring.c| 360 ++
 .../state_trackers/perfkit/perfkit_private.h   | 145 ++
 src/gallium/state_trackers/perfkit/util.c  |  56 +++
 src/gallium/targets/dri-perfkit.dyn|   3 +
 src/gallium/targets/perfkit/Makefile.am| 123 +
 src/gallium/targets/perfkit/perfkit.sym|   7 +
 src/gallium/targets/perfkit/target.c   |   1 +
 15 files changed, 1655 insertions(+)
 create mode 100644 src/gallium/state_trackers/perfkit/Makefile.am
 create mode 100644 src/gallium/state_trackers/perfkit/Makefile.sources
 create mode 100644 src/gallium/state_trackers/perfkit/context.c
 create mode 100644 src/gallium/state_trackers/perfkit/counter.c
 create mode 100644 src/gallium/state_trackers/perfkit/device.c
 create mode 100644 src/gallium/state_trackers/perfkit/entrypoint.c
 create mode 100644 src/gallium/state_trackers/perfkit/monitoring.c
 create mode 100644 src/gallium/state_trackers/perfkit/perfkit_private.h
 create mode 100644 src/gallium/state_trackers/perfkit/util.c
 create mode 100644 src/gallium/targets/dri-perfkit.dyn
 create mode 100644 src/gallium/targets/perfkit/Makefile.am
 create mode 100644 src/gallium/targets/perfkit/perfkit.sym
 create mode 100644 src/gallium/targets/perfkit/target.c

diff --git a/configure.ac b/configure.ac
index d32aa24..6c7aa03 100644
--- a/configure.ac
+++ b/configure.ac
@@ -79,6 +79,7 @@ LIBUDEV_REQUIRED=151
 GLPROTO_REQUIRED=1.4.14
 LIBOMXIL_BELLAGIO_REQUIRED=0.0
 LIBVA_REQUIRED=0.35.0
+PERFKIT_REQUIRED=3.0
 VDPAU_REQUIRED=0.4.1
 WAYLAND_REQUIRED=1.2.0
 XCB_REQUIRED=1.9.3
@@ -790,6 +791,11 @@ AC_ARG_ENABLE([vdpau],
  [enable vdpau library @:@default=auto@:@])],
[enable_vdpau=$enableval],
[enable_vdpau=auto])
+AC_ARG_ENABLE([perfkit],
+   [AS_HELP_STRING([--enable-perfkit],
+ [enable perfkit library @:@default=auto@:@])],
+   [enable_perfkit=$enableval],
+   [enable_perfkit=auto])
 AC_ARG_ENABLE([omx],
[AS_HELP_STRING([--enable-omx],
  [enable OpenMAX library @:@default=disabled@:@])],
@@ -856,6 +862,7 @@ if test x$enable_opengl = xno -a \
 x$enable_xa = xno -a \
 x$enable_xvmc = xno -a \
 x$enable_vdpau = xno -a \
+x$enable_perfkit = xno -a \
 x$enable_omx = xno -a \
 x$enable_va = xno -a \
 x$enable_opencl = xno; then
@@ -1584,6 +1591,10 @@ if test -n $with_gallium_drivers -a 
x$with_gallium_drivers != xswrast; then
PKG_CHECK_EXISTS([vdpau = $VDPAU_REQUIRED], [enable_vdpau=yes], 
[enable_vdpau=no])
 fi
 
+if test x$enable_perfkit = xauto; then
+   PKG_CHECK_EXISTS([perfkit], [enable_perfkit=yes], [enable_perfkit=no])
+fi
+
 if test x$enable_omx = xauto; then
PKG_CHECK_EXISTS([libomxil-bellagio = $LIBOMXIL_BELLAGIO_REQUIRED], 
[enable_omx=yes], [enable_omx=no])
 fi
@@ -1623,6 +1634,12 @@ if test x$enable_vdpau = xyes; then
 fi
 AM_CONDITIONAL(HAVE_ST_VDPAU, test x$enable_vdpau = xyes)
 
+if test x$enable_perfkit = xyes; then
+PKG_CHECK_MODULES([PERFKIT], [perfkit = $PERFKIT_REQUIRED])
+enable_gallium_loader=$enable_shared_pipe_drivers
+fi
+AM_CONDITIONAL(HAVE_ST_PERFKIT, test x$enable_perfkit = xyes)
+
 if test x$enable_omx = xyes; then
 PKG_CHECK_MODULES([OMX], [libomxil-bellagio = 
$LIBOMXIL_BELLAGIO_REQUIRED])
 enable_gallium_loader=$enable_shared_pipe_drivers
@@ -1979,6 +1996,14 @@ AC_ARG_WITH([vdpau-libdir],
 [VDPAU_LIB_INSTALL_DIR='${libdir}/vdpau'])
 AC_SUBST

[Nouveau] [RFC 0/3] implement nouveau-perfKit

2015-06-02 Thread Samuel Pitoiset

Hello,

A series I started a long time ago but now I need some feedbacks. :-)

This state tracker implements NVIDIA PerfKit 3.0.1 which is currently
only available on Windows 7+ for desktop graphics cards. A Linux/Android
implementation is provided by NVIDIA but only for NVIDIA Tegra K1.

This Gallium state tracker is loosely based on the VDPAU tracker and since
it uses the pipe_query interface, other drivers which expose performance
counters should be also able to expose them easily through PerfKit.

Unlike GL_AMD_performance_monitor, NVIDIA PerfKit allows to monitor
multi-passes events and the API supports different types of performance
counters (GPU, CPU, OpenGL).

Currently, only MP counters for NVC0:NVE4 Nouveau drivers are exposed.

To be able to use NVIDIA PerfKit from your OpenGL applications, you will
need to install the wrapper library which includes the headers of the API.

You can download this library from:
http://cgit.freedesktop.org/~hakzsam/libperfkit/

The wrapper library contains a large number of unit tests (~120) that helped
me to understand the API. More than 85% of test compliance for mesa.

Feel free to make a review of the perfkit state tracker and libperfkit.
Thanks!

Samuel Pitoiset (3):
  util: move LIST_FIRST_ENTRY from nv30_query.c to list.h
  util: add LIST_MOVE_TAIL to list.h
  st/perfkit: add a state tracker for NVIDIA PerfKit

 configure.ac   |  30 ++
 src/gallium/Makefile.am|   4 +
 src/gallium/drivers/nouveau/nv30/nv30_query.c  |   3 -
 src/gallium/state_trackers/perfkit/Makefile.am |  41 ++
 .../state_trackers/perfkit/Makefile.sources|   8 +
 src/gallium/state_trackers/perfkit/context.c   | 186 
 src/gallium/state_trackers/perfkit/counter.c   | 522 +
 src/gallium/state_trackers/perfkit/device.c|  91 
 src/gallium/state_trackers/perfkit/entrypoint.c|  78 +++
 src/gallium/state_trackers/perfkit/monitoring.c| 360 ++
 .../state_trackers/perfkit/perfkit_private.h   | 145 ++
 src/gallium/state_trackers/perfkit/util.c  |  56 +++
 src/gallium/targets/dri-perfkit.dyn|   3 +
 src/gallium/targets/perfkit/Makefile.am| 123 +
 src/gallium/targets/perfkit/perfkit.sym|   7 +
 src/gallium/targets/perfkit/target.c   |   1 +
 src/util/list.h|  12 +
 17 files changed, 1667 insertions(+), 3 deletions(-)
 create mode 100644 src/gallium/state_trackers/perfkit/Makefile.am
 create mode 100644 src/gallium/state_trackers/perfkit/Makefile.sources
 create mode 100644 src/gallium/state_trackers/perfkit/context.c
 create mode 100644 src/gallium/state_trackers/perfkit/counter.c
 create mode 100644 src/gallium/state_trackers/perfkit/device.c
 create mode 100644 src/gallium/state_trackers/perfkit/entrypoint.c
 create mode 100644 src/gallium/state_trackers/perfkit/monitoring.c
 create mode 100644 src/gallium/state_trackers/perfkit/perfkit_private.h
 create mode 100644 src/gallium/state_trackers/perfkit/util.c
 create mode 100644 src/gallium/targets/dri-perfkit.dyn
 create mode 100644 src/gallium/targets/perfkit/Makefile.am
 create mode 100644 src/gallium/targets/perfkit/perfkit.sym
 create mode 100644 src/gallium/targets/perfkit/target.c

-- 
2.4.2

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Re: [Nouveau] [PATCH RFC 05/20] pm: reorganize the nvif interface

2015-06-09 Thread Samuel Pitoiset




On 06/09/2015 12:02 AM, Ben Skeggs wrote:

On 8 June 2015 at 06:40, Samuel Pitoiset samuel.pitoi...@gmail.com wrote:

This commit introduces the NVIF_IOCTL_NEW_V0_PERFMON class which will be
used in order to query domains, signals and sources. This separates the
querying and the counting interface.

Hey Samuel,

I've merged patches 1-4 already, I've got some comments on this one,
but after they're solved I'm happy to merge up to (and including)
patch 18.  Patches 19/20, I need to think about some more.



Hey Ben,

Thanks for reviewing this series so quickly. :-)


Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
  bin/nv_perfmon.c  | 12 ++--
  drm/nouveau/include/nvif/class.h  | 26 --
  drm/nouveau/include/nvif/ioctl.h  |  5 +++--
  drm/nouveau/nvkm/engine/pm/base.c | 38 --
  4 files changed, 57 insertions(+), 24 deletions(-)

diff --git a/bin/nv_perfmon.c b/bin/nv_perfmon.c
index a8c5838..30a3138 100644
--- a/bin/nv_perfmon.c
+++ b/bin/nv_perfmon.c
@@ -600,7 +600,7 @@ main(int argc, char **argv)
 const char *cfg = NULL;
 const char *dbg = error;
 u64 dev = ~0ULL;
-   struct nvif_perfctr_query_v0 args = {};
+   struct nvif_perfmon_query_signal_v0 args = {};
 struct nvif_client *client;
 struct nvif_object object;
 int ret, c, k;
@@ -644,15 +644,14 @@ main(int argc, char **argv)
 }

 ret = nvif_object_init(nvif_object(device), NULL, 0xdeadbeef,
-  NVIF_IOCTL_NEW_V0_PERFCTR,
-  (struct nvif_perfctr_v0) {
-  }, sizeof(struct nvif_perfctr_v0), object);
+  NVIF_IOCTL_NEW_V0_PERFMON, NULL, 0, object);
 assert(ret == 0);
 do {
 u32 prev_iter = args.iter;

 args.name[0] = '\0';
-   ret = nvif_mthd(object, NVIF_PERFCTR_V0_QUERY, args, 
sizeof(args));
+   ret = nvif_mthd(object, NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
 assert(ret == 0);

 if (prev_iter) {
@@ -663,7 +662,8 @@ main(int argc, char **argv)
 args.iter = prev_iter;
 strncpy(signals[nr_signals - 1], args.name,
 sizeof(args.name));
-   ret = nvif_mthd(object, NVIF_PERFCTR_V0_QUERY, args, 
sizeof(args));
+   ret = nvif_mthd(object, NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
 assert(ret == 0);
 }
 } while (args.iter != 0x);
diff --git a/drm/nouveau/include/nvif/class.h b/drm/nouveau/include/nvif/class.h
index 64f8b2f..11935a0 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -251,6 +251,20 @@ struct gf110_dma_v0 {
   * perfmon
   
**/

+#define NVIF_PERFMON_V0_QUERY_SIGNAL   0x00
+
+struct nvif_perfmon_query_signal_v0 {
+   __u8  version;
+   __u8  pad01[3];
+   __u32 iter;
+   char  name[64];
+};
+
+
+/***
+ * perfctr
+ 
**/
+
  struct nvif_perfctr_v0 {
 __u8  version;
 __u8  pad01[1];
@@ -259,16 +273,8 @@ struct nvif_perfctr_v0 {
 char  name[4][64];
  };

-#define NVIF_PERFCTR_V0_QUERY  0x00
-#define NVIF_PERFCTR_V0_SAMPLE 0x01
-#define NVIF_PERFCTR_V0_READ   0x02
-
-struct nvif_perfctr_query_v0 {
-   __u8  version;
-   __u8  pad01[3];
-   __u32 iter;
-   char  name[64];
-};
+#define NVIF_PERFCTR_V0_SAMPLE 0x00
+#define NVIF_PERFCTR_V0_READ   0x01

  struct nvif_perfctr_sample {
  };
diff --git a/drm/nouveau/include/nvif/ioctl.h b/drm/nouveau/include/nvif/ioctl.h
index 4cd8e32..517cd27 100644
--- a/drm/nouveau/include/nvif/ioctl.h
+++ b/drm/nouveau/include/nvif/ioctl.h
@@ -49,8 +49,9 @@ struct nvif_ioctl_new_v0 {
 __u64 token;
 __u32 handle;
  /* these class numbers are made up by us, and not nvidia-assigned */
-#define NVIF_IOCTL_NEW_V0_PERFCTR0x
-#define NVIF_IOCTL_NEW_V0_CONTROL0xfffe
+#define NVIF_IOCTL_NEW_V0_PERFMON0x
+#define NVIF_IOCTL_NEW_V0_PERFCTR0xfffe
+#define NVIF_IOCTL_NEW_V0_CONTROL0xfffd

It doesn't matter

[Nouveau] [RFC PATCH 6/8] nv50: add support for compute/graphics global performance counters

2015-06-22 Thread Samuel Pitoiset

This commit adds support for both compute and graphics global
performance counters which have been reverse engineered with
CUPTI (Linux) and PerfKit (Windows).

Currently, only one query type can be monitored at the same time because
the Gallium's HUD doesn't fit pretty well. This will be improved later.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv50/nv50_query.c  | 1057 +++-
 src/gallium/drivers/nouveau/nv50/nv50_screen.h |   35 +
 2 files changed, 1087 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c 
b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index 1162110..b9d2914 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -27,6 +27,8 @@
 #include nv50/nv50_context.h
 #include nv_object.xml.h
 
+#include nouveau_perfmon.h
+
 #define NV50_QUERY_STATE_READY   0
 #define NV50_QUERY_STATE_ACTIVE  1
 #define NV50_QUERY_STATE_ENDED   2
@@ -51,10 +53,25 @@ struct nv50_query {
boolean is64bit;
struct nouveau_mm_allocation *mm;
struct nouveau_fence *fence;
+   struct nouveau_object *perfdom;
 };
 
 #define NV50_QUERY_ALLOC_SPACE 256
 
+#ifdef DEBUG
+static void nv50_hw_pm_dump_perfdom(struct nvif_perfdom_v0 *args);
+#endif
+
+static boolean
+nv50_hw_pm_query_create(struct nv50_context *, struct nv50_query *);
+static void
+nv50_hw_pm_query_destroy(struct nv50_context *, struct nv50_query *);
+static boolean
+nv50_hw_pm_query_begin(struct nv50_context *, struct nv50_query *);
+static void nv50_hw_pm_query_end(struct nv50_context *, struct nv50_query *);
+static boolean nv50_hw_pm_query_result(struct nv50_context *,
+struct nv50_query *, boolean, void *);
+
 static INLINE struct nv50_query *
 nv50_query(struct pipe_query *pipe)
 {
@@ -96,12 +113,18 @@ nv50_query_allocate(struct nv50_context *nv50, struct 
nv50_query *q, int size)
 static void
 nv50_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
 {
+   struct nv50_context *nv50 = nv50_context(pipe);
+   struct nv50_query *q = nv50_query(pq);
+
if (!pq)
   return;
 
-   nv50_query_allocate(nv50_context(pipe), nv50_query(pq), 0);
-   nouveau_fence_ref(NULL, nv50_query(pq)-fence);
-   FREE(nv50_query(pq));
+   if ((q-type = NV50_HW_PM_QUERY(0)  q-type = NV50_HW_PM_QUERY_LAST))
+  nv50_hw_pm_query_destroy(nv50, q);
+
+   nv50_query_allocate(nv50, q, 0);
+   nouveau_fence_ref(NULL, q-fence);
+   FREE(q);
 }
 
 static struct pipe_query *
@@ -130,6 +153,11 @@ nv50_query_create(struct pipe_context *pipe, unsigned 
type, unsigned index)
   q-data -= 32 / sizeof(*q-data); /* we advance before query_begin ! */
}
 
+   if ((q-type = NV50_HW_PM_QUERY(0)  q-type = NV50_HW_PM_QUERY_LAST)) {
+  if (!nv50_hw_pm_query_create(nv50, q))
+ return NULL;
+   }
+
return (struct pipe_query *)q;
 }
 
@@ -154,6 +182,7 @@ nv50_query_begin(struct pipe_context *pipe, struct 
pipe_query *pq)
struct nv50_context *nv50 = nv50_context(pipe);
struct nouveau_pushbuf *push = nv50-base.pushbuf;
struct nv50_query *q = nv50_query(pq);
+   boolean ret = TRUE;
 
if (!pq)
   return FALSE;
@@ -211,10 +240,13 @@ nv50_query_begin(struct pipe_context *pipe, struct 
pipe_query *pq)
   nv50_query_get(push, q, 0x10, 0x5002);
   break;
default:
+  if ((q-type = NV50_HW_PM_QUERY(0)  q-type = 
NV50_HW_PM_QUERY_LAST)) {
+ ret = nv50_hw_pm_query_begin(nv50, q);
+  }
   break;
}
q-state = NV50_QUERY_STATE_ACTIVE;
-   return true;
+   return ret;
 }
 
 static void
@@ -274,7 +306,9 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query 
*pq)
   q-state = NV50_QUERY_STATE_READY;
   break;
default:
-  assert(0);
+  if ((q-type = NV50_HW_PM_QUERY(0)  q-type = 
NV50_HW_PM_QUERY_LAST)) {
+ nv50_hw_pm_query_end(nv50, q);
+  }
   break;
}
 
@@ -309,6 +343,10 @@ nv50_query_result(struct pipe_context *pipe, struct 
pipe_query *pq,
if (!pq)
   return FALSE;
 
+   if ((q-type = NV50_HW_PM_QUERY(0)  q-type = NV50_HW_PM_QUERY_LAST)) {
+  return nv50_hw_pm_query_result(nv50, q, wait, result);
+   }
+
if (q-state != NV50_QUERY_STATE_READY)
   nv50_query_update(q);
 
@@ -488,6 +526,1015 @@ nva0_so_target_save_offset(struct pipe_context *pipe,
nv50_query_end(pipe, targ-pq);
 }
 
+/* === HARDWARE GLOBAL PERFORMANCE COUNTERS for NV50 === */
+
+struct nv50_hw_pm_source_cfg
+{
+   const char *name;
+   uint64_t value;
+};
+
+struct nv50_hw_pm_signal_cfg
+{
+   const char *name;
+   const struct nv50_hw_pm_source_cfg src[8];
+};
+
+struct nv50_hw_pm_counter_cfg
+{
+   uint16_t logic_op;
+   const struct nv50_hw_pm_signal_cfg sig[4];
+};
+
+enum nv50_hw_pm_query_display
+{
+   NV50_HW_PM_EVENT_DISPLAY_RAW,
+   NV50_HW_PM_EVENT_DISPLAY_RATIO,
+};
+
+enum nv50_hw_pm_query_count
+{
+   NV50_HW_PM_EVENT_COUNT_SIMPLE,
+   NV50_HW_PM_EVENT_COUNT_B4

[Nouveau] [RFC PATCH 3/8] nv50: allocate and map a notifier buffer object for PM

2015-06-22 Thread Samuel Pitoiset

This notifier buffer object will be used to read back global performance
counters results written by the kernel.

For each domain, we will store the handle of the perfdom object, an
array of 4 counters and the number of cycles. Like the Gallium's HUD,
we keep a list of busy queries in a ring in order to prevent stalls
when reading queries.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 29 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.h |  6 ++
 2 files changed, 35 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index c985344..3a99cc8 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -368,6 +368,7 @@ nv50_screen_destroy(struct pipe_screen *pscreen)
nouveau_object_del(screen-m2mf);
nouveau_object_del(screen-sync);
nouveau_object_del(screen-sw);
+   nouveau_object_del(screen-query);
 
nouveau_screen_fini(screen-base);
 
@@ -699,9 +700,11 @@ nv50_screen_create(struct nouveau_device *dev)
struct nv50_screen *screen;
struct pipe_screen *pscreen;
struct nouveau_object *chan;
+   struct nv04_fifo *fifo;
uint64_t value;
uint32_t tesla_class;
unsigned stack_size;
+   uint32_t length;
int ret;
 
screen = CALLOC_STRUCT(nv50_screen);
@@ -727,6 +730,7 @@ nv50_screen_create(struct nouveau_device *dev)
screen-base.pushbuf-rsvd_kick = 5;
 
chan = screen-base.channel;
+   fifo = chan-data;
 
pscreen-destroy = nv50_screen_destroy;
pscreen-context_create = nv50_create;
@@ -772,6 +776,23 @@ nv50_screen_create(struct nouveau_device *dev)
   goto fail;
}
 
+   /* Compute size (in bytes) of the notifier buffer object which is used
+* in order to read back global performance counters results written
+* by the kernel. For each domain, we store the handle of the perfdom
+* object, an array of 4 counters and the number of cycles. Like for
+* the Gallium's HUD, we keep a list of busy queries in a ring in order
+* to prevent stalls when reading queries. */
+   length = (1 + (NV50_HW_PM_RING_BUFFER_NUM_DOMAINS * 6) *
+  NV50_HW_PM_RING_BUFFER_MAX_QUERIES) * 4;
+
+   ret = nouveau_object_new(chan, 0xbeef0302, NOUVEAU_NOTIFIER_CLASS,
+(struct nv04_notify){ .length = length },
+sizeof(struct nv04_notify), screen-query);
+   if (ret) {
+   NOUVEAU_ERR(Failed to allocate notifier object for PM: %d\n, ret);
+   goto fail;
+   }
+
ret = nouveau_object_new(chan, 0xbeef506e, 0x506e,
 NULL, 0, screen-sw);
if (ret) {
@@ -845,6 +866,14 @@ nv50_screen_create(struct nouveau_device *dev)
nouveau_heap_init(screen-gp_code_heap, 0, 1  NV50_CODE_BO_SIZE_LOG2);
nouveau_heap_init(screen-fp_code_heap, 0, 1  NV50_CODE_BO_SIZE_LOG2);
 
+   ret = nouveau_bo_wrap(screen-base.device, fifo-notify, 
screen-notify_bo);
+   if (ret == 0)
+  nouveau_bo_map(screen-notify_bo, 0, screen-base.client);
+   if (ret) {
+  NOUVEAU_ERR(Failed to map notifier object for PM: %d\n, ret);
+  goto fail;
+   }
+
nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, value);
 
screen-TPs = util_bitcount(value  0x);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index 69fdfdb..71a5247 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -59,6 +59,7 @@ struct nv50_screen {
struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
struct nouveau_bo *stack_bo;
struct nouveau_bo *tls_bo;
+   struct nouveau_bo *notify_bo;
 
unsigned TPs;
unsigned MPsInTP;
@@ -89,6 +90,7 @@ struct nv50_screen {
} fence;
 
struct nouveau_object *sync;
+   struct nouveau_object *query;
 
struct nouveau_object *tesla;
struct nouveau_object *eng2d;
@@ -96,6 +98,10 @@ struct nv50_screen {
struct nouveau_object *sw;
 };
 
+/* Parameters of the ring buffer used to read back global PM counters. */
+#define NV50_HW_PM_RING_BUFFER_NUM_DOMAINS 8
+#define NV50_HW_PM_RING_BUFFER_MAX_QUERIES 9 /* HUD_NUM_QUERIES + 1 */
+
 static INLINE struct nv50_screen *
 nv50_screen(struct pipe_screen *screen)
 {
-- 
2.4.4

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[Nouveau] [RFC PATCH 7/8] nv50: expose global performance counters to the HUD

2015-06-22 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv50/nv50_query.c  | 41 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c |  1 +
 src/gallium/drivers/nouveau/nv50/nv50_screen.h |  3 ++
 3 files changed, 45 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c 
b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index b9d2914..062d427 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -1535,6 +1535,47 @@ nv50_hw_pm_query_result(struct nv50_context *nv50, 
struct nv50_query *q,
return TRUE;
 }
 
+int
+nv50_screen_get_driver_query_info(struct pipe_screen *pscreen,
+  unsigned id,
+  struct pipe_driver_query_info *info)
+{
+   struct nv50_screen *screen = nv50_screen(pscreen);
+   int count = 0;
+
+   // TODO: Check DRM version when nvif will be merged in libdrm!
+   if (screen-base.perfmon) {
+  nv50_identify_events(screen);
+  count += NV50_HW_PM_QUERY_COUNT;
+   }
+
+   if (!info)
+  return count;
+
+   /* Init default values. */
+   info-name = this_is_not_the_query_you_are_looking_for;
+   info-query_type = 0xdeadd01d;
+   info-type = PIPE_DRIVER_QUERY_TYPE_UINT64;
+   info-max_value.u64 = 0;
+   info-group_id = -1;
+
+   if (id  count) {
+  if (screen-base.perfmon) {
+ const struct nv50_hw_pm_query_cfg *cfg =
+nv50_hw_pm_query_get_cfg(screen, NV50_HW_PM_QUERY(id));
+
+ info-name = cfg-event-name;
+ info-query_type = NV50_HW_PM_QUERY(id);
+ info-max_value.u64 =
+(cfg-event-display == NV50_HW_PM_EVENT_DISPLAY_RATIO) ? 100 : 0;
+ return 1;
+  }
+   }
+
+   /* User asked for info about non-existing query. */
+   return 0;
+}
+
 void
 nv50_init_query_functions(struct nv50_context *nv50)
 {
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 53817c0..f07798e 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -745,6 +745,7 @@ nv50_screen_create(struct nouveau_device *dev)
pscreen-get_param = nv50_screen_get_param;
pscreen-get_shader_param = nv50_screen_get_shader_param;
pscreen-get_paramf = nv50_screen_get_paramf;
+   pscreen-get_driver_query_info = nv50_screen_get_driver_query_info;
 
nv50_screen_init_resource_functions(pscreen);
 
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index 0449659..69127c0 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -143,6 +143,9 @@ nv50_screen(struct pipe_screen *screen)
 #define NV50_HW_PM_QUERY_TEX_CACHE_HIT  22
 #define NV50_HW_PM_QUERY_TEX_WAITS_FOR_FB   23
 
+int nv50_screen_get_driver_query_info(struct pipe_screen *, unsigned,
+  struct pipe_driver_query_info *);
+
 boolean nv50_blitter_create(struct nv50_screen *);
 void nv50_blitter_destroy(struct nv50_screen *);
 
-- 
2.4.4

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[Nouveau] [RFC PATCH 0/8] nv50: expose global performance counters

2015-06-22 Thread Samuel Pitoiset

Hello there,

This series exposes NVIDIA's global performance counters for Tesla through the
Gallium's HUD and the GL_AMD_performance_monitor extension.

This adds support for 24 hardware events which have been reverse engineered
with PerfKit (Windows) and CUPTI (Linux). These hardware events will allow
developers to profile OpenGL applications.

To reduce latency and to improve accuracy, these global performance counters
are tied to the command stream of the GPU using a set of software methods
instead of ioctls. Results are then written by the kernel to a mapped notifier
buffer object that allows the userspace to read back them.

However, the libdrm branch which implements the new nvif interface exposed by
Nouveau and the software methods interface are not upstream yet. I hope this
should done in the next days.

The code of this series can be found here:
http://cgit.freedesktop.org/~hakzsam/mesa/log/?h=nouveau_perfmon

The libdrm branch can be found here:
http://cgit.freedesktop.org/~hakzsam/drm/log/?h=nouveau_perfmon

The code of the software methods interface can be found here (two last commits):
http://cgit.freedesktop.org/~hakzsam/nouveau/log/?h=nouveau_perfmon

An other series which exposes global performance counters for Fermi and Kepler
will be submitted once I have got enough reviews for this one.

Feel free to make a review.

Thanks,
Samuel.

Samuel Pitoiset (8):
  nouveau: implement the nvif hardware performance counters interface
  nv50: allocate a software object class
  nv50: allocate and map a notifier buffer object for PM
  nv50: configure the ring buffer for reading back PM counters
  nv50: prevent NULL pointer dereference with pipe_query functions
  nv50: add support for compute/graphics global performance counters
  nv50: expose global performance counters to the HUD
  nv50: enable GL_AMD_performance_monitor

 src/gallium/drivers/nouveau/Makefile.sources   |2 +
 src/gallium/drivers/nouveau/nouveau_perfmon.c  |  302 +++
 src/gallium/drivers/nouveau/nouveau_perfmon.h  |   59 ++
 src/gallium/drivers/nouveau/nouveau_screen.c   |5 +
 src/gallium/drivers/nouveau/nouveau_screen.h   |1 +
 src/gallium/drivers/nouveau/nv50/nv50_query.c  | 1148 +++-
 src/gallium/drivers/nouveau/nv50/nv50_screen.c |   49 +
 src/gallium/drivers/nouveau/nv50/nv50_screen.h |   51 ++
 src/gallium/drivers/nouveau/nv50/nv50_winsys.h |1 +
 9 files changed, 1612 insertions(+), 6 deletions(-)
 create mode 100644 src/gallium/drivers/nouveau/nouveau_perfmon.c
 create mode 100644 src/gallium/drivers/nouveau/nouveau_perfmon.h

-- 
2.4.4

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[Nouveau] [RFC PATCH 8/8] nv50: enable GL_AMD_performance_monitor

2015-06-22 Thread Samuel Pitoiset

This exposes a group of global performance counters that enables
GL_AMD_performance_monitor. All piglit tests are okay.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv50/nv50_query.c  | 35 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c |  1 +
 src/gallium/drivers/nouveau/nv50/nv50_screen.h |  6 +
 3 files changed, 42 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c 
b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index 062d427..6638e82 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -1566,6 +1566,7 @@ nv50_screen_get_driver_query_info(struct pipe_screen 
*pscreen,
 
  info-name = cfg-event-name;
  info-query_type = NV50_HW_PM_QUERY(id);
+ info-group_id = NV50_HW_PM_QUERY_GROUP;
  info-max_value.u64 =
 (cfg-event-display == NV50_HW_PM_EVENT_DISPLAY_RATIO) ? 100 : 0;
  return 1;
@@ -1576,6 +1577,40 @@ nv50_screen_get_driver_query_info(struct pipe_screen 
*pscreen,
return 0;
 }
 
+int
+nv50_screen_get_driver_query_group_info(struct pipe_screen *pscreen,
+unsigned id,
+struct pipe_driver_query_group_info 
*info)
+{
+   struct nv50_screen *screen = nv50_screen(pscreen);
+   int count = 0;
+
+   // TODO: Check DRM version when nvif will be merged in libdrm!
+   if (screen-base.perfmon) {
+  count++; /* NV50_HW_PM_QUERY_GROUP */
+   }
+
+   if (!info)
+  return count;
+
+   if (id == NV50_HW_PM_QUERY_GROUP) {
+  if (screen-base.perfmon) {
+ info-name = Global performance counters;
+ info-type = PIPE_DRIVER_QUERY_GROUP_TYPE_GPU;
+ info-num_queries = NV50_HW_PM_QUERY_COUNT;
+ info-max_active_queries = 1; /* TODO: get rid of this limitation! */
+ return 1;
+  }
+   }
+
+   /* user asked for info about non-existing query group */
+   info-name = this_is_not_the_query_group_you_are_looking_for;
+   info-max_active_queries = 0;
+   info-num_queries = 0;
+   info-type = 0;
+   return 0;
+}
+
 void
 nv50_init_query_functions(struct nv50_context *nv50)
 {
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index f07798e..dfe20c9 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -746,6 +746,7 @@ nv50_screen_create(struct nouveau_device *dev)
pscreen-get_shader_param = nv50_screen_get_shader_param;
pscreen-get_paramf = nv50_screen_get_paramf;
pscreen-get_driver_query_info = nv50_screen_get_driver_query_info;
+   pscreen-get_driver_query_group_info = 
nv50_screen_get_driver_query_group_info;
 
nv50_screen_init_resource_functions(pscreen);
 
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index 69127c0..807ae0e 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -114,6 +114,9 @@ nv50_screen(struct pipe_screen *screen)
return (struct nv50_screen *)screen;
 }
 
+/* Hardware global performance counters groups. */
+#define NV50_HW_PM_QUERY_GROUP 0
+
 /* Hardware global performance counters. */
 #define NV50_HW_PM_QUERY_COUNT  24
 #define NV50_HW_PM_QUERY(i)(PIPE_QUERY_DRIVER_SPECIFIC + (i))
@@ -146,6 +149,9 @@ nv50_screen(struct pipe_screen *screen)
 int nv50_screen_get_driver_query_info(struct pipe_screen *, unsigned,
   struct pipe_driver_query_info *);
 
+int nv50_screen_get_driver_query_group_info(struct pipe_screen *, unsigned,
+struct 
pipe_driver_query_group_info *);
+
 boolean nv50_blitter_create(struct nv50_screen *);
 void nv50_blitter_destroy(struct nv50_screen *);
 
-- 
2.4.4

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[Nouveau] [RFC PATCH 5/8] nv50: prevent NULL pointer dereference with pipe_query functions

2015-06-22 Thread Samuel Pitoiset

This may happen when nv50_query_create() fails to create a new query.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv50/nv50_query.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c 
b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index 55fcac8..1162110 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -96,6 +96,9 @@ nv50_query_allocate(struct nv50_context *nv50, struct 
nv50_query *q, int size)
 static void
 nv50_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
 {
+   if (!pq)
+  return;
+
nv50_query_allocate(nv50_context(pipe), nv50_query(pq), 0);
nouveau_fence_ref(NULL, nv50_query(pq)-fence);
FREE(nv50_query(pq));
@@ -152,6 +155,9 @@ nv50_query_begin(struct pipe_context *pipe, struct 
pipe_query *pq)
struct nouveau_pushbuf *push = nv50-base.pushbuf;
struct nv50_query *q = nv50_query(pq);
 
+   if (!pq)
+  return FALSE;
+
/* For occlusion queries we have to change the storage, because a previous
 * query might set the initial render conition to FALSE even *after* we re-
 * initialized it to TRUE.
@@ -218,6 +224,9 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query 
*pq)
struct nouveau_pushbuf *push = nv50-base.pushbuf;
struct nv50_query *q = nv50_query(pq);
 
+   if (!pq)
+  return;
+
q-state = NV50_QUERY_STATE_ENDED;
 
switch (q-type) {
@@ -294,9 +303,12 @@ nv50_query_result(struct pipe_context *pipe, struct 
pipe_query *pq,
uint64_t *res64 = (uint64_t *)result;
uint32_t *res32 = (uint32_t *)result;
boolean *res8 = (boolean *)result;
-   uint64_t *data64 = (uint64_t *)q-data;
+   uint64_t *data64;
int i;
 
+   if (!pq)
+  return FALSE;
+
if (q-state != NV50_QUERY_STATE_READY)
   nv50_query_update(q);
 
@@ -314,6 +326,7 @@ nv50_query_result(struct pipe_context *pipe, struct 
pipe_query *pq,
}
q-state = NV50_QUERY_STATE_READY;
 
+   data64 = (uint64_t *)q-data;
switch (q-type) {
case PIPE_QUERY_GPU_FINISHED:
   res8[0] = TRUE;
-- 
2.4.4

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[Nouveau] [RFC PATCH 4/8] nv50: configure the ring buffer for reading back PM counters

2015-06-22 Thread Samuel Pitoiset

To write data at the right offset, the kernel has to know some
parameters of this ring buffer, like the number of domains and the
maximum number of queries.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 3a99cc8..53817c0 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -441,6 +441,13 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
 
BEGIN_NV04(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen-sw-handle);
+   BEGIN_NV04(push, SUBC_SW(0x0190), 1);
+   PUSH_DATA (push, screen-query-handle);
+   // XXX: Maybe add a check for DRM version here ?
+   BEGIN_NV04(push, SUBC_SW(0x0600), 1);
+   PUSH_DATA (push, NV50_HW_PM_RING_BUFFER_MAX_QUERIES);
+   BEGIN_NV04(push, SUBC_SW(0x0604), 1);
+   PUSH_DATA (push, NV50_HW_PM_RING_BUFFER_NUM_DOMAINS);
 
BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
-- 
2.4.4

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[Nouveau] [RFC PATCH 2/8] nv50: allocate a software object class

2015-06-22 Thread Samuel Pitoiset

This will allow to monitor global performance counters through the
command stream of the GPU instead of using ioctls.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 11 +++
 src/gallium/drivers/nouveau/nv50/nv50_screen.h |  1 +
 src/gallium/drivers/nouveau/nv50/nv50_winsys.h |  1 +
 3 files changed, 13 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 6583a35..c985344 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -367,6 +367,7 @@ nv50_screen_destroy(struct pipe_screen *pscreen)
nouveau_object_del(screen-eng2d);
nouveau_object_del(screen-m2mf);
nouveau_object_del(screen-sync);
+   nouveau_object_del(screen-sw);
 
nouveau_screen_fini(screen-base);
 
@@ -437,6 +438,9 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen-tesla-handle);
 
+   BEGIN_NV04(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
+   PUSH_DATA (push, screen-sw-handle);
+
BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 
@@ -768,6 +772,13 @@ nv50_screen_create(struct nouveau_device *dev)
   goto fail;
}
 
+   ret = nouveau_object_new(chan, 0xbeef506e, 0x506e,
+NULL, 0, screen-sw);
+   if (ret) {
+  NOUVEAU_ERR(Failed to allocate SW object: %d\n, ret);
+  goto fail;
+   }
+
ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 NULL, 0, screen-m2mf);
if (ret) {
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index 881051b..69fdfdb 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -93,6 +93,7 @@ struct nv50_screen {
struct nouveau_object *tesla;
struct nouveau_object *eng2d;
struct nouveau_object *m2mf;
+   struct nouveau_object *sw;
 };
 
 static INLINE struct nv50_screen *
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h 
b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h
index e8578c8..5cb33ef 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_winsys.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_winsys.h
@@ -60,6 +60,7 @@ PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo 
*bo, uint32_t flags)
 #define SUBC_COMPUTE(m) 6, (m)
 #define NV50_COMPUTE(n) SUBC_COMPUTE(NV50_COMPUTE_##n)
 
+#define SUBC_SW(m) 7, (m)
 
 static INLINE uint32_t
 NV50_FIFO_PKHDR(int subc, int mthd, unsigned size)
-- 
2.4.4

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Re: [Nouveau] [RFC PATCH 5/8] nv50: prevent NULL pointer dereference with pipe_query functions

2015-06-22 Thread Samuel Pitoiset




On 06/22/2015 10:52 PM, Ilia Mirkin wrote:

If query_create fails, why would any of these functions get called?


Because the HUD doesn't check if query_create() fails and it calls other 
pipe_query functions with NULL pointer instead of a valid query object.




On Mon, Jun 22, 2015 at 4:53 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:

This may happen when nv50_query_create() fails to create a new query.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
  src/gallium/drivers/nouveau/nv50/nv50_query.c | 15 ++-
  1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c 
b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index 55fcac8..1162110 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -96,6 +96,9 @@ nv50_query_allocate(struct nv50_context *nv50, struct 
nv50_query *q, int size)
  static void
  nv50_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
  {
+   if (!pq)
+  return;
+
 nv50_query_allocate(nv50_context(pipe), nv50_query(pq), 0);
 nouveau_fence_ref(NULL, nv50_query(pq)-fence);
 FREE(nv50_query(pq));
@@ -152,6 +155,9 @@ nv50_query_begin(struct pipe_context *pipe, struct 
pipe_query *pq)
 struct nouveau_pushbuf *push = nv50-base.pushbuf;
 struct nv50_query *q = nv50_query(pq);

+   if (!pq)
+  return FALSE;
+
 /* For occlusion queries we have to change the storage, because a previous
  * query might set the initial render conition to FALSE even *after* we re-
  * initialized it to TRUE.
@@ -218,6 +224,9 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query 
*pq)
 struct nouveau_pushbuf *push = nv50-base.pushbuf;
 struct nv50_query *q = nv50_query(pq);

+   if (!pq)
+  return;
+
 q-state = NV50_QUERY_STATE_ENDED;

 switch (q-type) {
@@ -294,9 +303,12 @@ nv50_query_result(struct pipe_context *pipe, struct 
pipe_query *pq,
 uint64_t *res64 = (uint64_t *)result;
 uint32_t *res32 = (uint32_t *)result;
 boolean *res8 = (boolean *)result;
-   uint64_t *data64 = (uint64_t *)q-data;
+   uint64_t *data64;
 int i;

+   if (!pq)
+  return FALSE;
+
 if (q-state != NV50_QUERY_STATE_READY)
nv50_query_update(q);

@@ -314,6 +326,7 @@ nv50_query_result(struct pipe_context *pipe, struct 
pipe_query *pq,
 }
 q-state = NV50_QUERY_STATE_READY;

+   data64 = (uint64_t *)q-data;
 switch (q-type) {
 case PIPE_QUERY_GPU_FINISHED:
res8[0] = TRUE;
--
2.4.4

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[Nouveau] [PATCH 2/2] pm/nv40: rename pcounter domains to 'pc' instead of 'pm'

2015-06-19 Thread Samuel Pitoiset

This trivial patch makes thing more consistent since hardware signals
names are prefixed by 'pcXX'.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/pm/nv40.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drm/nouveau/nvkm/engine/pm/nv40.c 
b/drm/nouveau/nvkm/engine/pm/nv40.c
index 1c6d1ca..5a87f3a 100644
--- a/drm/nouveau/nvkm/engine/pm/nv40.c
+++ b/drm/nouveau/nvkm/engine/pm/nv40.c
@@ -108,7 +108,7 @@ nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object 
*engine,
if (ret)
return ret;
 
-   ret = nvkm_perfdom_new(priv-base, pm, 0, 0, 0, 4, mclass-doms);
+   ret = nvkm_perfdom_new(priv-base, pc, 0, 0, 0, 4, mclass-doms);
if (ret)
return ret;
 
-- 
2.4.3

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[Nouveau] [PATCH 2/2] pm/gk104: add compute signals/sources

2015-06-19 Thread Samuel Pitoiset

These signals and sources have been reverse engineered from CUPTI
(Linux). Graphics signals exposed by PerfKit (Windows only) will be
added later. I need to reverse engineer them and it's a bit painful.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/pm/gf100.h |  1 +
 drm/nouveau/nvkm/engine/pm/gf117.c |  8 +++-
 drm/nouveau/nvkm/engine/pm/gk104.c | 85 ++
 3 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/drm/nouveau/nvkm/engine/pm/gf100.h 
b/drm/nouveau/nvkm/engine/pm/gf100.h
index 40ced89..d73f0ca 100644
--- a/drm/nouveau/nvkm/engine/pm/gf100.h
+++ b/drm/nouveau/nvkm/engine/pm/gf100.h
@@ -27,5 +27,6 @@ int gf100_pm_fini(struct nvkm_object *, bool);
 extern const struct nvkm_specdom gf100_pm_gpc[];
 
 extern const struct nvkm_specsrc gf100_pmfb_sources[];
+extern const struct nvkm_specsrc gf117_pbfb_sources[];
 
 #endif
diff --git a/drm/nouveau/nvkm/engine/pm/gf117.c 
b/drm/nouveau/nvkm/engine/pm/gf117.c
index 911ff3f..01d3a48 100644
--- a/drm/nouveau/nvkm/engine/pm/gf117.c
+++ b/drm/nouveau/nvkm/engine/pm/gf117.c
@@ -39,7 +39,7 @@ gf117_pmfb_sources[] = {
{}
 };
 
-static const struct nvkm_specsrc
+const struct nvkm_specsrc
 gf117_pbfb_sources[] = {
{ 0x110100, (const struct nvkm_specmux[]) {
{ 0x1, 0, unk0 },
@@ -47,6 +47,12 @@ gf117_pbfb_sources[] = {
{ 0x3, 8, unk8 },
{}
}, pbfb0_pm_unk100 },
+{ 0x10f100, (const struct nvkm_specmux[]) {
+   { 0x1, 0, unk0 },
+   { 0xf, 4, unk4 },
+   { 0x3, 8, unk8 },
+   {}
+   }, pbfb_broadcast_pm_unk100 },
{}
 };
 
diff --git a/drm/nouveau/nvkm/engine/pm/gk104.c 
b/drm/nouveau/nvkm/engine/pm/gk104.c
index 7462dff..5067f72 100644
--- a/drm/nouveau/nvkm/engine/pm/gk104.c
+++ b/drm/nouveau/nvkm/engine/pm/gk104.c
@@ -23,6 +23,52 @@
  */
 #include gf100.h
 
+static const struct nvkm_specsrc
+gk104_pmfb_sources[] = {
+   { 0x140028, (const struct nvkm_specmux[]) {
+   { 0x3fff, 0, unk0 },
+   { 0x7, 16, unk16 },
+   { 0x3, 24, unk24 },
+   { 0x2, 28, unk28 },
+   {}
+   }, pmfb0_pm_unk28 },
+   { 0x14125c, (const struct nvkm_specmux[]) {
+   { 0x3fff, 0, unk0 },
+   {}
+   }, pmfb0_subp0_pm_unk25c },
+   { 0x14165c, (const struct nvkm_specmux[]) {
+   { 0x3fff, 0, unk0 },
+   {}
+   }, pmfb0_subp1_pm_unk25c },
+   { 0x141a5c, (const struct nvkm_specmux[]) {
+   { 0x3fff, 0, unk0 },
+   {}
+   }, pmfb0_subp2_pm_unk25c },
+   { 0x141e5c, (const struct nvkm_specmux[]) {
+   { 0x3fff, 0, unk0 },
+   {}
+   }, pmfb0_subp3_pm_unk25c },
+   {}
+};
+
+static const struct nvkm_specsrc
+gk104_tex_sources[] = {
+   { 0x5042c0, (const struct nvkm_specmux[]) {
+   { 0xf, 0, sel0, true },
+   { 0x7, 8, sel1, true },
+   {}
+   }, pgraph_gpc0_tpc0_tex_pm_mux_c_d },
+   { 0x5042c8, (const struct nvkm_specmux[]) {
+   { 0x1f, 0, sel, true },
+   {}
+   }, pgraph_gpc0_tpc0_tex_pm_unkc8 },
+   { 0x5042b8, (const struct nvkm_specmux[]) {
+   { 0xff, 0, sel, true },
+   {}
+   }, pgraph_gpc0_tpc0_tex_pm_unkb8 },
+   {}
+};
+
 static const struct nvkm_specdom
 gk104_pm_hub[] = {
{ 0x60, (const struct nvkm_specsig[]) {
@@ -69,12 +115,51 @@ gk104_pm_gpc[] = {
{ 0xc7, gpc00_user_0 },
{}
}, gf100_perfctr_func },
+   { 0x20, (const struct nvkm_specsig[]) {
+   {}
+   }, gf100_perfctr_func },
+   { 0x20, (const struct nvkm_specsig[]) {
+   { 0x00, gpc02_tex_00, gk104_tex_sources },
+   { 0x01, gpc02_tex_01, gk104_tex_sources },
+   { 0x02, gpc02_tex_02, gk104_tex_sources },
+   { 0x03, gpc02_tex_03, gk104_tex_sources },
+   { 0x04, gpc02_tex_04, gk104_tex_sources },
+   { 0x05, gpc02_tex_05, gk104_tex_sources },
+   { 0x06, gpc02_tex_06, gk104_tex_sources },
+   { 0x07, gpc02_tex_07, gk104_tex_sources },
+   { 0x08, gpc02_tex_08, gk104_tex_sources },
+   { 0x0a, gpc02_tex_0a, gk104_tex_sources },
+   { 0x0b, gpc02_tex_0b, gk104_tex_sources },
+   { 0x0d, gpc02_tex_0c, gk104_tex_sources },
+   { 0x0c

[Nouveau] [PATCH 1/2] pm/gk104: re-use gf100_pm_ctor()

2015-06-19 Thread Samuel Pitoiset

gk104_pm_ctor() is equal to gf100_pm_ctor().

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvkm/engine/pm.h   |  2 +-
 drm/nouveau/nvkm/engine/device/gk104.c |  8 ++---
 drm/nouveau/nvkm/engine/pm/gk104.c | 60 +-
 3 files changed, 14 insertions(+), 56 deletions(-)

diff --git a/drm/nouveau/include/nvkm/engine/pm.h 
b/drm/nouveau/include/nvkm/engine/pm.h
index ed36daf..c4c704b 100644
--- a/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drm/nouveau/include/nvkm/engine/pm.h
@@ -29,6 +29,6 @@ extern struct nvkm_oclass *gt215_pm_oclass;
 extern struct nvkm_oclass *gf100_pm_oclass;
 extern struct nvkm_oclass *gf108_pm_oclass;
 extern struct nvkm_oclass *gf117_pm_oclass;
-extern struct nvkm_oclass gk104_pm_oclass;
+extern struct nvkm_oclass *gk104_pm_oclass;
 extern struct nvkm_oclass gk110_pm_oclass;
 #endif
diff --git a/drm/nouveau/nvkm/engine/device/gk104.c 
b/drm/nouveau/nvkm/engine/device/gk104.c
index 6a9483f..2b1fce2 100644
--- a/drm/nouveau/nvkm/engine/device/gk104.c
+++ b/drm/nouveau/nvkm/engine/device/gk104.c
@@ -91,7 +91,7 @@ gk104_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSVLD  ] = gk104_msvld_oclass;
device-oclass[NVDEV_ENGINE_MSPDEC ] = gk104_mspdec_oclass;
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device-cname = GK107;
@@ -125,7 +125,7 @@ gk104_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSVLD  ] = gk104_msvld_oclass;
device-oclass[NVDEV_ENGINE_MSPDEC ] = gk104_mspdec_oclass;
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device-cname = GK106;
@@ -159,7 +159,7 @@ gk104_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSVLD  ] = gk104_msvld_oclass;
device-oclass[NVDEV_ENGINE_MSPDEC ] = gk104_mspdec_oclass;
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xea:
device-cname = GK20A;
@@ -179,7 +179,7 @@ gk104_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_SW ] =  gf100_sw_oclass;
device-oclass[NVDEV_ENGINE_GR ] =  gk20a_gr_oclass;
device-oclass[NVDEV_ENGINE_CE2] = gk104_ce2_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
device-oclass[NVDEV_SUBDEV_VOLT   ] = gk20a_volt_oclass;
device-oclass[NVDEV_SUBDEV_PMU] =  gk20a_pmu_oclass;
break;
diff --git a/drm/nouveau/nvkm/engine/pm/gk104.c 
b/drm/nouveau/nvkm/engine/pm/gk104.c
index 3565f29..7462dff 100644
--- a/drm/nouveau/nvkm/engine/pm/gk104.c
+++ b/drm/nouveau/nvkm/engine/pm/gk104.c
@@ -85,58 +85,16 @@ gk104_pm_part[] = {
{}
 };
 
-static int
-gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
-{
-   struct gf100_pm_priv *priv;
-   u32 mask;
-   int ret;
-
-   ret = nvkm_pm_create(parent, engine, oclass, priv);
-   *pobject = nv_object(priv);
-   if (ret)
-   return ret;
-
-   /* HUB */
-   ret = nvkm_perfdom_new(priv-base, hub, 0, 0x1b, 0, 0x200,
-  gk104_pm_hub);
-   if (ret)
-   return ret;
-
-   /* GPC */
-   mask  = (1  nv_rd32(priv, 0x022430)) - 1;
-   mask = ~nv_rd32(priv, 0x022504);
-   mask = ~nv_rd32(priv, 0x022584);
-
-   ret = nvkm_perfdom_new(priv-base, gpc, mask, 0x18,
-  0x1000, 0x200, gk104_pm_gpc);
-   if (ret)
-   return ret;
-
-   /* PART */
-   mask  = (1  nv_rd32(priv, 0x022438)) - 1;
-   mask = ~nv_rd32(priv, 0x022548);
-   mask = ~nv_rd32(priv, 0x0225c8);
-
-   ret = nvkm_perfdom_new(priv-base, part, mask, 0x1a,
-  0x1000, 0x200, gk104_pm_part);
-   if (ret)
-   return ret;
-
-   nv_engine(priv)-cclass = nvkm_pm_cclass;
-   nv_engine(priv)-sclass =  nvkm_pm_sclass;
-   return 0;
-}
-
-struct nvkm_oclass
-gk104_pm_oclass = {
-   .handle = NV_ENGINE(PM, 0xe0),
-   .ofuncs = (struct nvkm_ofuncs) {
-   .ctor = gk104_pm_ctor,
+struct

Re: [Nouveau] [Mesa-dev] [RFC PATCH 5/8] nv50: prevent NULL pointer dereference with pipe_query functions

2015-06-23 Thread Samuel Pitoiset




On 06/23/2015 08:57 AM, Michel Dänzer wrote:

On 23.06.2015 06:02, Samuel Pitoiset wrote:


On 06/22/2015 10:52 PM, Ilia Mirkin wrote:

If query_create fails, why would any of these functions get called?

Because the HUD doesn't check if query_create() fails and it calls other
pipe_query functions with NULL pointer instead of a valid query object.

Could the HUD code be fixed instead?
It's definitely possible, and probably the best solution instead of 
preventing NULL pointer dereference in the underlying drivers. I'll make 
a patch.





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Re: [Nouveau] [PATCH] fix a wrong use of a logical operator in drmmode_output_dpms()

2015-06-10 Thread Samuel Pitoiset


Pushed.

On 05/27/2015 01:23 PM, Samuel Pitoiset wrote:



On 05/21/2015 06:40 AM, Dave Airlie wrote:
On 21 May 2015 at 03:26, Samuel Pitoiset samuel.pitoi...@gmail.com 
wrote:


On 05/20/2015 07:13 PM, Ilia Mirkin wrote:

This is obviously a bug, but one that has been there for some time.
Please figure out what this is guarding, and confirm that the feature
continues to work.


Sure, but do you have any ideas how to test this part of the DDX ?
It's the first time I play with it...


It's fine, the code just avoids going into the name checks if the type
isn't a enum,
it won't break anything actually fixing it.

The fix is

Reviewed-by: Dave Airlie airl...@redhat.com


Okay, thanks Dave.


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[Nouveau] [PATCH 1/2] pm: fix signals/sources for GT200+

2015-06-14 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---

This patch should be squashed with pm/nv50: add compute and graphics 
signals/sources.

 drm/nouveau/nvkm/engine/pm/gt200.c | 8 
 drm/nouveau/nvkm/engine/pm/gt215.c | 3 +--
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/gt200.c 
b/drm/nouveau/nvkm/engine/pm/gt200.c
index 220a027..e92f9c7 100644
--- a/drm/nouveau/nvkm/engine/pm/gt200.c
+++ b/drm/nouveau/nvkm/engine/pm/gt200.c
@@ -26,7 +26,7 @@
 const struct nvkm_specsrc
 gt200_crop_sources[] = {
{ 0x407008, (const struct nvkm_specmux[]) {
-   { 0x7, 0, sel0, true },
+   { 0xf, 0, sel0, true },
{ 0x1f, 16, sel1, true },
{}
}, pgraph_rop0_crop_pm_mux },
@@ -45,7 +45,7 @@ gt200_prop_sources[] = {
 const struct nvkm_specsrc
 gt200_tex_sources[] = {
{ 0x408508, (const struct nvkm_specmux[]) {
-   { 0x3fff, 0, unk0 },
+   { 0xf, 0, unk0 },
{}
}, pgraph_tpc0_tex_unk08 },
{}
@@ -94,7 +94,7 @@ gt200_pm[] = {
{ 0x5d, pc01_vfetch_17, g84_vfetch_sources },
{ 0x5e, pc01_vfetch_18, g84_vfetch_sources },
{ 0x5f, pc01_vfetch_19, g84_vfetch_sources },
- { 0x07, pc01_zcull_00, nv50_zcull_sources },
+   { 0x07, pc01_zcull_00, nv50_zcull_sources },
{ 0x08, pc01_zcull_01, nv50_zcull_sources },
{ 0x09, pc01_zcull_02, nv50_zcull_sources },
{ 0x0a, pc01_zcull_03, nv50_zcull_sources },
@@ -105,7 +105,7 @@ gt200_pm[] = {
{ 0xec, pc01_trailer },
{}
}, nv40_perfctr_func },
-   { 0xe0, (const struct nvkm_specsig[]) {
+   { 0xf0, (const struct nvkm_specsig[]) {
{ 0x55, pc02_crop_00, gt200_crop_sources },
{ 0x56, pc02_crop_01, gt200_crop_sources },
{ 0x57, pc02_crop_02, gt200_crop_sources },
diff --git a/drm/nouveau/nvkm/engine/pm/gt215.c 
b/drm/nouveau/nvkm/engine/pm/gt215.c
index b5542dc..f5eae63 100644
--- a/drm/nouveau/nvkm/engine/pm/gt215.c
+++ b/drm/nouveau/nvkm/engine/pm/gt215.c
@@ -23,10 +23,9 @@
  */
 #include nv40.h
 
-// TODO: check for GT200
 static const struct nvkm_specsrc
 gt215_zcull_sources[] = {
-   { 0x4002ca4, (const struct nvkm_specmux[]) {
+   { 0x402ca4, (const struct nvkm_specmux[]) {
{ 0x7fff, 0, unk0 },
{ 0xff, 24, unk24 },
{}
-- 
2.4.2

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Re: [Nouveau] [PATCH RFC 05/20] pm: reorganize the nvif interface

2015-06-14 Thread Samuel Pitoiset




On 06/14/2015 04:32 AM, Ben Skeggs wrote:

On 10 June 2015 at 07:53, Samuel Pitoiset samuel.pitoi...@gmail.com wrote:


On 06/09/2015 12:02 AM, Ben Skeggs wrote:

On 8 June 2015 at 06:40, Samuel Pitoiset samuel.pitoi...@gmail.com
wrote:

This commit introduces the NVIF_IOCTL_NEW_V0_PERFMON class which will be
used in order to query domains, signals and sources. This separates the
querying and the counting interface.

Hey Samuel,

I've merged patches 1-4 already, I've got some comments on this one,
but after they're solved I'm happy to merge up to (and including)
patch 18.  Patches 19/20, I need to think about some more.


Hey Ben,

Thanks for reviewing this series so quickly. :-)



Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
   bin/nv_perfmon.c  | 12 ++--
   drm/nouveau/include/nvif/class.h  | 26 --
   drm/nouveau/include/nvif/ioctl.h  |  5 +++--
   drm/nouveau/nvkm/engine/pm/base.c | 38
--
   4 files changed, 57 insertions(+), 24 deletions(-)

diff --git a/bin/nv_perfmon.c b/bin/nv_perfmon.c
index a8c5838..30a3138 100644
--- a/bin/nv_perfmon.c
+++ b/bin/nv_perfmon.c
@@ -600,7 +600,7 @@ main(int argc, char **argv)
  const char *cfg = NULL;
  const char *dbg = error;
  u64 dev = ~0ULL;
-   struct nvif_perfctr_query_v0 args = {};
+   struct nvif_perfmon_query_signal_v0 args = {};
  struct nvif_client *client;
  struct nvif_object object;
  int ret, c, k;
@@ -644,15 +644,14 @@ main(int argc, char **argv)
  }

  ret = nvif_object_init(nvif_object(device), NULL, 0xdeadbeef,
-  NVIF_IOCTL_NEW_V0_PERFCTR,
-  (struct nvif_perfctr_v0) {
-  }, sizeof(struct nvif_perfctr_v0),
object);
+  NVIF_IOCTL_NEW_V0_PERFMON, NULL, 0,
object);
  assert(ret == 0);
  do {
  u32 prev_iter = args.iter;

  args.name[0] = '\0';
-   ret = nvif_mthd(object, NVIF_PERFCTR_V0_QUERY, args,
sizeof(args));
+   ret = nvif_mthd(object, NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
  assert(ret == 0);

  if (prev_iter) {
@@ -663,7 +662,8 @@ main(int argc, char **argv)
  args.iter = prev_iter;
  strncpy(signals[nr_signals - 1], args.name,
  sizeof(args.name));
-   ret = nvif_mthd(object, NVIF_PERFCTR_V0_QUERY,
args, sizeof(args));
+   ret = nvif_mthd(object,
NVIF_PERFMON_V0_QUERY_SIGNAL,
+   args, sizeof(args));
  assert(ret == 0);
  }
  } while (args.iter != 0x);
diff --git a/drm/nouveau/include/nvif/class.h
b/drm/nouveau/include/nvif/class.h
index 64f8b2f..11935a0 100644
--- a/drm/nouveau/include/nvif/class.h
+++ b/drm/nouveau/include/nvif/class.h
@@ -251,6 +251,20 @@ struct gf110_dma_v0 {
* perfmon

**/

+#define NVIF_PERFMON_V0_QUERY_SIGNAL
0x00
+
+struct nvif_perfmon_query_signal_v0 {
+   __u8  version;
+   __u8  pad01[3];
+   __u32 iter;
+   char  name[64];
+};
+
+

+/***
+ * perfctr
+
**/
+
   struct nvif_perfctr_v0 {
  __u8  version;
  __u8  pad01[1];
@@ -259,16 +273,8 @@ struct nvif_perfctr_v0 {
  char  name[4][64];
   };

-#define NVIF_PERFCTR_V0_QUERY
0x00
-#define NVIF_PERFCTR_V0_SAMPLE
0x01
-#define NVIF_PERFCTR_V0_READ
0x02
-
-struct nvif_perfctr_query_v0 {
-   __u8  version;
-   __u8  pad01[3];
-   __u32 iter;
-   char  name[64];
-};
+#define NVIF_PERFCTR_V0_SAMPLE
0x00
+#define NVIF_PERFCTR_V0_READ
0x01

   struct nvif_perfctr_sample {
   };
diff --git a/drm/nouveau/include/nvif/ioctl.h
b/drm/nouveau/include/nvif/ioctl.h
index 4cd8e32..517cd27 100644
--- a/drm/nouveau/include/nvif/ioctl.h
+++ b/drm/nouveau/include/nvif/ioctl.h
@@ -49,8 +49,9 @@ struct nvif_ioctl_new_v0 {
  __u64 token;
  __u32 handle;
   /* these class numbers are made up by us, and not nvidia-assigned */
-#define NVIF_IOCTL_NEW_V0_PERFCTR
0x
-#define NVIF_IOCTL_NEW_V0_CONTROL
0xfffe
+#define NVIF_IOCTL_NEW_V0_PERFMON
0x
+#define NVIF_IOCTL_NEW_V0_PERFCTR
0xfffe
+#define NVIF_IOCTL_NEW_V0_CONTROL
0xfffd

It doesn't matter this time, because we're technically breaking ABI
already anyway and current userspace won't be effected, but best to
avoid changing class numbers like this :)  It's fine this time though.


Sure, since the nvif interface is still not exposed through libdrm, this is
not going to affect

[Nouveau] [PATCH 2/2] pm: some fixes related to sources

2015-06-14 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---

This patch should be squashed with pm: allow the userspace to configure 
sources.

 drm/nouveau/nvkm/engine/pm/base.c | 21 -
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index f505a11..7866e22 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -154,6 +154,8 @@ nvkm_perfsrc_enable(struct nvkm_pm *ppm, struct 
nvkm_perfctr *ctr)
 
/* enable the source */
nv_mask(ppm, src-addr, mask, value);
+   nv_debug(ppm, enabled source 0x%08x 0x%08x 0x%08x\n,
+src-addr, mask, value);
}
}
return 0;
@@ -165,6 +167,7 @@ nvkm_perfsrc_disable(struct nvkm_pm *ppm, struct 
nvkm_perfctr *ctr)
struct nvkm_perfdom *dom = NULL;
struct nvkm_perfsig *sig;
struct nvkm_perfsrc *src;
+   u32 mask;
int i, j;
 
for (i = 0; i  4  ctr-signal[i]; i++) {
@@ -178,8 +181,16 @@ nvkm_perfsrc_disable(struct nvkm_pm *ppm, struct 
nvkm_perfctr *ctr)
if (!src)
return -EINVAL;
 
+   /* unset enable bit if needed */
+   mask = 0x;
+   if (src-enable)
+   mask = 0x8000;
+   mask |= (src-mask  src-shift);
+
/* disable the source */
-   nv_mask(ppm, src-addr, src-mask  src-shift, 0);
+   nv_mask(ppm, src-addr, mask, 0);
+   nv_debug(ppm, disabled source 0x%08x 0x%08x\n,
+src-addr, mask);
}
}
return 0;
@@ -309,7 +320,7 @@ nvkm_perfdom_dtor(struct nvkm_object *object)
 }
 
 static int
-nvkm_perfctr_new(struct nvkm_perfdom *dom, int slot,
+nvkm_perfctr_new(struct nvkm_perfdom *dom, int slot, uint8_t domain,
 struct nvkm_perfsig *signal[4], uint64_t source[4][8],
 uint16_t logic_op, struct nvkm_perfctr **pctr)
 {
@@ -323,6 +334,7 @@ nvkm_perfctr_new(struct nvkm_perfdom *dom, int slot,
if (!ctr)
return -ENOMEM;
 
+   ctr-domain   = domain;
ctr-logic_op = logic_op;
ctr-slot = slot;
for (i = 0; i  4; i++) {
@@ -361,7 +373,7 @@ nvkm_perfdom_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
 
for (c = 0; c  ARRAY_SIZE(args-v0.ctr); c++) {
struct nvkm_perfsig *sig[4] = {};
-   u64 src[4][8];
+   u64 src[4][8] = {};
 
for (s = 0; s  ARRAY_SIZE(args-v0.ctr[c].signal); s++) {
sig[s] = nvkm_perfsig_find(ppm, args-v0.domain,
@@ -378,11 +390,10 @@ nvkm_perfdom_ctor(struct nvkm_object *parent, struct 
nvkm_object *engine,
}
}
 
-   ret = nvkm_perfctr_new(sdom, c, sig, src,
+   ret = nvkm_perfctr_new(sdom, c, args-v0.domain, sig, src,
   args-v0.ctr[c].logic_op, ctr[c]);
if (ret)
return ret;
-   ctr[c]-domain = args-v0.domain;
}
 
if (!sdom)
-- 
2.4.2

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[Nouveau] [PATCH 1/2] pm/gf100: allow to share GPC, HUB and PART domains

2015-06-14 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvkm/engine/pm.h   |  2 +-
 drm/nouveau/nvkm/engine/device/gf100.c | 18 +-
 drm/nouveau/nvkm/engine/pm/gf100.c | 22 +-
 drm/nouveau/nvkm/engine/pm/gf100.h | 11 +++
 4 files changed, 34 insertions(+), 19 deletions(-)

diff --git a/drm/nouveau/include/nvkm/engine/pm.h 
b/drm/nouveau/include/nvkm/engine/pm.h
index 82f1c7f..ce5d93e 100644
--- a/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drm/nouveau/include/nvkm/engine/pm.h
@@ -26,7 +26,7 @@ extern struct nvkm_oclass *nv50_pm_oclass;
 extern struct nvkm_oclass *g84_pm_oclass;
 extern struct nvkm_oclass *gt200_pm_oclass;
 extern struct nvkm_oclass *gt215_pm_oclass;
-extern struct nvkm_oclass gf100_pm_oclass;
+extern struct nvkm_oclass *gf100_pm_oclass;
 extern struct nvkm_oclass gk104_pm_oclass;
 extern struct nvkm_oclass gk110_pm_oclass;
 #endif
diff --git a/drm/nouveau/nvkm/engine/device/gf100.c 
b/drm/nouveau/nvkm/engine/device/gf100.c
index 82b38d7..84a6abb 100644
--- a/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drm/nouveau/nvkm/engine/device/gf100.c
@@ -90,7 +90,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_CE1] = gf100_ce1_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device-cname = GF104;
@@ -123,7 +123,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_CE1] = gf100_ce1_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device-cname = GF106;
@@ -155,7 +155,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device-cname = GF114;
@@ -188,7 +188,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_CE1] = gf100_ce1_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device-cname = GF116;
@@ -220,7 +220,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device-cname = GF108;
@@ -252,7 +252,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc8:
device-cname = GF110;
@@ -285,7 +285,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_CE1] = gf100_ce1_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device-cname = GF119;
@@ -317,7 +317,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gf110_disp_oclass;
-   device-oclass

[Nouveau] [PATCH 2/2] pm/gf100: add compute signals/sources

2015-06-14 Thread Samuel Pitoiset

These signals and sources have been reverse engineered from CUPTI
(Linux). Graphics signals exposed by PerfKit (Windows only) will be
added later. I need to reverse engineer them and it's a bit painful.

This commit also adds a new class for GF108 and GF117.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/include/nvkm/engine/pm.h   |  2 +
 drm/nouveau/nvkm/engine/device/gf100.c |  6 +--
 drm/nouveau/nvkm/engine/pm/Kbuild  |  2 +
 drm/nouveau/nvkm/engine/pm/gf100.c | 96 +-
 drm/nouveau/nvkm/engine/pm/gf100.h |  5 ++
 drm/nouveau/nvkm/engine/pm/gf108.c | 84 +
 drm/nouveau/nvkm/engine/pm/gf117.c | 92 
 7 files changed, 282 insertions(+), 5 deletions(-)
 create mode 100644 drm/nouveau/nvkm/engine/pm/gf108.c
 create mode 100644 drm/nouveau/nvkm/engine/pm/gf117.c

diff --git a/drm/nouveau/include/nvkm/engine/pm.h 
b/drm/nouveau/include/nvkm/engine/pm.h
index ce5d93e..ed36daf 100644
--- a/drm/nouveau/include/nvkm/engine/pm.h
+++ b/drm/nouveau/include/nvkm/engine/pm.h
@@ -27,6 +27,8 @@ extern struct nvkm_oclass *g84_pm_oclass;
 extern struct nvkm_oclass *gt200_pm_oclass;
 extern struct nvkm_oclass *gt215_pm_oclass;
 extern struct nvkm_oclass *gf100_pm_oclass;
+extern struct nvkm_oclass *gf108_pm_oclass;
+extern struct nvkm_oclass *gf117_pm_oclass;
 extern struct nvkm_oclass gk104_pm_oclass;
 extern struct nvkm_oclass gk110_pm_oclass;
 #endif
diff --git a/drm/nouveau/nvkm/engine/device/gf100.c 
b/drm/nouveau/nvkm/engine/device/gf100.c
index 84a6abb..65b151d 100644
--- a/drm/nouveau/nvkm/engine/device/gf100.c
+++ b/drm/nouveau/nvkm/engine/device/gf100.c
@@ -252,7 +252,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device-cname = GF110;
@@ -317,7 +317,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gf110_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
device-cname = GF117;
@@ -347,7 +347,7 @@ gf100_identify(struct nvkm_device *device)
device-oclass[NVDEV_ENGINE_MSPPP  ] = gf100_msppp_oclass;
device-oclass[NVDEV_ENGINE_CE0] = gf100_ce0_oclass;
device-oclass[NVDEV_ENGINE_DISP   ] =  gf110_disp_oclass;
-   device-oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
+   device-oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
default:
nv_fatal(device, unknown Fermi chipset\n);
diff --git a/drm/nouveau/nvkm/engine/pm/Kbuild 
b/drm/nouveau/nvkm/engine/pm/Kbuild
index cc01048..4fadf55 100644
--- a/drm/nouveau/nvkm/engine/pm/Kbuild
+++ b/drm/nouveau/nvkm/engine/pm/Kbuild
@@ -5,5 +5,7 @@ nvkm-y += nvkm/engine/pm/g84.o
 nvkm-y += nvkm/engine/pm/gt200.o
 nvkm-y += nvkm/engine/pm/gt215.o
 nvkm-y += nvkm/engine/pm/gf100.o
+nvkm-y += nvkm/engine/pm/gf108.o
+nvkm-y += nvkm/engine/pm/gf117.o
 nvkm-y += nvkm/engine/pm/gk104.o
 nvkm-y += nvkm/engine/pm/gk110.o
diff --git a/drm/nouveau/nvkm/engine/pm/gf100.c 
b/drm/nouveau/nvkm/engine/pm/gf100.c
index 64db47e..b40c218 100644
--- a/drm/nouveau/nvkm/engine/pm/gf100.c
+++ b/drm/nouveau/nvkm/engine/pm/gf100.c
@@ -23,18 +23,110 @@
  */
 #include gf100.h
 
+const struct nvkm_specsrc
+gf100_pmfb_sources[] = {
+   { 0x140028, (const struct nvkm_specmux[]) {
+   { 0x3fff, 0, unk0 },
+   { 0x7, 16, unk16 },
+   { 0x3, 24, unk24 },
+   { 0x2, 29, unk29 },
+   {}
+   }, pmfb0_pm_unk28 },
+   {}
+};
+
+static const struct nvkm_specsrc
+gf100_l1_sources[] = {
+   { 0x5044a8, (const struct nvkm_specmux[]) {
+   { 0x3f, 0, sel, true },
+   {}
+   }, pgraph_gpc0_tpc0_l1_pm_mux },
+   {}
+};
+
+static const struct nvkm_specsrc
+gf100_pbfb_sources[] = {
+   { 0x10f100, (const struct nvkm_specmux[]) {
+   { 0x1, 0, unk0 },
+   { 0xf, 4, unk4 },
+   { 0x3, 8, unk8 },
+   {}
+   }, pbfb_broadcast_pm_unk100 },
+   {}
+};
+
+static const struct nvkm_specsrc
+gf100_tex_sources[] = {
+   { 0x5042c0, (const

Re: [Nouveau] [PATCH] fix a wrong use of a logical operator in drmmode_output_dpms()

2015-05-27 Thread Samuel Pitoiset




On 05/21/2015 06:40 AM, Dave Airlie wrote:

On 21 May 2015 at 03:26, Samuel Pitoiset samuel.pitoi...@gmail.com wrote:


On 05/20/2015 07:13 PM, Ilia Mirkin wrote:

This is obviously a bug, but one that has been there for some time.
Please figure out what this is guarding, and confirm that the feature
continues to work.


Sure, but do you have any ideas how to test this part of the DDX ?
It's the first time I play with it...


It's fine, the code just avoids going into the name checks if the type
isn't a enum,
it won't break anything actually fixing it.

The fix is

Reviewed-by: Dave Airlie airl...@redhat.com


Okay, thanks Dave.
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Re: [Nouveau] [RFC PATCH 3/8] nv50: allocate and map a notifier buffer object for PM

2015-06-28 Thread Samuel Pitoiset




On 06/26/2015 01:02 AM, Ilia Mirkin wrote:

On Mon, Jun 22, 2015 at 4:53 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:

This notifier buffer object will be used to read back global performance
counters results written by the kernel.

For each domain, we will store the handle of the perfdom object, an
array of 4 counters and the number of cycles. Like the Gallium's HUD,
we keep a list of busy queries in a ring in order to prevent stalls
when reading queries.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
  src/gallium/drivers/nouveau/nv50/nv50_screen.c | 29 ++
  src/gallium/drivers/nouveau/nv50/nv50_screen.h |  6 ++
  2 files changed, 35 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index c985344..3a99cc8 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -368,6 +368,7 @@ nv50_screen_destroy(struct pipe_screen *pscreen)
 nouveau_object_del(screen-m2mf);
 nouveau_object_del(screen-sync);
 nouveau_object_del(screen-sw);
+   nouveau_object_del(screen-query);

 nouveau_screen_fini(screen-base);

@@ -699,9 +700,11 @@ nv50_screen_create(struct nouveau_device *dev)
 struct nv50_screen *screen;
 struct pipe_screen *pscreen;
 struct nouveau_object *chan;
+   struct nv04_fifo *fifo;
 uint64_t value;
 uint32_t tesla_class;
 unsigned stack_size;
+   uint32_t length;
 int ret;

 screen = CALLOC_STRUCT(nv50_screen);
@@ -727,6 +730,7 @@ nv50_screen_create(struct nouveau_device *dev)
 screen-base.pushbuf-rsvd_kick = 5;

 chan = screen-base.channel;
+   fifo = chan-data;

 pscreen-destroy = nv50_screen_destroy;
 pscreen-context_create = nv50_create;
@@ -772,6 +776,23 @@ nv50_screen_create(struct nouveau_device *dev)
goto fail;
 }

+   /* Compute size (in bytes) of the notifier buffer object which is used
+* in order to read back global performance counters results written
+* by the kernel. For each domain, we store the handle of the perfdom
+* object, an array of 4 counters and the number of cycles. Like for
+* the Gallium's HUD, we keep a list of busy queries in a ring in order
+* to prevent stalls when reading queries. */
+   length = (1 + (NV50_HW_PM_RING_BUFFER_NUM_DOMAINS * 6) *
+  NV50_HW_PM_RING_BUFFER_MAX_QUERIES) * 4;

This calculation may become apparent to me later, but it certainly
isn't now. What's the *6? You refer to an array of 4 counters...
should that have been 6 counters? Or should this have been a 4?


This refers to the handle of the object, the array of 4 counters and the 
number of cycles.

In other words, for each domain we store: id, ctr0, ctr1, ctr2, ctr3, clk.




+
+   ret = nouveau_object_new(chan, 0xbeef0302, NOUVEAU_NOTIFIER_CLASS,
+(struct nv04_notify){ .length = length },
+sizeof(struct nv04_notify), screen-query);
+   if (ret) {
+   NOUVEAU_ERR(Failed to allocate notifier object for PM: %d\n, ret);
+   goto fail;
+   }
+
 ret = nouveau_object_new(chan, 0xbeef506e, 0x506e,
  NULL, 0, screen-sw);
 if (ret) {
@@ -845,6 +866,14 @@ nv50_screen_create(struct nouveau_device *dev)
 nouveau_heap_init(screen-gp_code_heap, 0, 1  NV50_CODE_BO_SIZE_LOG2);
 nouveau_heap_init(screen-fp_code_heap, 0, 1  NV50_CODE_BO_SIZE_LOG2);

+   ret = nouveau_bo_wrap(screen-base.device, fifo-notify, 
screen-notify_bo);
+   if (ret == 0)
+  nouveau_bo_map(screen-notify_bo, 0, screen-base.client);

ret = ...


Good catch, thanks.




+   if (ret) {
+  NOUVEAU_ERR(Failed to map notifier object for PM: %d\n, ret);
+  goto fail;
+   }
+
 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, value);

 screen-TPs = util_bitcount(value  0x);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index 69fdfdb..71a5247 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -59,6 +59,7 @@ struct nv50_screen {
 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
 struct nouveau_bo *stack_bo;
 struct nouveau_bo *tls_bo;
+   struct nouveau_bo *notify_bo;

 unsigned TPs;
 unsigned MPsInTP;
@@ -89,6 +90,7 @@ struct nv50_screen {
 } fence;

 struct nouveau_object *sync;
+   struct nouveau_object *query;

 struct nouveau_object *tesla;
 struct nouveau_object *eng2d;
@@ -96,6 +98,10 @@ struct nv50_screen {
 struct nouveau_object *sw;
  };

+/* Parameters of the ring buffer used to read back global PM counters. */
+#define NV50_HW_PM_RING_BUFFER_NUM_DOMAINS 8
+#define NV50_HW_PM_RING_BUFFER_MAX_QUERIES 9 /* HUD_NUM_QUERIES + 1 */
+
  static INLINE struct nv50_screen *
  nv50_screen(struct pipe_screen *screen)
  {
--
2.4.4

Re: [Nouveau] [RFC PATCH 6/8] nv50: add support for compute/graphics global performance counters

2015-06-28 Thread Samuel Pitoiset




On 06/26/2015 01:09 AM, Ilia Mirkin wrote:

What's with the \%'s everywhere?


Maybe percent will be better ?



On Mon, Jun 22, 2015 at 4:53 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:

This commit adds support for both compute and graphics global
performance counters which have been reverse engineered with
CUPTI (Linux) and PerfKit (Windows).

Currently, only one query type can be monitored at the same time because
the Gallium's HUD doesn't fit pretty well. This will be improved later.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
  src/gallium/drivers/nouveau/nv50/nv50_query.c  | 1057 +++-
  src/gallium/drivers/nouveau/nv50/nv50_screen.h |   35 +
  2 files changed, 1087 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_query.c 
b/src/gallium/drivers/nouveau/nv50/nv50_query.c
index 1162110..b9d2914 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_query.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_query.c
@@ -27,6 +27,8 @@
  #include nv50/nv50_context.h
  #include nv_object.xml.h

+#include nouveau_perfmon.h
+
  #define NV50_QUERY_STATE_READY   0
  #define NV50_QUERY_STATE_ACTIVE  1
  #define NV50_QUERY_STATE_ENDED   2
@@ -51,10 +53,25 @@ struct nv50_query {
 boolean is64bit;
 struct nouveau_mm_allocation *mm;
 struct nouveau_fence *fence;
+   struct nouveau_object *perfdom;
  };

  #define NV50_QUERY_ALLOC_SPACE 256

+#ifdef DEBUG
+static void nv50_hw_pm_dump_perfdom(struct nvif_perfdom_v0 *args);
+#endif
+
+static boolean
+nv50_hw_pm_query_create(struct nv50_context *, struct nv50_query *);
+static void
+nv50_hw_pm_query_destroy(struct nv50_context *, struct nv50_query *);
+static boolean
+nv50_hw_pm_query_begin(struct nv50_context *, struct nv50_query *);
+static void nv50_hw_pm_query_end(struct nv50_context *, struct nv50_query *);
+static boolean nv50_hw_pm_query_result(struct nv50_context *,
+struct nv50_query *, boolean, void *);
+
  static INLINE struct nv50_query *
  nv50_query(struct pipe_query *pipe)
  {
@@ -96,12 +113,18 @@ nv50_query_allocate(struct nv50_context *nv50, struct 
nv50_query *q, int size)
  static void
  nv50_query_destroy(struct pipe_context *pipe, struct pipe_query *pq)
  {
+   struct nv50_context *nv50 = nv50_context(pipe);
+   struct nv50_query *q = nv50_query(pq);
+
 if (!pq)
return;

-   nv50_query_allocate(nv50_context(pipe), nv50_query(pq), 0);
-   nouveau_fence_ref(NULL, nv50_query(pq)-fence);
-   FREE(nv50_query(pq));
+   if ((q-type = NV50_HW_PM_QUERY(0)  q-type = NV50_HW_PM_QUERY_LAST))
+  nv50_hw_pm_query_destroy(nv50, q);
+
+   nv50_query_allocate(nv50, q, 0);
+   nouveau_fence_ref(NULL, q-fence);
+   FREE(q);
  }

  static struct pipe_query *
@@ -130,6 +153,11 @@ nv50_query_create(struct pipe_context *pipe, unsigned 
type, unsigned index)
q-data -= 32 / sizeof(*q-data); /* we advance before query_begin ! */
 }

+   if ((q-type = NV50_HW_PM_QUERY(0)  q-type = NV50_HW_PM_QUERY_LAST)) {
+  if (!nv50_hw_pm_query_create(nv50, q))
+ return NULL;
+   }
+
 return (struct pipe_query *)q;
  }

@@ -154,6 +182,7 @@ nv50_query_begin(struct pipe_context *pipe, struct 
pipe_query *pq)
 struct nv50_context *nv50 = nv50_context(pipe);
 struct nouveau_pushbuf *push = nv50-base.pushbuf;
 struct nv50_query *q = nv50_query(pq);
+   boolean ret = TRUE;

 if (!pq)
return FALSE;
@@ -211,10 +240,13 @@ nv50_query_begin(struct pipe_context *pipe, struct 
pipe_query *pq)
nv50_query_get(push, q, 0x10, 0x5002);
break;
 default:
+  if ((q-type = NV50_HW_PM_QUERY(0)  q-type = 
NV50_HW_PM_QUERY_LAST)) {
+ ret = nv50_hw_pm_query_begin(nv50, q);
+  }
break;
 }
 q-state = NV50_QUERY_STATE_ACTIVE;
-   return true;
+   return ret;
  }

  static void
@@ -274,7 +306,9 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query 
*pq)
q-state = NV50_QUERY_STATE_READY;
break;
 default:
-  assert(0);
+  if ((q-type = NV50_HW_PM_QUERY(0)  q-type = 
NV50_HW_PM_QUERY_LAST)) {
+ nv50_hw_pm_query_end(nv50, q);
+  }
break;
 }

@@ -309,6 +343,10 @@ nv50_query_result(struct pipe_context *pipe, struct 
pipe_query *pq,
 if (!pq)
return FALSE;

+   if ((q-type = NV50_HW_PM_QUERY(0)  q-type = NV50_HW_PM_QUERY_LAST)) {
+  return nv50_hw_pm_query_result(nv50, q, wait, result);
+   }
+
 if (q-state != NV50_QUERY_STATE_READY)
nv50_query_update(q);

@@ -488,6 +526,1015 @@ nva0_so_target_save_offset(struct pipe_context *pipe,
 nv50_query_end(pipe, targ-pq);
  }

+/* === HARDWARE GLOBAL PERFORMANCE COUNTERS for NV50 === */
+
+struct nv50_hw_pm_source_cfg
+{
+   const char *name;
+   uint64_t value;
+};
+
+struct nv50_hw_pm_signal_cfg
+{
+   const char *name;
+   const struct nv50_hw_pm_source_cfg src[8];
+};
+
+struct nv50_hw_pm_counter_cfg
+{
+   uint16_t logic_op;
+   const struct

Re: [Nouveau] [RFC PATCH 4/8] nv50: configure the ring buffer for reading back PM counters

2015-06-28 Thread Samuel Pitoiset




On 06/26/2015 01:04 AM, Ilia Mirkin wrote:

Yeah, this whole thing has to be guarded by a drm version check,
otherwise it'll end up with errors in dmesg I assume. Perhaps only
allocate screen-query when the drm version matches, and gate things
on that for the rest of the code?


Yes, this sounds good to me.



On Mon, Jun 22, 2015 at 4:53 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:

To write data at the right offset, the kernel has to know some
parameters of this ring buffer, like the number of domains and the
maximum number of queries.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
  src/gallium/drivers/nouveau/nv50/nv50_screen.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 3a99cc8..53817c0 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -441,6 +441,13 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)

 BEGIN_NV04(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 PUSH_DATA (push, screen-sw-handle);
+   BEGIN_NV04(push, SUBC_SW(0x0190), 1);
+   PUSH_DATA (push, screen-query-handle);
+   // XXX: Maybe add a check for DRM version here ?
+   BEGIN_NV04(push, SUBC_SW(0x0600), 1);
+   PUSH_DATA (push, NV50_HW_PM_RING_BUFFER_MAX_QUERIES);
+   BEGIN_NV04(push, SUBC_SW(0x0604), 1);
+   PUSH_DATA (push, NV50_HW_PM_RING_BUFFER_NUM_DOMAINS);

FYI you can do BEGIN_NV04(..., 2), since they're sequential.


I'm going to make the change.




 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
--
2.4.4

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Re: [Nouveau] [Mesa-dev] [PATCH 2/2] nv30: fix clip plane uploads and enable changes

2015-05-24 Thread Samuel Pitoiset




On 05/24/2015 06:58 AM, Ilia Mirkin wrote:

nv30_validate_clip depends on the rasterizer state. Also we should
upload all the new clip planes on change since next time the plane data
won't have changed, but the enables might.

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
  src/gallium/drivers/nouveau/nv30/nv30_state_validate.c | 16 +++-
  1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c 
b/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c
index 86ac4f7..a954dcc 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_state_validate.c
@@ -272,15 +272,13 @@ nv30_validate_clip(struct nv30_context *nv30)
 uint32_t clpd_enable = 0;
  
 for (i = 0; i  6; i++) {

-  if (nv30-rast-pipe.clip_plane_enable  (1  i)) {
- if (nv30-dirty  NV30_NEW_CLIP) {
-BEGIN_NV04(push, NV30_3D(VP_UPLOAD_CONST_ID), 5);
-PUSH_DATA (push, i);
-PUSH_DATAp(push, nv30-clip.ucp[i], 4);
- }
-
- clpd_enable |= 1  (1 + 4*i);
+  if (nv30-dirty  NV30_NEW_CLIP) {
+ BEGIN_NV04(push, NV30_3D(VP_UPLOAD_CONST_ID), 5);
+ PUSH_DATA (push, i);
+ PUSH_DATAp(push, nv30-clip.ucp[i], 4);
}
+  if (nv30-rast-pipe.clip_plane_enable  (1  i))
+ clpd_enable |= 2  (4*i);


Can you explain why did you change this line?


 }
  
 BEGIN_NV04(push, NV30_3D(VP_CLIP_PLANES_ENABLE), 1);

@@ -389,7 +387,7 @@ static struct state_validate hwtnl_validate_list[] = {
  { nv30_validate_stipple,   NV30_NEW_STIPPLE },
  { nv30_validate_scissor,   NV30_NEW_SCISSOR | NV30_NEW_RASTERIZER },
  { nv30_validate_viewport,  NV30_NEW_VIEWPORT },
-{ nv30_validate_clip,  NV30_NEW_CLIP },
+{ nv30_validate_clip,  NV30_NEW_CLIP | NV30_NEW_RASTERIZER },
  { nv30_fragprog_validate,  NV30_NEW_FRAGPROG | NV30_NEW_FRAGCONST },
  { nv30_vertprog_validate,  NV30_NEW_VERTPROG | NV30_NEW_VERTCONST |
 NV30_NEW_FRAGPROG | NV30_NEW_RASTERIZER },


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Re: [Nouveau] [PATCH 4/8] acpi: Allow evaluate_optimus_dsm to take NULL results

2015-05-26 Thread Samuel Pitoiset




On 05/26/2015 12:22 AM, Pierre Moreau wrote:

Signed-off-by: Pierre Moreau pierre.mor...@free.fr
---
  drm/nouveau/nouveau_acpi.c | 10 --
  1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drm/nouveau/nouveau_acpi.c b/drm/nouveau/nouveau_acpi.c
index 36f4a40..073f7d7 100644
--- a/drm/nouveau/nouveau_acpi.c
+++ b/drm/nouveau/nouveau_acpi.c
@@ -88,15 +88,14 @@ static int nouveau_evaluate_optimus_dsm(acpi_handle handle, 
int func, int arg, u
for (i = 0; i  4; i++)
args_buff[i] = (arg  i * 8)  0xFF;
  
-	*result = 0;

obj = acpi_evaluate_dsm_typed(handle, nouveau_op_dsm_muid, 
nouveau_op_dsm_rid,
  func, argv4, ACPI_TYPE_BUFFER);
if (!obj) {
acpi_handle_info(handle, failed to evaluate _DSM\n);
return AE_ERROR;
} else {
-   if (obj-buffer.length == 4) {
-   *result |= obj-buffer.pointer[0];
+   if (!result  obj-buffer.length == 4) {
+   *result  = obj-buffer.pointer[0];


segfault here if result is NULL! ;)


*result |= (obj-buffer.pointer[1]  8);
*result |= (obj-buffer.pointer[2]  16);
*result |= (obj-buffer.pointer[3]  24);
@@ -322,18 +321,17 @@ void nouveau_register_dsm_handler(void)
  /* Must be called for Optimus models before the card can be turned off */
  void nouveau_switcheroo_optimus_dsm(void)
  {
-   u32 result = 0;
if (!nouveau_dsm_priv.optimus_detected)
return;
  
  	nouveau_evaluate_optimus_dsm(nouveau_dsm_priv.dhandle,

 NOUVEAU_DSM_OPTIMUS_FLAGS,
-0x3, result);
+0x3, NULL);
  
  	nouveau_evaluate_optimus_dsm(nouveau_dsm_priv.dhandle,

 NOUVEAU_DSM_OPTIMUS_CAPS,
 NOUVEAU_DSM_OPTIMUS_SET_POWERDOWN,
-result);
+NULL);
  
  }
  


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Re: [Nouveau] [PATCH 5/8] acpi: Check returned object type by Optimus _DSM locally

2015-05-26 Thread Samuel Pitoiset




On 05/26/2015 12:22 AM, Pierre Moreau wrote:

Most _DSM will return an integer value of 0x8002 when given an unknown
UUID, revision ID or function ID. Checking locally allows us to differentiate
that case from other ACPI errors, and to not report a failed to evaluate _DSM
if 0x8002 is returned which was confusing.

Signed-off-by: Pierre Moreau pierre.mor...@free.fr
---
  drm/nouveau/nouveau_acpi.c | 15 ---
  1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drm/nouveau/nouveau_acpi.c b/drm/nouveau/nouveau_acpi.c
index 073f7d7..7aeaf7d 100644
--- a/drm/nouveau/nouveau_acpi.c
+++ b/drm/nouveau/nouveau_acpi.c
@@ -88,12 +88,12 @@ static int nouveau_evaluate_optimus_dsm(acpi_handle handle, 
int func, int arg, u
for (i = 0; i  4; i++)
args_buff[i] = (arg  i * 8)  0xFF;
  
-	obj = acpi_evaluate_dsm_typed(handle, nouveau_op_dsm_muid, nouveau_op_dsm_rid,

- func, argv4, ACPI_TYPE_BUFFER);
+   obj = acpi_evaluate_dsm(handle, nouveau_op_dsm_muid, nouveau_op_dsm_rid,
+   func, argv4);
if (!obj) {
acpi_handle_info(handle, failed to evaluate _DSM\n);
return AE_ERROR;
-   } else {
+   } else if (obj-type == ACPI_TYPE_BUFFER) {
if (!result  obj-buffer.length == 4) {
*result  = obj-buffer.pointer[0];
*result |= (obj-buffer.pointer[1]  8);
@@ -101,6 +101,15 @@ static int nouveau_evaluate_optimus_dsm(acpi_handle 
handle, int func, int arg, u
*result |= (obj-buffer.pointer[3]  24);
}
ACPI_FREE(obj);
+   } else if (obj-type == ACPI_TYPE_INTEGER 
+  obj-integer.value == 0x8002) {
+   acpi_handle_debug(handle, failed to query Optimus _DSM\n);
+   ACPI_FREE(obj);
+   return -ENODEV;
+   } else {
+   acpi_handle_err(handle, unexpected returned value by Optimus 
_DSM\n);
+   ACPI_FREE(obj);
+   return AE_ERROR;
}
  
  	return 0;


How do you handle the case where result is NULL and the type is 
ACPI_TYPE_BUFFER ?

Because you don't return any error. Is that expected?
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Re: [Nouveau] [PATCH 7/8] acpi: Add support for Apple Gmux _DMS

2015-05-26 Thread Samuel Pitoiset




On 05/26/2015 12:22 AM, Pierre Moreau wrote:

Signed-off-by: Pierre Moreau pierre.mor...@free.fr
---
  drm/nouveau/nouveau_acpi.c | 53 --
  drm/nouveau/nouveau_acpi.h |  2 ++
  drm/nouveau/nouveau_drm.c  |  6 --
  drm/nouveau/nouveau_vga.c  | 10 +
  4 files changed, 63 insertions(+), 8 deletions(-)

diff --git a/drm/nouveau/nouveau_acpi.c b/drm/nouveau/nouveau_acpi.c
index 104d291..3d6a1ea 100644
--- a/drm/nouveau/nouveau_acpi.c
+++ b/drm/nouveau/nouveau_acpi.c
@@ -29,6 +29,10 @@
  
  #define NOUVEAU_DSM_OPTIMUS_SET_POWERDOWN (NOUVEAU_DSM_OPTIMUS_POWERDOWN_PS3 | NOUVEAU_DSM_OPTIMUS_FLAGS_CHANGED)
  
+#define NOUVEAU_DSM_GMUX_V1_CAPS (3  6)

+
+#define NOUVEAU_DSM_GMUX_V2_CAPS (1  1)
+
  /* result of the optimus caps function */
  #define OPTIMUS_ENABLED (1  0)
  #define OPTIMUS_STATUS_MASK (3  3)
@@ -45,6 +49,7 @@
  static struct nouveau_dsm_priv {
bool mux_detected;
bool optimus_detected;
+   bool gmux_detected;
acpi_handle dhandle;
acpi_handle rom_handle;
  } nouveau_dsm_priv;
@@ -57,8 +62,13 @@ bool nouveau_has_mux(void) {
return nouveau_dsm_priv.mux_detected;
  }
  
+bool nouveau_has_gmux(void) {

+   return nouveau_dsm_priv.gmux_detected;
+}
+
  #define NOUVEAU_DSM_HAS_MUX 0x1
  #define NOUVEAU_DSM_HAS_OPT 0x2
+#define NOUVEAU_DSM_HAS_GMUX 0x4
  
  #ifdef CONFIG_VGA_SWITCHEROO

  static const uint32_t nouveau_mux_dsm_rid = 0x0102;
@@ -73,6 +83,18 @@ static const char nouveau_op_dsm_muid[] = {
0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0,
  };
  
+static const uint32_t nouveau_gmux_v1_dsm_rid = 0x101;

+static const char nouveau_gmux_v1_dsm_muid[] = {
+   0xA6, 0x69, 0x86, 0x99, 0xE9, 0x8B, 0xFB, 0x49,
+   0xBD, 0xDB, 0x51, 0xA1, 0xEF, 0xE1, 0x9C, 0x3D,
+};
+
+static const uint32_t nouveau_gmux_v2_dsm_rid = 0x001;
+static const char nouveau_gmux_v2_dsm_muid[] = {
+   0xC6, 0xB7, 0xB5, 0xA0, 0x18, 0x13, 0x1C, 0x44,
+   0xB0, 0xC9, 0xFE, 0x69, 0x5E, 0xAF, 0x94, 0x9B,
+};
+
  static int nouveau_evaluate_optimus_dsm(acpi_handle handle, int func, int 
arg, uint32_t *result)
  {
int i;
@@ -161,6 +183,17 @@ static int nouveau_evaluate_mux_dsm(acpi_handle handle, 
int func, int arg)
return ret;
  }
  
+static int nouveau_check_gmux_dsm(acpi_handle handle)

+{
+   bool has_v1 = acpi_check_dsm(handle, nouveau_gmux_v1_dsm_muid,
+nouveau_gmux_v1_dsm_rid,
+NOUVEAU_DSM_GMUX_V1_CAPS);
+   bool has_v2 = acpi_check_dsm(handle, nouveau_gmux_v2_dsm_muid,
+nouveau_gmux_v2_dsm_rid,
+NOUVEAU_DSM_GMUX_V2_CAPS);
+   return has_v1 || has_v2;
+}
+
  static int nouveau_dsm_switch_mux(acpi_handle handle, int mux_id)
  {
mxm_wmi_call_mxmx(mux_id == NOUVEAU_DSM_MUX_LED_STAMINA ? 
MXM_MXDS_ADAPTER_IGD : MXM_MXDS_ADAPTER_0);
@@ -238,6 +271,9 @@ static int nouveau_dsm_pci_probe(struct pci_dev *pdev)
   1  NOUVEAU_DSM_MUX_POWER))
retval |= NOUVEAU_DSM_HAS_MUX;
  
+	if (nouveau_check_gmux_dsm(dhandle))

+   retval |= NOUVEAU_DSM_HAS_GMUX;
+
if (nouveau_check_optimus_dsm(dhandle))
retval |= NOUVEAU_DSM_HAS_OPT;
  
@@ -263,6 +299,7 @@ static bool nouveau_dsm_detect(void)

struct pci_dev *pdev = NULL;
int has_dsm = 0;
int has_optimus = 0;
+   bool has_gmux = false;
int vga_count = 0;
bool guid_valid;
int retval;
@@ -283,6 +320,8 @@ static bool nouveau_dsm_detect(void)
has_dsm |= 1;
if (retval  NOUVEAU_DSM_HAS_OPT)
has_optimus = 1;
+   if (retval  NOUVEAU_DSM_HAS_GMUX)
+   has_gmux = true;
}
  
  	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D  8, pdev)) != NULL) {

@@ -293,9 +332,11 @@ static bool nouveau_dsm_detect(void)
has_dsm |= 1;
if (retval  NOUVEAU_DSM_HAS_OPT)
has_optimus = 1;
+   if (retval  NOUVEAU_DSM_HAS_GMUX)
+   has_gmux = true;
}
  
-	/* find the optimus DSM or the mux DSM */

+   /* find the optimus DSM, the mux DSM or the gmux DSM */
if (has_optimus == 1) {
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
buffer);
@@ -310,6 +351,13 @@ static bool nouveau_dsm_detect(void)
acpi_method_name);
nouveau_dsm_priv.mux_detected = true;
ret = true;
+   } else if (has_gmux) {
+   acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
+   buffer);
+   printk(KERN_INFO VGA switcheroo: detected gmux DSM switching method 
%s handle\n,
+   acpi_method_name);
+

[Nouveau] [PATCH] fix a wrong use of a logical operator in drmmode_output_dpms()

2015-05-20 Thread Samuel Pitoiset

This is probably a typo error which has been introduced in 2009...
This fixes the following warning detected by Clang :

drmmode_display.c:907:30: warning: use of logical '' with constant operand 
[-Wconstant-logical-operand]
if (props  (props-flags  DRM_MODE_PROP_ENUM)) {

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 src/drmmode_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 7c1d2bb..161bccd 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -904,7 +904,7 @@ drmmode_output_dpms(xf86OutputPtr output, int mode)
 
for (i = 0; i  koutput-count_props; i++) {
props = drmModeGetProperty(drmmode-fd, koutput-props[i]);
-   if (props  (props-flags  DRM_MODE_PROP_ENUM)) {
+   if (props  (props-flags  DRM_MODE_PROP_ENUM)) {
if (!strcmp(props-name, DPMS)) {
mode_id = koutput-props[i];
drmModeFreeProperty(props);
-- 
2.4.1

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Re: [Nouveau] [PATCH 8/8] acpi: Use booleans when probing different _DSM types

2015-05-26 Thread Samuel Pitoiset




On 05/26/2015 02:46 PM, Pierre Moreau wrote:

I'm thinking of re-writing this patch to just OR the different returned retval 
and test for individual bits directly in the final conditionals.
So this would give something like:


int retval = 0;

while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA  8, pdev)) != NULL) {
vga_count++;
retval |= nouveau_dsm_pci_probe(pdev);
}
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D  8, pdev)) != NULL) {
vga_count++;
retval |= nouveau_dsm_pci_probe(pdev);
}

if (retval  NOUVEAU_DSM_HAS_OPT) {
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
buffer);
printk(KERN_INFO VGA switcheroo: detected Optimus DSM method %s 
handle\n,
acpi_method_name);
nouveau_dsm_priv.optimus_detected = true;
ret = true;
} else if (vga_count == 2  (retval  NOUVEAU_DSM_HAS_MUX)  guid_valid) {
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
buffer);
printk(KERN_INFO VGA switcheroo: detected mux DSM switching method %s 
handle\n,
acpi_method_name);
nouveau_dsm_priv.mux_detected = true;
ret = true;
} else if (retval  NOUVEAU_DSM_HAS_GMUX) {
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
buffer);
printk(KERN_INFO VGA switcheroo: detected gmux DSM switching method %s 
handle\n,
acpi_method_name);
nouveau_dsm_priv.gmux_detected = true;
ret = true;
}


Any opinions on this?


If this improves readability of the code, go ahead.



Pierre

- Mail original -

Signed-off-by: Pierre Moreau pierre.mor...@free.fr
---
  drm/nouveau/nouveau_acpi.c | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drm/nouveau/nouveau_acpi.c b/drm/nouveau/nouveau_acpi.c
index 3d6a1ea..5d63621 100644
--- a/drm/nouveau/nouveau_acpi.c
+++ b/drm/nouveau/nouveau_acpi.c
@@ -297,8 +297,8 @@ static bool nouveau_dsm_detect(void)
char acpi_method_name[255] = { 0 };
struct acpi_buffer buffer = {sizeof(acpi_method_name),
acpi_method_name};
struct pci_dev *pdev = NULL;
-   int has_dsm = 0;
-   int has_optimus = 0;
+   bool has_mux = false;
+   bool has_optimus = false;
bool has_gmux = false;
int vga_count = 0;
bool guid_valid;
@@ -317,9 +317,9 @@ static bool nouveau_dsm_detect(void)
  
  		retval = nouveau_dsm_pci_probe(pdev);

if (retval  NOUVEAU_DSM_HAS_MUX)
-   has_dsm |= 1;
+   has_mux = true;
if (retval  NOUVEAU_DSM_HAS_OPT)
-   has_optimus = 1;
+   has_optimus = true;
if (retval  NOUVEAU_DSM_HAS_GMUX)
has_gmux = true;
}
@@ -329,9 +329,9 @@ static bool nouveau_dsm_detect(void)
  
  		retval = nouveau_dsm_pci_probe(pdev);

if (retval  NOUVEAU_DSM_HAS_MUX)
-   has_dsm |= 1;
+   has_mux = true;
if (retval  NOUVEAU_DSM_HAS_OPT)
-   has_optimus = 1;
+   has_optimus = true;
if (retval  NOUVEAU_DSM_HAS_GMUX)
has_gmux = true;
}
@@ -344,7 +344,7 @@ static bool nouveau_dsm_detect(void)
acpi_method_name);
nouveau_dsm_priv.optimus_detected = true;
ret = true;
-   } else if (vga_count == 2  has_dsm  guid_valid) {
+   } else if (vga_count == 2  has_mux  guid_valid) {
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
buffer);
printk(KERN_INFO VGA switcheroo: detected mux DSM switching
method %s handle\n,
--
2.4.1

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[Nouveau] [PATCH 1/4] pm: allow zeroed signals to enable sources

2015-08-04 Thread Samuel Pitoiset

Hardware signals index 0x00 are defined for some domains and they have
to be allowed to enable sources like the others.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/pm/base.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/base.c 
b/drm/nouveau/nvkm/engine/pm/base.c
index 94991d6..48c1ce6 100644
--- a/drm/nouveau/nvkm/engine/pm/base.c
+++ b/drm/nouveau/nvkm/engine/pm/base.c
@@ -134,7 +134,7 @@ nvkm_perfsrc_enable(struct nvkm_pm *ppm, struct 
nvkm_perfctr *ctr)
u32 mask, value;
int i, j;
 
-   for (i = 0; i  4  ctr-signal[i]; i++) {
+   for (i = 0; i  4; i++) {
for (j = 0; j  8  ctr-source[i][j]; j++) {
sig = nvkm_perfsig_find(ppm, ctr-domain,
ctr-signal[i], dom);
@@ -170,7 +170,7 @@ nvkm_perfsrc_disable(struct nvkm_pm *ppm, struct 
nvkm_perfctr *ctr)
u32 mask;
int i, j;
 
-   for (i = 0; i  4  ctr-signal[i]; i++) {
+   for (i = 0; i  4; i++) {
for (j = 0; j  8  ctr-source[i][j]; j++) {
sig = nvkm_perfsig_find(ppm, ctr-domain,
ctr-signal[i], dom);
-- 
2.4.6

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[Nouveau] [PATCH 1/2] pm/nv50: fix wrong addr for ZCULL source on G80:GT215

2015-07-26 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/pm/nv50.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drm/nouveau/nvkm/engine/pm/nv50.c 
b/drm/nouveau/nvkm/engine/pm/nv50.c
index a778bc7..14d474b 100644
--- a/drm/nouveau/nvkm/engine/pm/nv50.c
+++ b/drm/nouveau/nvkm/engine/pm/nv50.c
@@ -34,7 +34,7 @@ nv50_prop_sources[] = {
 
 const struct nvkm_specsrc
 nv50_zcull_sources[] = {
-   { 0x4002ca4, (const struct nvkm_specmux[]) {
+   { 0x402ca4, (const struct nvkm_specmux[]) {
{ 0x7fff, 0, unk0 },
{}
}, pgraph_zcull_pm_unka4 },
-- 
2.4.6

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[Nouveau] [PATCH 2/2] pm/nv50: TPC[0x3] must be used for PGRAPH muxs on G80

2015-07-26 Thread Samuel Pitoiset

I thought that using TPC[0x0] like for G84:GT215 was sufficient on G80,
but it's actually not the case. According to NVIDIA PerfKit on Windows,
we have to configure PGRAPH related muxs on TPC[0x3] for this chipset.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/pm/g84.c  | 25 +
 drm/nouveau/nvkm/engine/pm/nv50.c | 22 +++---
 drm/nouveau/nvkm/engine/pm/priv.h |  1 -
 3 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/pm/g84.c b/drm/nouveau/nvkm/engine/pm/g84.c
index dda539c..815bb0d 100644
--- a/drm/nouveau/nvkm/engine/pm/g84.c
+++ b/drm/nouveau/nvkm/engine/pm/g84.c
@@ -33,6 +33,15 @@ g84_vfetch_sources[] = {
 };
 
 static const struct nvkm_specsrc
+g84_prop_sources[] = {
+   { 0x408e50, (const struct nvkm_specmux[]) {
+   { 0x1f, 0, sel, true },
+   {}
+   }, pgraph_tpc0_prop_pm_mux },
+   {}
+};
+
+static const struct nvkm_specsrc
 g84_crop_sources[] = {
{ 0x407008, (const struct nvkm_specmux[]) {
{ 0xf, 0, sel0, true },
@@ -109,14 +118,14 @@ g84_pm[] = {
{ 0x31, pc02_crop_01, g84_crop_sources },
{ 0x32, pc02_crop_02, g84_crop_sources },
{ 0x33, pc02_crop_03, g84_crop_sources },
-   { 0x00, pc02_prop_00, nv50_prop_sources },
-   { 0x01, pc02_prop_01, nv50_prop_sources },
-   { 0x02, pc02_prop_02, nv50_prop_sources },
-   { 0x03, pc02_prop_03, nv50_prop_sources },
-   { 0x04, pc02_prop_04, nv50_prop_sources },
-   { 0x05, pc02_prop_05, nv50_prop_sources },
-   { 0x06, pc02_prop_06, nv50_prop_sources },
-   { 0x07, pc02_prop_07, nv50_prop_sources },
+   { 0x00, pc02_prop_00, g84_prop_sources },
+   { 0x01, pc02_prop_01, g84_prop_sources },
+   { 0x02, pc02_prop_02, g84_prop_sources },
+   { 0x03, pc02_prop_03, g84_prop_sources },
+   { 0x04, pc02_prop_04, g84_prop_sources },
+   { 0x05, pc02_prop_05, g84_prop_sources },
+   { 0x06, pc02_prop_06, g84_prop_sources },
+   { 0x07, pc02_prop_07, g84_prop_sources },
{ 0x48, pc02_tex_00, g84_tex_sources },
{ 0x49, pc02_tex_01, g84_tex_sources },
{ 0x4a, pc02_tex_02, g84_tex_sources },
diff --git a/drm/nouveau/nvkm/engine/pm/nv50.c 
b/drm/nouveau/nvkm/engine/pm/nv50.c
index 14d474b..dee73af 100644
--- a/drm/nouveau/nvkm/engine/pm/nv50.c
+++ b/drm/nouveau/nvkm/engine/pm/nv50.c
@@ -24,15 +24,6 @@
 #include nv40.h
 
 const struct nvkm_specsrc
-nv50_prop_sources[] = {
-   { 0x408e50, (const struct nvkm_specmux[]) {
-   { 0x1f, 0, sel, true },
-   {}
-   }, pgraph_tpc0_prop_pm_mux },
-   {}
-};
-
-const struct nvkm_specsrc
 nv50_zcull_sources[] = {
{ 0x402ca4, (const struct nvkm_specmux[]) {
{ 0x7fff, 0, unk0 },
@@ -52,6 +43,15 @@ nv50_zrop_sources[] = {
 };
 
 static const struct nvkm_specsrc
+nv50_prop_sources[] = {
+   { 0x40be50, (const struct nvkm_specmux[]) {
+   { 0x1f, 0, sel, true },
+   {}
+   }, pgraph_tpc3_prop_pm_mux },
+   {}
+};
+
+static const struct nvkm_specsrc
 nv50_crop_sources[] = {
 { 0x407008, (const struct nvkm_specmux[]) {
 { 0x7, 0, sel0, true },
@@ -63,10 +63,10 @@ nv50_crop_sources[] = {
 
 static const struct nvkm_specsrc
 nv50_tex_sources[] = {
-   { 0x408808, (const struct nvkm_specmux[]) {
+   { 0x40b808, (const struct nvkm_specmux[]) {
{ 0x3fff, 0, unk0 },
{}
-   }, pgraph_tpc0_tex_unk08 },
+   }, pgraph_tpc3_tex_unk08 },
{}
 };
 
diff --git a/drm/nouveau/nvkm/engine/pm/priv.h 
b/drm/nouveau/nvkm/engine/pm/priv.h
index 5bcc739..69b7278 100644
--- a/drm/nouveau/nvkm/engine/pm/priv.h
+++ b/drm/nouveau/nvkm/engine/pm/priv.h
@@ -44,7 +44,6 @@ struct nvkm_perfsrc {
bool enable;
 };
 
-extern const struct nvkm_specsrc nv50_prop_sources[];
 extern const struct nvkm_specsrc nv50_zcull_sources[];
 extern const struct nvkm_specsrc nv50_zrop_sources[];
 extern const struct nvkm_specsrc g84_vfetch_sources[];
-- 
2.4.6

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Re: [Nouveau] [Mesa-dev] [PATCH] nvc0: bind a fake tess control program when there isn't one available

2015-07-26 Thread Samuel Pitoiset




On 07/26/2015 06:56 AM, Ilia Mirkin wrote:

Apparently this is necessary in order for tess factors to work in a tess
eval program without a tess control program bound. Probably because it
uses the fake program's shader header to work out the number of patch
constants.

Fixes vs-tes-tessinner-tessouter-inputs

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
  src/gallium/drivers/nouveau/nvc0/nvc0_context.c  |  5 +
  src/gallium/drivers/nouveau/nvc0/nvc0_context.h  |  3 +++
  src/gallium/drivers/nouveau/nvc0/nvc0_program.c  | 17 +
  src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c |  6 +-
  4 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
index 84f8db6..46970db 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
@@ -132,6 +132,9 @@ nvc0_context_unreference_resources(struct nvc0_context 
*nvc0)
pipe_resource_reference(res, NULL);
 }
 util_dynarray_fini(nvc0-global_residents);
+
+   if (nvc0-tcp_empty)
+  nvc0-base.pipe.delete_tcs_state(nvc0-base.pipe, nvc0-tcp_empty);
  }
  
  static void

@@ -326,6 +329,8 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
  
 /* shader builtin library is per-screen, but we need a context for m2mf */

 nvc0_program_library_upload(nvc0);
+   nvc0_program_init_tcp_empty(nvc0);
+   nvc0-dirty |= NVC0_NEW_TCTLPROG;
  
 /* add permanently resident buffers to bufctxts */
  
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h

index f449942..df1a891 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -128,6 +128,8 @@ struct nvc0_context {
 struct nvc0_program *fragprog;
 struct nvc0_program *compprog;
  
+   struct nvc0_program *tcp_empty;

+
 struct nvc0_constbuf constbuf[6][NVC0_MAX_PIPE_CONSTBUFS];
 uint16_t constbuf_dirty[6];
 uint16_t constbuf_valid[6];
@@ -227,6 +229,7 @@ void nvc0_program_destroy(struct nvc0_context *, struct 
nvc0_program *);
  void nvc0_program_library_upload(struct nvc0_context *);
  uint32_t nvc0_program_symbol_offset(const struct nvc0_program *,
  uint32_t label);
+void nvc0_program_init_tcp_empty(struct nvc0_context *);
  
  /* nvc0_query.c */

  void nvc0_init_query_functions(struct nvc0_context *);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 4941831..e9975ce 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -22,6 +22,8 @@
  
  #include pipe/p_defines.h
  
+#include tgsi/tgsi_ureg.h

+
  #include nvc0/nvc0_context.h
  
  #include codegen/nv50_ir_driver.h

@@ -803,3 +805,18 @@ nvc0_program_symbol_offset(const struct nvc0_program 
*prog, uint32_t label)
   return prog-code_base + base + syms[i].offset;
 return prog-code_base; /* no symbols or symbol not found */
  }
+
+void
+nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
+{
+   struct ureg_program *ureg;
+
+   ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
+   if (!ureg)
+  return;
+
+   ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
+   ureg_END(ureg);
+
+   nvc0-tcp_empty = ureg_create_shader_and_destroy(ureg, nvc0-base.pipe);
+}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
index 8aa127a..e21515f 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
@@ -148,8 +148,12 @@ nvc0_tctlprog_validate(struct nvc0_context *nvc0)
BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(2)), 1);
PUSH_DATA (push, tp-num_gprs);
 } else {
-  BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
+  tp = nvc0-tcp_empty;
+  if (!nvc0_program_validate(nvc0, tp))
+ assert(!unable to validate empty tcp);
+  BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 2);
PUSH_DATA (push, 0x20);
+  PUSH_DATA (push, tp-code_base);
 }


It would be good to check if tp is not NULL before trying to validate 
the program.
And if the program can't be validated, I don't think we want to push 
tp-code_base, isn't it?



 nvc0_program_update_context_state(nvc0, tp, 1);
  }


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Re: [Nouveau] [PATCH] nv50: adjust min/max lod by base level on G80

2015-07-20 Thread Samuel Pitoiset


Reviewed-by: Samuel Pitoiset samuel.pitoi...@gmail.com

On 07/20/2015 09:26 AM, Ilia Mirkin wrote:

Make the assumption that there's a 1:1 TIC - TSC connection, and
increase min/max lod by the relevant texture's base level. Also if
there's no mipfilter, we have to enable it while forcing min/max lod to
the base level.

This fixes many, but not all, tex-miplevel-selection tests on G80.

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---

All the textureLod tests fail. If I also adjust the lod_bias by the
first_level, then the regular tests start failing.

Not sure what the right move is here... need to trace the blob to see
what it does here.

  src/gallium/drivers/nouveau/nv50/nv50_state.c  |  1 +
  .../drivers/nouveau/nv50/nv50_stateobj_tex.h   |  1 +
  src/gallium/drivers/nouveau/nv50/nv50_tex.c| 39 ++
  3 files changed, 41 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state.c 
b/src/gallium/drivers/nouveau/nv50/nv50_state.c
index d4d41af..98c4c3a 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state.c
@@ -464,6 +464,7 @@ nv50_sampler_state_create(struct pipe_context *pipe,
 struct nv50_tsc_entry *so = MALLOC_STRUCT(nv50_tsc_entry);
 float f[2];
  
+   so-pipe = *cso;

 so-id = -1;
  
 so-tsc[0] = (0x00026000 |

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h 
b/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h
index 99548cb..9a19166 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_stateobj_tex.h
@@ -5,6 +5,7 @@
  #include pipe/p_state.h
  
  struct nv50_tsc_entry {

+   struct pipe_sampler_state pipe;
 int id;
 uint32_t tsc[8];
  };
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_tex.c 
b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
index 17ae27f..d79c813 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
@@ -344,6 +344,45 @@ nv50_validate_tsc(struct nv50_context *nv50, int s)
   PUSH_DATA (push, (i  4) | 0);
   continue;
}
+  if (nv50-base.screen-class_3d == NV50_3D_CLASS) {
+ struct nv50_tic_entry *tic = nv50_tic_entry(nv50-textures[s][i]);
+
+ /* We must make sure that the MIN_LOD is at least set to the first
+  * level for the G80
+  */
+ bool need_update = false;
+ float min_lod = CLAMP(
+   tic-pipe.u.tex.first_level + tsc-pipe.min_lod, 0.0f, 15.0f);
+ float max_lod = CLAMP(
+   tic-pipe.u.tex.first_level + tsc-pipe.max_lod, 0.0f, 15.0f);
+
+ if (tsc-pipe.min_mip_filter == PIPE_TEX_MIPFILTER_NONE) {
+uint32_t old_tsc1 = tsc-tsc[1];
+tsc-tsc[1] = ~NV50_TSC_1_MIPF__MASK;
+if (tic-pipe.u.tex.first_level) {
+   tsc-tsc[1] |= NV50_TSC_1_MIPF_NEAREST;
+   max_lod = min_lod = tic-pipe.u.tex.first_level;
+}
+if (tsc-tsc[1] != old_tsc1)
+   need_update = true;
+ }
+
+ uint32_t new_tsc2 =
+(((int)(max_lod * 256.0f)  0xfff)  12) |
+((int)(min_lod * 256.0f)  0xfff);
+ if ((tsc-tsc[2]  0xff) != new_tsc2) {
+tsc-tsc[2] = ~0xffu;
+tsc-tsc[2] |= new_tsc2;
+need_update = true;
+ }
+
+ if (need_update  tsc-id = 0) {
+nv50_sifc_linear_u8(nv50-base, nv50-screen-txc,
+65536 + tsc-id * 32,
+NOUVEAU_BO_VRAM, 32, tsc-tsc);
+need_flush = TRUE;
+ }
+  }
if (tsc-id  0) {
   tsc-id = nv50_screen_tsc_alloc(nv50-screen, tsc);
  


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Re: [Nouveau] [Mesa-dev] [PATCH] nvc0: fix geometry program revalidation of clipping params

2015-07-13 Thread Samuel Pitoiset

What piglit test does this fix?

On Sat, Jul 11, 2015 at 7:13 PM, Ilia Mirkin imir...@alum.mit.edu wrote:

 Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
 Cc: mesa-sta...@lists.freedesktop.org
 ---

 Even though in practice a geometry program will never be using UCP's,
 we still were revalidating (aka recompiling) the program when more
 clip planes became enabled (which also are used for regular clip
 distances).

 This seems like it should have led to massive fail, but I guess you
 don't change the number of clip planes when using geometry shaders.
 But I'm going to put this through a full piglit run just in case
 there's something I'm missing.

  src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
 b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
 index 785e52e..11f2b10 100644
 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
 +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
 @@ -339,7 +339,7 @@ nvc0_check_program_ucps(struct nvc0_context *nvc0,
nvc0_vertprog_validate(nvc0);
 else
 if (likely(vp == nvc0-gmtyprog))
 -  nvc0_vertprog_validate(nvc0);
 +  nvc0_gmtyprog_validate(nvc0);
 else
nvc0_tevlprog_validate(nvc0);
  }
 --
 2.3.6

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-- 
Best regards,
Samuel Pitoiset.
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Re: [Nouveau] [Mesa-dev] [PATCH] nv50: avoid using inline vertex data submit when gl_VertexID is used

2015-08-24 Thread Samuel Pitoiset




On 08/24/2015 10:02 PM, Ilia Mirkin wrote:

Edge flag stuff is annoying. Pretty sure only blender uses it. shade
model = flat should get fixed on nv50 before edge flags, since blender
uses that too, and it's produces much worse visual artifacts.


No rush for this one though.



I'm having second thoughts about this patch. I think I'm going to go
back to my previous approach of just calling
nv50_vertex_arrays_validate when vbo_fifo  vertexid. I suspect that
vertexid usage with small draws from client buffers is next to
inexistent, no need to re-emit this stuff so often.


Good, I'd be happy to have a look at this second approach.



On Mon, Aug 24, 2015 at 4:07 PM, Samuel Pitoiset
samuel.pitoi...@gmail.com wrote:

Reviewed-by: Samuel Pitoiset samuel.pitoi...@gmail.com

This fix is simpler than I was expected. What about the edge flag stuff now?
:)


On 08/24/2015 05:51 PM, Ilia Mirkin wrote:

The hardware only generates vertexid when vertices come from a VBO. This
fixes:

vertexid-drawelements
vertexid-drawarrays

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Cc: 11.0 mesa-sta...@lists.freedesktop.org
---
   src/gallium/drivers/nouveau/nv50/nv50_program.c| 1 +
   src/gallium/drivers/nouveau/nv50/nv50_program.h| 1 +
   src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 3 ++-
   src/gallium/drivers/nouveau/nv50/nv50_vbo.c| 8 
   4 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index 02dc367..eff4477 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -66,6 +66,7 @@ nv50_vertprog_assign_slots(struct nv50_ir_prog_info
*info)
 case TGSI_SEMANTIC_VERTEXID:
prog-vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
prog-vp.attrs[2] |=
NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID_DRAW_ARRAYS_ADD_START;
+ prog-vp.vertexid = 1;
continue;
 default:
break;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.h
b/src/gallium/drivers/nouveau/nv50/nv50_program.h
index 5d3ff56..f4e8e94 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.h
@@ -76,6 +76,7 @@ struct nv50_program {
 ubyte psiz;/* output slot of point size */
 ubyte bfc[2];  /* indices into varying for FFC (FP) or BFC
(VP) */
 ubyte edgeflag;
+  ubyte vertexid;
 ubyte clpd[2]; /* output slot of clip distance[i]'s 1st
component */
 ubyte clpd_nr;
  } vp;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index b304a17..66dcf43 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -503,7 +503,8 @@ static struct state_validate {
   { nv50_validate_samplers,  NV50_NEW_SAMPLERS },
   { nv50_stream_output_validate, NV50_NEW_STRMOUT |
  NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG
},
-{ nv50_vertex_arrays_validate, NV50_NEW_VERTEX | NV50_NEW_ARRAYS },
+{ nv50_vertex_arrays_validate, NV50_NEW_VERTEX | NV50_NEW_ARRAYS |
+   NV50_NEW_VERTPROG },
   { nv50_validate_min_samples,   NV50_NEW_MIN_SAMPLES },
   };
   #define validate_list_len (sizeof(validate_list) /
sizeof(validate_list[0]))
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
index 600b973..fb4305f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -301,6 +301,14 @@ nv50_vertex_arrays_validate(struct nv50_context
*nv50)
  unsigned i;
  const unsigned n = MAX2(vertex-num_elements,
nv50-state.num_vtxelts);
   +   /* A vertexid is not generated for inline data uploads. Have to use
a
+* VBO. This check must come after the vertprog has been validated,
+* otherwise vertexid may be unset.
+*/
+   assert(nv50-vertprog-translated);
+   if (nv50-vertprog-vp.vertexid)
+  nv50-vbo_push_hint = 0;
+
  if (unlikely(vertex-need_conversion))
 nv50-vbo_fifo = ~0;
  else




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Re: [Nouveau] [Mesa-dev] [PATCH] nv50: avoid using inline vertex data submit when gl_VertexID is used

2015-08-24 Thread Samuel Pitoiset


Reviewed-by: Samuel Pitoiset samuel.pitoi...@gmail.com

This fix is simpler than I was expected. What about the edge flag stuff 
now? :)


On 08/24/2015 05:51 PM, Ilia Mirkin wrote:

The hardware only generates vertexid when vertices come from a VBO. This
fixes:

   vertexid-drawelements
   vertexid-drawarrays

Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
Cc: 11.0 mesa-sta...@lists.freedesktop.org
---
  src/gallium/drivers/nouveau/nv50/nv50_program.c| 1 +
  src/gallium/drivers/nouveau/nv50/nv50_program.h| 1 +
  src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 3 ++-
  src/gallium/drivers/nouveau/nv50/nv50_vbo.c| 8 
  4 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c 
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index 02dc367..eff4477 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -66,6 +66,7 @@ nv50_vertprog_assign_slots(struct nv50_ir_prog_info *info)
case TGSI_SEMANTIC_VERTEXID:
   prog-vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
   prog-vp.attrs[2] |= 
NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID_DRAW_ARRAYS_ADD_START;
+ prog-vp.vertexid = 1;
   continue;
default:
   break;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.h 
b/src/gallium/drivers/nouveau/nv50/nv50_program.h
index 5d3ff56..f4e8e94 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.h
@@ -76,6 +76,7 @@ struct nv50_program {
ubyte psiz;/* output slot of point size */
ubyte bfc[2];  /* indices into varying for FFC (FP) or BFC (VP) */
ubyte edgeflag;
+  ubyte vertexid;
ubyte clpd[2]; /* output slot of clip distance[i]'s 1st component */
ubyte clpd_nr;
 } vp;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c 
b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index b304a17..66dcf43 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -503,7 +503,8 @@ static struct state_validate {
  { nv50_validate_samplers,  NV50_NEW_SAMPLERS },
  { nv50_stream_output_validate, NV50_NEW_STRMOUT |
 NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG },
-{ nv50_vertex_arrays_validate, NV50_NEW_VERTEX | NV50_NEW_ARRAYS },
+{ nv50_vertex_arrays_validate, NV50_NEW_VERTEX | NV50_NEW_ARRAYS |
+   NV50_NEW_VERTPROG },
  { nv50_validate_min_samples,   NV50_NEW_MIN_SAMPLES },
  };
  #define validate_list_len (sizeof(validate_list) / sizeof(validate_list[0]))
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c 
b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
index 600b973..fb4305f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -301,6 +301,14 @@ nv50_vertex_arrays_validate(struct nv50_context *nv50)
 unsigned i;
 const unsigned n = MAX2(vertex-num_elements, nv50-state.num_vtxelts);
  
+   /* A vertexid is not generated for inline data uploads. Have to use a

+* VBO. This check must come after the vertprog has been validated,
+* otherwise vertexid may be unset.
+*/
+   assert(nv50-vertprog-translated);
+   if (nv50-vertprog-vp.vertexid)
+  nv50-vbo_push_hint = 0;
+
 if (unlikely(vertex-need_conversion))
nv50-vbo_fifo = ~0;
 else


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Re: [Nouveau] llvm TGSI backend (WIP) questions

2015-11-13 Thread Samuel Pitoiset




On 11/13/2015 02:46 PM, Hans de Goede wrote:

Hi All,


Hey Hans,



So as discussed I've started working on a TGSI backend for
llvm to use as a way to get compute going on nouveau (and other gpu-s).

I'm still learning all the ins and outs of llvm so I do not have
much to show yet.

I've rebased Francisco's (curro's) latest version on top of llvm
trunk, and added a commit on top to actual get it build with the
latest trunk. So currently I'm at the point where I've just
taken Francisco's code, and made it compile, no more and no less.

I have a git repo with this work available here:

http://cgit.freedesktop.org/~jwrdegoede/llvm/


Thanks for sharing your work. :-)



So the next step would be to test this and see if it actually
does anything, questions:

1) Does anyone have a simple test case / command where I can
invoke just llvm and get TGSI asm output to check ?

2) Assuming I get the above to (somewhat) work, is there a
way to make llvm show the output of the various intermediate
passes in a human readable form ?


Basically, you need to ask Clang to emit LLVM code for you, for example, 
this command will emit LLVM IR:


clang -cc1 -cl-std=CL1.2 -emit-llvm -triple spir64-unknown-unknown kernel.cl

Note that this command only works with an old LLVM version (I don't 
remember exactly).


But in your case, and for that TGSI backend, I don't think there is a 
-emit-tgsi option which can directly output TGSI from OpenCL.


The other way, and in my opinion the best, is to write a little C++ 
program based on Clang/LLVM API for generating TGSI code. To do that,
you can have a look at 
src/gallium/state_trackers/clover/llvm/invocation.cpp which contains an 
example (but it seems to be outdated).


Basically, you need to call that CompilerInvocation object with some 
parameters and all the stuff around. This should not take more than 
100LOC in my opinion. I think the first step should be to emit LLVM IR 
before trying to get TGSI working.


I could write that program for you if you want but I don't think to have 
time to do it during this weekend.


Thanks.



Regards,

Hans


--
-Samuel
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Re: [Nouveau] [PATCH] nv50, nvc0: don't base decisions on available pushbuf space

2015-10-10 Thread Samuel Pitoiset




On 10/10/2015 09:42 PM, Ilia Mirkin wrote:

On Sat, Oct 10, 2015 at 3:41 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:

This patch looks fine except that it should be a bit more normalized. I
mean, sometimes you break when PUSH_SPACE fails, sometimes not. Same for
PUSH_SPACE calls, sometimes you add it sometimes not.

Meh. We need to get our error checking situation straight, but this
isn't the patch to do it in.


Yeah, but this needs to be clarified.




Did you run a full piglit test this time ? :)

Nope, but I ran a full piglit before this patch. Almost took down my
box. Probably won't be running it again for this patch.


Ok, I'll run a full piglit this night then.




See my comment below.


On 10/10/2015 11:09 AM, Ilia Mirkin wrote:

We still have to push everything out, might as well kick earlier and
flip pushbufs when we know we'll need it. This resolves some issues with
the new policy of making sure that we always leave a bit of room at the
end for fences.

Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: mesa-sta...@lists.freedesktop.org
---
   src/gallium/drivers/nouveau/nv50/nv50_shader_state.c |  9 ++---
   src/gallium/drivers/nouveau/nv50/nv50_transfer.c | 16
+++-
   src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c | 20
+---
   3 files changed, 10 insertions(+), 35 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
index fdde11f..941555f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
@@ -65,14 +65,9 @@ nv50_constbufs_validate(struct nv50_context *nv50)
  PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
   }
   while (words) {
-   unsigned nr;
-
-   if (!PUSH_SPACE(push, 16))
-  break;
-   nr = PUSH_AVAIL(push);
-   assert(nr >= 16);
-   nr = MIN2(MIN2(nr - 3, words), NV04_PFIFO_MAX_PACKET_LEN);
+   unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
   +   PUSH_SPACE(push, nr + 3);


This PUSH_SPACE call doesn't seem to be needed for me because
NV50_PUSH_EXPLICIT_SPACE_CHECKING is not set and the following BEGIN_XXX
calls will allocate space.

I want to ensure that both of the below commands are in the same
batch. Not sure if it's necessary, but... don't want to find out. They
were in the same batch before. And this batch stuff is what was
causing the M2MF errors I was seeing earlier.




  BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
  PUSH_DATA (push, (start << 8) | b);
  BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
index be51407..9a3fd1e 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
@@ -187,14 +187,7 @@ nv50_sifc_linear_u8(struct nouveau_context *nv,
  PUSH_DATA (push, 0);
while (count) {
-  unsigned nr;
-
-  if (!PUSH_SPACE(push, 16))
- break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 1);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN);
+  unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
   BEGIN_NI04(push, NV50_2D(SIFC_DATA), nr);
 PUSH_DATAp(push, src, nr);
@@ -395,12 +388,9 @@ nv50_cb_push(struct nouveau_context *nv,
  nouveau_pushbuf_validate(push);
while (words) {
-  unsigned nr;
-
-  nr = PUSH_AVAIL(push);
-  nr = MIN2(nr - 7, words);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+  unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
   +  PUSH_SPACE(push, nr + 7);
 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 PUSH_DATAh(push, bo->offset + base);
 PUSH_DATA (push, bo->offset + base);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
index aaec60a..d459dd6 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
@@ -188,14 +188,10 @@ nvc0_m2mf_push_linear(struct nouveau_context *nv,
  nouveau_pushbuf_validate(push);
while (count) {
-  unsigned nr;
+  unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
   -  if (!PUSH_SPACE(push, 16))
+  if (!PUSH_SPACE(push, nr + 9))
break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 9);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN);
   BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);
 PUSH_DATAh(push, dst->offset + offset);
@@ -234,14 +230,10 @@ nve4_p2mf_push_linear(struct nouveau_context *nv,
  nouveau_pushbuf_validate(push);
whi

Re: [Nouveau] [Mesa-dev] [PATCH] nouveau: avoid emitting new fences unnecessarily

2015-10-10 Thread Samuel Pitoiset


Does this fix those texelFetch piglit tests ? Or is it the second patch ?

Anyway, this patch is :

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

On 10/10/2015 08:12 AM, Ilia Mirkin wrote:

Right now we emit on every kick, but this is only necessary if something
will ever be able to observe that the fence completed. If there are no
refs, leave the fence alone and emit it another day.

This also happens to work around an issue for the kick handler -- a kick
can be a result of e.g. nouveau_bo_wait or explicit kick, or it can be
due to lack of space in the pushbuf. We want the emit to happen in the
current batch, so we want there to always be enough space. However an
explicit kick could take the reserved space for the implicitly-triggered
kick's fence emission if it happened right after. With the new mechanism,
hopefully there's no way to cause two fences to be emitted into the same
reserved space.

Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: mesa-sta...@lists.freedesktop.org
Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence)
---
  src/gallium/drivers/nouveau/nouveau_fence.c | 12 +---
  1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nouveau_fence.c 
b/src/gallium/drivers/nouveau/nouveau_fence.c
index ee4e08d..18b1592 100644
--- a/src/gallium/drivers/nouveau/nouveau_fence.c
+++ b/src/gallium/drivers/nouveau/nouveau_fence.c
@@ -190,8 +190,10 @@ nouveau_fence_wait(struct nouveau_fence *fence)
 /* wtf, someone is waiting on a fence in flush_notify handler? */
 assert(fence->state != NOUVEAU_FENCE_STATE_EMITTING);
  
-   if (fence->state < NOUVEAU_FENCE_STATE_EMITTED)

+   if (fence->state < NOUVEAU_FENCE_STATE_EMITTED) {
+  PUSH_SPACE(screen->pushbuf, 8);
nouveau_fence_emit(fence);
+   }
  
 if (fence->state < NOUVEAU_FENCE_STATE_FLUSHED)

if (nouveau_pushbuf_kick(screen->pushbuf, screen->pushbuf->channel))
@@ -224,8 +226,12 @@ nouveau_fence_wait(struct nouveau_fence *fence)
  void
  nouveau_fence_next(struct nouveau_screen *screen)
  {
-   if (screen->fence.current->state < NOUVEAU_FENCE_STATE_EMITTING)
-  nouveau_fence_emit(screen->fence.current);
+   if (screen->fence.current->state < NOUVEAU_FENCE_STATE_EMITTING) {
+  if (screen->fence.current->ref > 1)
+ nouveau_fence_emit(screen->fence.current);
+  else
+ return;
+   }
  
 nouveau_fence_ref(NULL, >fence.current);
  


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Re: [Nouveau] [PATCH] nv50, nvc0: don't base decisions on available pushbuf space

2015-10-10 Thread Samuel Pitoiset

This patch looks fine except that it should be a bit more normalized. I 
mean, sometimes you break when PUSH_SPACE fails, sometimes not. Same for 
PUSH_SPACE calls, sometimes you add it sometimes not.


Did you run a full piglit test this time ? :)

See my comment below.

On 10/10/2015 11:09 AM, Ilia Mirkin wrote:

We still have to push everything out, might as well kick earlier and
flip pushbufs when we know we'll need it. This resolves some issues with
the new policy of making sure that we always leave a bit of room at the
end for fences.

Signed-off-by: Ilia Mirkin 
Cc: mesa-sta...@lists.freedesktop.org
---
  src/gallium/drivers/nouveau/nv50/nv50_shader_state.c |  9 ++---
  src/gallium/drivers/nouveau/nv50/nv50_transfer.c | 16 +++-
  src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c | 20 +---
  3 files changed, 10 insertions(+), 35 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c 
b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
index fdde11f..941555f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
@@ -65,14 +65,9 @@ nv50_constbufs_validate(struct nv50_context *nv50)
 PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  }
  while (words) {
-   unsigned nr;
-
-   if (!PUSH_SPACE(push, 16))
-  break;
-   nr = PUSH_AVAIL(push);
-   assert(nr >= 16);
-   nr = MIN2(MIN2(nr - 3, words), NV04_PFIFO_MAX_PACKET_LEN);
+   unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
  
+   PUSH_SPACE(push, nr + 3);


This PUSH_SPACE call doesn't seem to be needed for me because 
NV50_PUSH_EXPLICIT_SPACE_CHECKING is not set and the following BEGIN_XXX 
calls will allocate space.



 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 PUSH_DATA (push, (start << 8) | b);
 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c 
b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
index be51407..9a3fd1e 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
@@ -187,14 +187,7 @@ nv50_sifc_linear_u8(struct nouveau_context *nv,
 PUSH_DATA (push, 0);
  
 while (count) {

-  unsigned nr;
-
-  if (!PUSH_SPACE(push, 16))
- break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 1);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN);
+  unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
  
BEGIN_NI04(push, NV50_2D(SIFC_DATA), nr);

PUSH_DATAp(push, src, nr);
@@ -395,12 +388,9 @@ nv50_cb_push(struct nouveau_context *nv,
 nouveau_pushbuf_validate(push);
  
 while (words) {

-  unsigned nr;
-
-  nr = PUSH_AVAIL(push);
-  nr = MIN2(nr - 7, words);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+  unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
  
+  PUSH_SPACE(push, nr + 7);

BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
PUSH_DATAh(push, bo->offset + base);
PUSH_DATA (push, bo->offset + base);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
index aaec60a..d459dd6 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
@@ -188,14 +188,10 @@ nvc0_m2mf_push_linear(struct nouveau_context *nv,
 nouveau_pushbuf_validate(push);
  
 while (count) {

-  unsigned nr;
+  unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
  
-  if (!PUSH_SPACE(push, 16))

+  if (!PUSH_SPACE(push, nr + 9))
   break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 9);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN);
  
BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);

PUSH_DATAh(push, dst->offset + offset);
@@ -234,14 +230,10 @@ nve4_p2mf_push_linear(struct nouveau_context *nv,
 nouveau_pushbuf_validate(push);
  
 while (count) {

-  unsigned nr;
+  unsigned nr = MIN2(count, (NV04_PFIFO_MAX_PACKET_LEN - 1));
  
-  if (!PUSH_SPACE(push, 16))

+  if (!PUSH_SPACE(push, nr + 10))
   break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 8);
-  nr = MIN2(nr, (NV04_PFIFO_MAX_PACKET_LEN - 1));
  
BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);

PUSH_DATAh(push, dst->offset + offset);
@@ -571,9 +563,7 @@ nvc0_cb_bo_push(struct nouveau_context *nv,
 PUSH_DATA (push, bo->offset + base);
  
 while (words) {

-  unsigned nr = PUSH_AVAIL(push);
-  nr = MIN2(nr, words);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+  unsigned nr = MIN2(words,

Re: [Nouveau] [PATCH] nv50, nvc0: don't base decisions on available pushbuf space

2015-10-10 Thread Samuel Pitoiset




On 10/10/2015 09:58 PM, Ilia Mirkin wrote:

On Sat, Oct 10, 2015 at 3:55 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:


On 10/10/2015 09:42 PM, Ilia Mirkin wrote:

On Sat, Oct 10, 2015 at 3:41 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:

This patch looks fine except that it should be a bit more normalized. I
mean, sometimes you break when PUSH_SPACE fails, sometimes not. Same for
PUSH_SPACE calls, sometimes you add it sometimes not.

Meh. We need to get our error checking situation straight, but this
isn't the patch to do it in.


Yeah, but this needs to be clarified.

What does?


I mean, we should either use PUSH_SPACE everywhere or not at all, and 
always breaks (or not) when PUSH_SPACE fails.

That's really a minor issue.


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Re: [Nouveau] [PATCH] nv50, nvc0: don't base decisions on available pushbuf space

2015-10-10 Thread Samuel Pitoiset




On 10/10/2015 10:17 PM, Ilia Mirkin wrote:

On Sat, Oct 10, 2015 at 4:21 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:


On 10/10/2015 09:58 PM, Ilia Mirkin wrote:

On Sat, Oct 10, 2015 at 3:55 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:


On 10/10/2015 09:42 PM, Ilia Mirkin wrote:

On Sat, Oct 10, 2015 at 3:41 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:

This patch looks fine except that it should be a bit more normalized. I
mean, sometimes you break when PUSH_SPACE fails, sometimes not. Same
for
PUSH_SPACE calls, sometimes you add it sometimes not.

Meh. We need to get our error checking situation straight, but this
isn't the patch to do it in.


Yeah, but this needs to be clarified.

What does?


I mean, we should either use PUSH_SPACE everywhere or not at all, and always
breaks (or not) when PUSH_SPACE fails.
That's really a minor issue.

It's actually a major issue. Error-handling is practically
non-existent. There are a couple of spots here and there, but it
doesn't really scale up. I guess I (semi-)accidentally removed a
couple of spots that error checked, but, again, meh. Doing this for
real will require some careful thought.


Yeah, okay. So we really need to improve error-handling. :)


   -ilia


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Re: [Nouveau] [PATCH] nv50, nvc0: don't base decisions on available pushbuf space

2015-10-11 Thread Samuel Pitoiset

I did a full piglit run on Fermi. There are no regressions and you fixed 
texelFetch tests and other ones which failed with that assert.


I'm lazy to do it on Tesla, so:

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

Thanks!

On 10/10/2015 11:09 AM, Ilia Mirkin wrote:

We still have to push everything out, might as well kick earlier and
flip pushbufs when we know we'll need it. This resolves some issues with
the new policy of making sure that we always leave a bit of room at the
end for fences.

Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: mesa-sta...@lists.freedesktop.org
---
  src/gallium/drivers/nouveau/nv50/nv50_shader_state.c |  9 ++---
  src/gallium/drivers/nouveau/nv50/nv50_transfer.c | 16 +++-
  src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c | 20 +---
  3 files changed, 10 insertions(+), 35 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c 
b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
index fdde11f..941555f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c
@@ -65,14 +65,9 @@ nv50_constbufs_validate(struct nv50_context *nv50)
 PUSH_DATA (push, (b << 12) | (i << 8) | p | 1);
  }
  while (words) {
-   unsigned nr;
-
-   if (!PUSH_SPACE(push, 16))
-  break;
-   nr = PUSH_AVAIL(push);
-   assert(nr >= 16);
-   nr = MIN2(MIN2(nr - 3, words), NV04_PFIFO_MAX_PACKET_LEN);
+   unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
  
+   PUSH_SPACE(push, nr + 3);

 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 PUSH_DATA (push, (start << 8) | b);
 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c 
b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
index be51407..9a3fd1e 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
@@ -187,14 +187,7 @@ nv50_sifc_linear_u8(struct nouveau_context *nv,
 PUSH_DATA (push, 0);
  
 while (count) {

-  unsigned nr;
-
-  if (!PUSH_SPACE(push, 16))
- break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 1);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN);
+  unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
  
BEGIN_NI04(push, NV50_2D(SIFC_DATA), nr);

PUSH_DATAp(push, src, nr);
@@ -395,12 +388,9 @@ nv50_cb_push(struct nouveau_context *nv,
 nouveau_pushbuf_validate(push);
  
 while (words) {

-  unsigned nr;
-
-  nr = PUSH_AVAIL(push);
-  nr = MIN2(nr - 7, words);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+  unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
  
+  PUSH_SPACE(push, nr + 7);

BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
PUSH_DATAh(push, bo->offset + base);
PUSH_DATA (push, bo->offset + base);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
index aaec60a..d459dd6 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
@@ -188,14 +188,10 @@ nvc0_m2mf_push_linear(struct nouveau_context *nv,
 nouveau_pushbuf_validate(push);
  
 while (count) {

-  unsigned nr;
+  unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
  
-  if (!PUSH_SPACE(push, 16))

+  if (!PUSH_SPACE(push, nr + 9))
   break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 9);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN);
  
BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2);

PUSH_DATAh(push, dst->offset + offset);
@@ -234,14 +230,10 @@ nve4_p2mf_push_linear(struct nouveau_context *nv,
 nouveau_pushbuf_validate(push);
  
 while (count) {

-  unsigned nr;
+  unsigned nr = MIN2(count, (NV04_PFIFO_MAX_PACKET_LEN - 1));
  
-  if (!PUSH_SPACE(push, 16))

+  if (!PUSH_SPACE(push, nr + 10))
   break;
-  nr = PUSH_AVAIL(push);
-  assert(nr >= 16);
-  nr = MIN2(count, nr - 8);
-  nr = MIN2(nr, (NV04_PFIFO_MAX_PACKET_LEN - 1));
  
BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);

PUSH_DATAh(push, dst->offset + offset);
@@ -571,9 +563,7 @@ nvc0_cb_bo_push(struct nouveau_context *nv,
 PUSH_DATA (push, bo->offset + base);
  
 while (words) {

-  unsigned nr = PUSH_AVAIL(push);
-  nr = MIN2(nr, words);
-  nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+  unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN - 1);
  
PUSH_SPACE(push, nr + 2);

PUSH_REFN (push, bo, NOUVEAU_BO_WR | domain);


___

Re: [Nouveau] [PATCH] nouveau: make sure there's always room to emit a fence

2015-10-05 Thread Samuel Pitoiset


Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

On 10/05/2015 09:21 PM, Ilia Mirkin wrote:

I started seeing a lot of situations on nv30 where fence emission
wouldn't fit into the previous buffer (causing assertions). This ensures
that whenever checking for space, we always leave a bit of extra room
for the fence emission commands. Adjusts the nv30 and nvc0 fence
emission logic to bypass the space checking as well.

Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: mesa-sta...@lists.freedesktop.org
---
  src/gallium/drivers/nouveau/nouveau_winsys.h   | 2 ++
  src/gallium/drivers/nouveau/nv30/nv30_screen.c | 4 +++-
  src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 +
  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ++-
  4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h 
b/src/gallium/drivers/nouveau/nouveau_winsys.h
index 389a229..a44fd3e 100644
--- a/src/gallium/drivers/nouveau/nouveau_winsys.h
+++ b/src/gallium/drivers/nouveau/nouveau_winsys.h
@@ -24,6 +24,8 @@ PUSH_AVAIL(struct nouveau_pushbuf *push)
  static inline bool
  PUSH_SPACE(struct nouveau_pushbuf *push, uint32_t size)
  {
+   /* Provide a buffer so that fences always have room to be emitted */
+   size += 8;
 if (PUSH_AVAIL(push) < size)
return nouveau_pushbuf_space(push, size, 0, 0) == 0;
 return true;
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c 
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index 39267b3..335c163 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -347,7 +347,9 @@ nv30_screen_fence_emit(struct pipe_screen *pscreen, 
uint32_t *sequence)
  
 *sequence = ++screen->base.fence.sequence;
  
-   BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);

+   assert(PUSH_AVAIL(push) >= 3);
+   PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
+  (2 /* size */ << 18) | (7 /* subchan */ << 13));


Is there some other places where we do something like this?
If so, maybe we should introduce NV30_FIFO_PKHDR_SQ.


 PUSH_DATA (push, 0);
 PUSH_DATA (push, *sequence);
  }
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 6012ff6..812b246 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -388,6 +388,7 @@ nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 
*sequence)
 /* we need to do it after possible flush in MARK_RING */
 *sequence = ++screen->base.fence.sequence;
  
+   assert(PUSH_AVAIL(push) >= 5);

 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 PUSH_DATAh(push, screen->fence.bo->offset);
 PUSH_DATA (push, screen->fence.bo->offset);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 32da76c..afd91e6 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -537,7 +537,8 @@ nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 
*sequence)
 /* we need to do it after possible flush in MARK_RING */
 *sequence = ++screen->base.fence.sequence;
  
-   BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);

+   assert(PUSH_AVAIL(push) >= 5);
+   PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 PUSH_DATAh(push, screen->fence.bo->offset);
 PUSH_DATA (push, screen->fence.bo->offset);
 PUSH_DATA (push, *sequence);


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[Nouveau] [PATCH] core: remove unused variables detected by Clang

2015-08-26 Thread Samuel Pitoiset

These variables have been left since the recent big merge.

Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
 drm/nouveau/nvkm/engine/device/base.c | 4 
 drm/nouveau/nvkm/engine/dma/base.c| 5 -
 drm/nouveau/nvkm/engine/sw/base.c | 5 -
 3 files changed, 14 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/device/base.c 
b/drm/nouveau/nvkm/engine/device/base.c
index 952a508..a32ac99 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -2291,10 +2291,6 @@ nvkm_device_del(struct nvkm_device **pdevice)
}
 }
 
-static const struct nvkm_engine_func
-nvkm_device_func = {
-};
-
 int
 nvkm_device_ctor(const struct nvkm_device_func *func,
 const struct nvkm_device_quirk *quirk,
diff --git a/drm/nouveau/nvkm/engine/dma/base.c 
b/drm/nouveau/nvkm/engine/dma/base.c
index c1957ce..9769fc0 100644
--- a/drm/nouveau/nvkm/engine/dma/base.c
+++ b/drm/nouveau/nvkm/engine/dma/base.c
@@ -97,11 +97,6 @@ nvkm_dma_oclass_fifo_new(const struct nvkm_oclass *oclass, 
void *data, u32 size,
 }
 
 static const struct nvkm_sclass
-nvkm_dma_oclass_fifo = {
-   .ctor = nvkm_dma_oclass_fifo_new,
-};
-
-static const struct nvkm_sclass
 nvkm_dma_sclass[] = {
{ 0, 0, NV_DMA_FROM_MEMORY, NULL, nvkm_dma_oclass_fifo_new },
{ 0, 0, NV_DMA_TO_MEMORY, NULL, nvkm_dma_oclass_fifo_new },
diff --git a/drm/nouveau/nvkm/engine/sw/base.c 
b/drm/nouveau/nvkm/engine/sw/base.c
index d46f229..53c1f7e 100644
--- a/drm/nouveau/nvkm/engine/sw/base.c
+++ b/drm/nouveau/nvkm/engine/sw/base.c
@@ -55,11 +55,6 @@ nvkm_sw_oclass_new(const struct nvkm_oclass *oclass, void 
*data, u32 size,
return sclass-ctor(chan, oclass, data, size, pobject);
 }
 
-static const struct nvkm_sclass
-nvkm_sw_oclass = {
-   .ctor = nvkm_sw_oclass_new,
-};
-
 static int
 nvkm_sw_oclass_get(struct nvkm_oclass *oclass, int index)
 {
-- 
2.5.0

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Re: [Nouveau] [PATCH] [resend] nouveau: Disable AGP for SiS 761

2015-09-30 Thread Samuel Pitoiset


This patch has been merged by Ben yesterday.

http://cgit.freedesktop.org/~darktama/nouveau/commit/?id=8c713f90a63ffca10d122af09d439f3409c933ed

Why do you send a new version ? Is the previous patch wrong?

On 09/30/2015 01:48 PM, Ondrej Zary wrote:

SiS 761 chipset does not support AGP cards but has AGP capability (for
the onboard video). At least PC Chips A31G board using this chipset has
an AGP-like AGPro slot that's wired to the PCI bus. Enabling AGP will
fail (GPU lockup and software fbcon, X11 hangs).

Add support for matching just the host bridge in nvkm_device_agp_quirks
and add entry for SiS 761 with mode 0 (AGP disabled).

Signed-off-by: Ondrej Zary 
---
  drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c |8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c 
b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c
index 814cb51..385a90f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c
@@ -35,6 +35,8 @@ static const struct nvkm_device_agp_quirk
  nvkm_device_agp_quirks[] = {
/* VIA Apollo PRO133x / GeForce FX 5600 Ultra - fdo#20341 */
{ PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_NVIDIA, 0x0311, 2 },
+   /* SiS 761 does not support AGP cards, use PCI mode */
+   { PCI_VENDOR_ID_SI, 0x0761, PCI_ANY_ID, PCI_ANY_ID, 0 },
{},
  };
  
@@ -137,8 +139,10 @@ nvkm_agp_ctor(struct nvkm_pci *pci)

while (quirk->hostbridge_vendor) {
if (info.device->vendor == quirk->hostbridge_vendor &&
info.device->device == quirk->hostbridge_device &&
-   pci->pdev->vendor == quirk->chip_vendor &&
-   pci->pdev->device == quirk->chip_device) {
+   (quirk->chip_vendor == (u16)PCI_ANY_ID ||
+   pci->pdev->vendor == quirk->chip_vendor) &&
+   (quirk->chip_device == (u16)PCI_ANY_ID ||
+   pci->pdev->device == quirk->chip_device)) {
nvkm_info(subdev, "forcing default agp mode to %dX, "
  "use NvAGP= to override\n",
  quirk->mode);


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[Nouveau] [PATCH v3] ibus/gf100: increase wait timeout to avoid read faults

2015-09-24 Thread Samuel Pitoiset

Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.

This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
V3: changed some nvkm_mask() to nvkm_wr32() for gf100 (as the blob does)

 drm/nouveau/include/nvkm/subdev/ibus.h |  1 +
 drm/nouveau/nvkm/engine/device/base.c  |  4 +--
 drm/nouveau/nvkm/subdev/ibus/Kbuild|  1 +
 drm/nouveau/nvkm/subdev/ibus/gf100.c   | 17 ++--
 drm/nouveau/nvkm/subdev/ibus/gf117.c   | 51 ++
 drm/nouveau/nvkm/subdev/ibus/priv.h|  7 +
 6 files changed, 77 insertions(+), 4 deletions(-)
 create mode 100644 drm/nouveau/nvkm/subdev/ibus/gf117.c
 create mode 100644 drm/nouveau/nvkm/subdev/ibus/priv.h

diff --git a/drm/nouveau/include/nvkm/subdev/ibus.h 
b/drm/nouveau/include/nvkm/subdev/ibus.h
index 9d512cd..c4dcd26 100644
--- a/drm/nouveau/include/nvkm/subdev/ibus.h
+++ b/drm/nouveau/include/nvkm/subdev/ibus.h
@@ -3,6 +3,7 @@
 #include 
 
 int gf100_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
+int gf117_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 int gk104_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 int gk20a_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 #endif
diff --git a/drm/nouveau/nvkm/engine/device/base.c 
b/drm/nouveau/nvkm/engine/device/base.c
index 952a508..83383bc 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -1595,7 +1595,7 @@ nvd7_chipset = {
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
.i2c = gf117_i2c_new,
-   .ibus = gf100_ibus_new,
+   .ibus = gf117_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
@@ -1628,7 +1628,7 @@ nvd9_chipset = {
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
.i2c = gf119_i2c_new,
-   .ibus = gf100_ibus_new,
+   .ibus = gf117_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
diff --git a/drm/nouveau/nvkm/subdev/ibus/Kbuild 
b/drm/nouveau/nvkm/subdev/ibus/Kbuild
index a0b12d2..de888fa 100644
--- a/drm/nouveau/nvkm/subdev/ibus/Kbuild
+++ b/drm/nouveau/nvkm/subdev/ibus/Kbuild
@@ -1,3 +1,4 @@
 nvkm-y += nvkm/subdev/ibus/gf100.o
+nvkm-y += nvkm/subdev/ibus/gf117.o
 nvkm-y += nvkm/subdev/ibus/gk104.o
 nvkm-y += nvkm/subdev/ibus/gk20a.o
diff --git a/drm/nouveau/nvkm/subdev/ibus/gf100.c 
b/drm/nouveau/nvkm/subdev/ibus/gf100.c
index 37a0496..72d6330 100644
--- a/drm/nouveau/nvkm/subdev/ibus/gf100.c
+++ b/drm/nouveau/nvkm/subdev/ibus/gf100.c
@@ -21,7 +21,7 @@
  *
  * Authors: Ben Skeggs
  */
-#include 
+#include "priv.h"
 
 static void
 gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i)
@@ -56,7 +56,7 @@ gf100_ibus_intr_gpc(struct nvkm_subdev *ibus, int i)
nvkm_mask(device, 0x128128 + (i * 0x0400), 0x0200, 0x);
 }
 
-static void
+void
 gf100_ibus_intr(struct nvkm_subdev *ibus)
 {
struct nvkm_device *device = ibus->device;
@@ -92,8 +92,21 @@ gf100_ibus_intr(struct nvkm_subdev *ibus)
}
 }
 
+static int
+gf100_ibus_init(struct nvkm_subdev *ibus)
+{
+   struct nvkm_device *device = ibus->device;
+   nvkm_mask(device, 0x122310, 0x0003, 0x0800);
+   nvkm_wr32(device, 0x12232c, 0x00100064);
+   nvkm_wr32(device, 0x122330, 0x00100064);
+   nvkm_wr32(device, 0x122334, 0x00100064);
+   nvkm_mask(device, 0x122348, 0x0003, 0x0100);
+   return 0;
+}
+
 static const struct nvkm_subdev_func
 gf100_ibus = {
+   .init = gf100_ibus_init,
.intr = gf100_ibus_intr,
 };
 
diff --git a/drm/nouveau/nvkm/subdev/ibus/gf117.c 
b/drm/nouveau/nvkm/subdev/ibus/gf117.c
new file mode 100644
index 000..f69f263
--- /dev/null
+++ b/drm/nouveau/nvkm/subdev/ibus/gf117.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2015 Samuel Pitosiet
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR

[Nouveau] [PATCH 1/2] fb/ramgf100: disable memory reclocking by default

2015-09-23 Thread Samuel Pitoiset

Although memory reclocking seems to be completely broken on my GF119, we
can at least allow users to enable reclocking for the core clock.

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
 drm/nouveau/nvkm/subdev/fb/ramgf100.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drm/nouveau/nvkm/subdev/fb/ramgf100.c 
b/drm/nouveau/nvkm/subdev/fb/ramgf100.c
index 772425c..a3219a2 100644
--- a/drm/nouveau/nvkm/subdev/fb/ramgf100.c
+++ b/drm/nouveau/nvkm/subdev/fb/ramgf100.c
@@ -409,7 +409,7 @@ gf100_ram_prog(struct nvkm_ram *base)
 {
struct gf100_ram *ram = gf100_ram(base);
struct nvkm_device *device = ram->base.fb->subdev.device;
-   ram_exec(>fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
+   ram_exec(>fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", false));
return 0;
 }
 
-- 
2.5.3

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Re: [Nouveau] [PATCH 2/2] clk/gf100: allow users to enable reclocking

2015-09-23 Thread Samuel Pitoiset




On 09/24/2015 12:00 AM, Martin Peres wrote:

On 24/09/15 00:20, Samuel Pitoiset wrote:

Only the core clock is currently supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
  drm/nouveau/nvkm/subdev/clk/gf100.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drm/nouveau/nvkm/subdev/clk/gf100.c 
b/drm/nouveau/nvkm/subdev/clk/gf100.c

index a52b7e7..807305a 100644
--- a/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -462,5 +462,5 @@ gf100_clk_new(struct nvkm_device *device, int 
index, struct nvkm_clk **pclk)

  return -ENOMEM;
  *pclk = >base;
  -return nvkm_clk_ctor(_clk, device, index, false, 
>base);

+return nvkm_clk_ctor(_clk, device, index, true, >base);
  }
What changed that suddenly made reclocking OK? You really need to 
prove it is and a few hours of testing are not enough ;)


Make sure that the clock tree is parsed correctly, then programmed 
correctly. Make sure that reclocking while the card is being used is 
also kind of stable, at least on your card.


After that, you may enable it and test on more Fermis. Until then, 
this patch is premature, at best.


Yeah, this is probably a kind of experimental feature for now, but even 
if I didn't check a lot, it seems to be stable (with heaven at least).


Anyways, I'll do more checks to prove that is going to work as expected.

Thanks for your feedbacks Martin.
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[Nouveau] [PATCH 2/2] clk/gf100: allow users to enable reclocking

2015-09-23 Thread Samuel Pitoiset

Only the core clock is currently supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
 drm/nouveau/nvkm/subdev/clk/gf100.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drm/nouveau/nvkm/subdev/clk/gf100.c 
b/drm/nouveau/nvkm/subdev/clk/gf100.c
index a52b7e7..807305a 100644
--- a/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -462,5 +462,5 @@ gf100_clk_new(struct nvkm_device *device, int index, struct 
nvkm_clk **pclk)
return -ENOMEM;
*pclk = >base;
 
-   return nvkm_clk_ctor(_clk, device, index, false, >base);
+   return nvkm_clk_ctor(_clk, device, index, true, >base);
 }
-- 
2.5.3

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[Nouveau] [PATCH] ibus/gf100: increase wait timeout to avoid read faults

2015-09-23 Thread Samuel Pitoiset

Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.

This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
 drm/nouveau/include/nvkm/subdev/ibus.h |  1 +
 drm/nouveau/nvkm/engine/device/base.c  |  4 +--
 drm/nouveau/nvkm/subdev/ibus/Kbuild|  1 +
 drm/nouveau/nvkm/subdev/ibus/gf100.c   | 17 ++--
 drm/nouveau/nvkm/subdev/ibus/gf117.c   | 51 ++
 drm/nouveau/nvkm/subdev/ibus/priv.h|  7 +
 6 files changed, 77 insertions(+), 4 deletions(-)
 create mode 100644 drm/nouveau/nvkm/subdev/ibus/gf117.c
 create mode 100644 drm/nouveau/nvkm/subdev/ibus/priv.h

diff --git a/drm/nouveau/include/nvkm/subdev/ibus.h 
b/drm/nouveau/include/nvkm/subdev/ibus.h
index 9d512cd..c4dcd26 100644
--- a/drm/nouveau/include/nvkm/subdev/ibus.h
+++ b/drm/nouveau/include/nvkm/subdev/ibus.h
@@ -3,6 +3,7 @@
 #include 
 
 int gf100_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
+int gf117_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 int gk104_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 int gk20a_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 #endif
diff --git a/drm/nouveau/nvkm/engine/device/base.c 
b/drm/nouveau/nvkm/engine/device/base.c
index 952a508..83383bc 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -1595,7 +1595,7 @@ nvd7_chipset = {
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
.i2c = gf117_i2c_new,
-   .ibus = gf100_ibus_new,
+   .ibus = gf117_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
@@ -1628,7 +1628,7 @@ nvd9_chipset = {
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
.i2c = gf119_i2c_new,
-   .ibus = gf100_ibus_new,
+   .ibus = gf117_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
diff --git a/drm/nouveau/nvkm/subdev/ibus/Kbuild 
b/drm/nouveau/nvkm/subdev/ibus/Kbuild
index a0b12d2..de888fa 100644
--- a/drm/nouveau/nvkm/subdev/ibus/Kbuild
+++ b/drm/nouveau/nvkm/subdev/ibus/Kbuild
@@ -1,3 +1,4 @@
 nvkm-y += nvkm/subdev/ibus/gf100.o
+nvkm-y += nvkm/subdev/ibus/gf117.o
 nvkm-y += nvkm/subdev/ibus/gk104.o
 nvkm-y += nvkm/subdev/ibus/gk20a.o
diff --git a/drm/nouveau/nvkm/subdev/ibus/gf100.c 
b/drm/nouveau/nvkm/subdev/ibus/gf100.c
index 37a0496..382720f 100644
--- a/drm/nouveau/nvkm/subdev/ibus/gf100.c
+++ b/drm/nouveau/nvkm/subdev/ibus/gf100.c
@@ -21,7 +21,7 @@
  *
  * Authors: Ben Skeggs
  */
-#include 
+#include "priv.h"
 
 static void
 gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i)
@@ -56,7 +56,7 @@ gf100_ibus_intr_gpc(struct nvkm_subdev *ibus, int i)
nvkm_mask(device, 0x128128 + (i * 0x0400), 0x0200, 0x);
 }
 
-static void
+void
 gf100_ibus_intr(struct nvkm_subdev *ibus)
 {
struct nvkm_device *device = ibus->device;
@@ -92,8 +92,21 @@ gf100_ibus_intr(struct nvkm_subdev *ibus)
}
 }
 
+static int
+gf100_ibus_init(struct nvkm_subdev *ibus)
+{
+   struct nvkm_device *device = ibus->device;
+   nvkm_mask(device, 0x122310, 0x0003, 0x0800);
+   nvkm_mask(device, 0x12232c, 0x0003, 0x00100064);
+   nvkm_mask(device, 0x122330, 0x0003, 0x00100064);
+   nvkm_mask(device, 0x122334, 0x0003, 0x00100064);
+   nvkm_mask(device, 0x122348, 0x0003, 0x0100);
+   return 0;
+}
+
 static const struct nvkm_subdev_func
 gf100_ibus = {
+   .init = gf100_ibus_init,
.intr = gf100_ibus_intr,
 };
 
diff --git a/drm/nouveau/nvkm/subdev/ibus/gf117.c 
b/drm/nouveau/nvkm/subdev/ibus/gf117.c
new file mode 100644
index 000..f69f263
--- /dev/null
+++ b/drm/nouveau/nvkm/subdev/ibus/gf117.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2015 Samuel Pitosiet
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAI

[Nouveau] [PATCH v2] ibus/gf100: increase wait timeout to avoid read faults

2015-09-23 Thread Samuel Pitoiset

Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.

This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
V2: increase mask for the gf100 case

 drm/nouveau/include/nvkm/subdev/ibus.h |  1 +
 drm/nouveau/nvkm/engine/device/base.c  |  4 +--
 drm/nouveau/nvkm/subdev/ibus/Kbuild|  1 +
 drm/nouveau/nvkm/subdev/ibus/gf100.c   | 17 ++--
 drm/nouveau/nvkm/subdev/ibus/gf117.c   | 51 ++
 drm/nouveau/nvkm/subdev/ibus/priv.h|  7 +
 6 files changed, 77 insertions(+), 4 deletions(-)
 create mode 100644 drm/nouveau/nvkm/subdev/ibus/gf117.c
 create mode 100644 drm/nouveau/nvkm/subdev/ibus/priv.h

diff --git a/drm/nouveau/include/nvkm/subdev/ibus.h 
b/drm/nouveau/include/nvkm/subdev/ibus.h
index 9d512cd..c4dcd26 100644
--- a/drm/nouveau/include/nvkm/subdev/ibus.h
+++ b/drm/nouveau/include/nvkm/subdev/ibus.h
@@ -3,6 +3,7 @@
 #include 
 
 int gf100_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
+int gf117_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 int gk104_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 int gk20a_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **);
 #endif
diff --git a/drm/nouveau/nvkm/engine/device/base.c 
b/drm/nouveau/nvkm/engine/device/base.c
index 952a508..83383bc 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -1595,7 +1595,7 @@ nvd7_chipset = {
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
.i2c = gf117_i2c_new,
-   .ibus = gf100_ibus_new,
+   .ibus = gf117_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
@@ -1628,7 +1628,7 @@ nvd9_chipset = {
.fuse = gf100_fuse_new,
.gpio = gf119_gpio_new,
.i2c = gf119_i2c_new,
-   .ibus = gf100_ibus_new,
+   .ibus = gf117_ibus_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
diff --git a/drm/nouveau/nvkm/subdev/ibus/Kbuild 
b/drm/nouveau/nvkm/subdev/ibus/Kbuild
index a0b12d2..de888fa 100644
--- a/drm/nouveau/nvkm/subdev/ibus/Kbuild
+++ b/drm/nouveau/nvkm/subdev/ibus/Kbuild
@@ -1,3 +1,4 @@
 nvkm-y += nvkm/subdev/ibus/gf100.o
+nvkm-y += nvkm/subdev/ibus/gf117.o
 nvkm-y += nvkm/subdev/ibus/gk104.o
 nvkm-y += nvkm/subdev/ibus/gk20a.o
diff --git a/drm/nouveau/nvkm/subdev/ibus/gf100.c 
b/drm/nouveau/nvkm/subdev/ibus/gf100.c
index 37a0496..6c61d54 100644
--- a/drm/nouveau/nvkm/subdev/ibus/gf100.c
+++ b/drm/nouveau/nvkm/subdev/ibus/gf100.c
@@ -21,7 +21,7 @@
  *
  * Authors: Ben Skeggs
  */
-#include 
+#include "priv.h"
 
 static void
 gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i)
@@ -56,7 +56,7 @@ gf100_ibus_intr_gpc(struct nvkm_subdev *ibus, int i)
nvkm_mask(device, 0x128128 + (i * 0x0400), 0x0200, 0x);
 }
 
-static void
+void
 gf100_ibus_intr(struct nvkm_subdev *ibus)
 {
struct nvkm_device *device = ibus->device;
@@ -92,8 +92,21 @@ gf100_ibus_intr(struct nvkm_subdev *ibus)
}
 }
 
+static int
+gf100_ibus_init(struct nvkm_subdev *ibus)
+{
+   struct nvkm_device *device = ibus->device;
+   nvkm_mask(device, 0x122310, 0x0003, 0x0800);
+   nvkm_mask(device, 0x12232c, 0x0073, 0x00100064);
+   nvkm_mask(device, 0x122330, 0x0073, 0x00100064);
+   nvkm_mask(device, 0x122334, 0x0073, 0x00100064);
+   nvkm_mask(device, 0x122348, 0x0003, 0x0100);
+   return 0;
+}
+
 static const struct nvkm_subdev_func
 gf100_ibus = {
+   .init = gf100_ibus_init,
.intr = gf100_ibus_intr,
 };
 
diff --git a/drm/nouveau/nvkm/subdev/ibus/gf117.c 
b/drm/nouveau/nvkm/subdev/ibus/gf117.c
new file mode 100644
index 000..f69f263
--- /dev/null
+++ b/drm/nouveau/nvkm/subdev/ibus/gf117.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2015 Samuel Pitosiet
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR

Re: [Nouveau] NV50 compute support questions

2015-12-07 Thread Samuel Pitoiset




On 12/07/2015 04:10 PM, Hans de Goede wrote:

Hi



Hi,


On 04-12-15 09:45, Hans de Goede wrote:


I've ordered a GTX740 (GK107) card, which should arrive soon, and
I'll be using that so I can (hopefully) focus on the llvm tgsi bits
again.


So the card arrived today and I've plugged it in tests/trivial/compute
looks much better with this. But there does seem to be one issue
(other then the atomic bits not working) :

- test_resource_indirect


Exactly, two or three test don't work on Kepler < GK110.
It's on my todolist, but with a low priority. :-)

Thanks for reporting this anyway.


(1, 0)[0]: got 0x2/0.00, expected 0x3/0.00
(3, 0)[0]: got 0x6/0.00, expected 0x7/0.00
(5, 0)[0]: got 0xa/0.00, expected 0xb/0.00
(7, 0)[0]: got 0xe/0.00, expected 0xf/0.00
(9, 0)[0]: got 0x12/0.00, expected 0x13/0.00
(11, 0)[0]: got 0x16/0.00, expected 0x17/0.00
(13, 0)[0]: got 0x1a/0.00, expected 0x1b/0.00
(15, 0)[0]: got 0x1e/0.00, expected 0x1f/0.00
(17, 0)[0]: got 0x22/0.00, expected 0x23/0.00
(19, 0)[0]: got 0x26/0.00, expected 0x27/0.00
(21, 0)[0]: got 0x2a/0.00, expected 0x2b/0.00
(23, 0)[0]: got 0x2e/0.00, expected 0x2f/0.00
(25, 0)[0]: got 0x32/0.00, expected 0x33/0.00
(27, 0)[0]: got 0x36/0.00, expected 0x37/0.00
(29, 0)[0]: got 0x3a/0.00, expected 0x3b/0.00
(31, 0)[0]: got 0x3e/0.00, expected 0x3f/0.00
(33, 0)[0]: got 0x42/0.00, expected 0x43/0.00
(35, 0)[0]: got 0x46/0.00, expected 0x47/0.00
(37, 0)[0]: got 0x4a/0.00, expected 0x4b/0.00
(39, 0)[0]: got 0x4e/0.00, expected 0x4f/0.00
(64, 1): FAIL (32)

Regards,

Hans


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Re: [Nouveau] [mesa v2 8/9] nvc0: remove allocation of unused sw class

2015-12-08 Thread Samuel Pitoiset


NACK.

This patches breaks MP performance counters on Fermi/Kepler because they 
actually use software methods to configure multiplexers. Global perf 
counters will also use software methods to init, sample and read 
hardware counters, so this SW object is definitely needed.


Instead of removing it, we need to do something like that:

http://paste.awesom.eu/EQeX

Thanks.

On 11/27/2015 02:05 AM, Ben Skeggs wrote:

From: Ben Skeggs 

This would need to be fixed before NVIF can be switched on, but since we
don't use it anyway, just remove it.

Signed-off-by: Ben Skeggs 
---
  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 8 
  src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 -
  2 files changed, 9 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 4897ebe..11cb74a 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -447,7 +447,6 @@ nvc0_screen_destroy(struct pipe_screen *pscreen)
 nouveau_object_del(>eng2d);
 nouveau_object_del(>m2mf);
 nouveau_object_del(>compute);
-   nouveau_object_del(>nvsw);

 nouveau_screen_fini(>base);

@@ -698,13 +697,6 @@ nvc0_screen_create(struct nouveau_device *dev)
 screen->base.fence.update = nvc0_screen_fence_update;


-   ret = nouveau_object_new(chan,
-(dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
-NULL, 0, >nvsw);
-   if (ret)
-  FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
-
-
 switch (dev->chipset & ~0xf) {
 case 0x110:
 case 0x100:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 8b73102..caf34aa 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -105,7 +105,6 @@ struct nvc0_screen {
 struct nouveau_object *eng2d;
 struct nouveau_object *m2mf;
 struct nouveau_object *compute;
-   struct nouveau_object *nvsw;
  };

  static inline struct nvc0_screen *



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Re: [Nouveau] NV50 compute support questions

2015-12-02 Thread Samuel Pitoiset

On 12/02/2015 04:34 PM, Hans de Goede wrote:

On 01-12-15, Samuel Pitoiset wrote:

 >>> Ok, here is a MMT trace of vectorAdd:
 >>>
 >>> https://fedorapeople.org/~jwrdegoede/vectorAdd.log.gz
 >>
 >> Hi Hans,
 >>
 >> Thanks a lot.
 >
 > Well, I didn't know but Martin has a GK208...
 > I just tested the compute support on his card and ... it works without
 > any changes. :-)
 >
 > I'm sorry, I was sure the compute support didn't work on this chipset.

No need to be sorry because, ...

 > Feel free to test on your GK208 and report back if you have problems.

I've done that, and for me it does not work, if I try to enable compute
support like this:

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 461fcaa..ab4ea85 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -187,7 +187,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen,
enum pipe_cap param)
 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 case PIPE_CAP_COMPUTE:
-  return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
+  return 1;
 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ?
1 : 0;

@@ -246,8 +246,6 @@ nvc0_screen_get_shader_param(struct pipe_screen
*pscreen, unsigned shader,
   return 0;
break;
 case PIPE_SHADER_COMPUTE:
-  if (class_3d > NVE4_3D_CLASS)
- return 0;
break;
 default:
return 0;
@@ -574,11 +572,10 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
 case 0xd0:
return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 case 0xe0:
-  return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 case 0xf0:
 case 0x100:
 case 0x110:
-  return 0;
+  return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 default:
return -1;
 }

Then as soon as I do startx (which starts gnome-shell) the machine
freezes. This is with mesa-master with the above changes on top.

X / gnome-shell will happily work of I do not call
nve4_screen_compute_setup()
but then test/trivial/compute fails with a null-ptr exception.

Do you perhaps have some extra patches in your tree, or am I just unlucky ?

I've tested this on both a 4.2 and a 4.4-rc3 kernel.

Hi,

My bad... I used the wrong card on reator (which is the REing machine of 
Martin). The primary card is a GK106 and the second one is the GK208. 
That doesn't explain why I did something wrong but heh? :-)

You are right. With those bits added locally, the compute support 
totally hangs the GPU on my GK208 (NV108), and a reboot is needed.

Please give a shot at this branch :
http://cgit.freedesktop.org/~hakzsam/mesa/log/?h=nvf0_compute

It fixes the initialization of the compute state and allows me to
launch 'test_input_global' (ie. ./compute 8) on my GK208 without
any dmesg fails. That's a good start but more patches are coming. :-)

Btw, according to the trace you sent me, you have a GK208b (NV106).

Thanks!

Regards,

Hans

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Re: [Nouveau] NV50 compute support questions

2015-12-04 Thread Samuel Pitoiset




On 12/04/2015 10:12 AM, Hans de Goede wrote:

Hi,

On 04-12-15 09:54, Samuel Pitoiset wrote:



On 12/04/2015 09:45 AM, Hans de Goede wrote:





Please give a shot at this branch :
http://cgit.freedesktop.org/~hakzsam/mesa/log/?h=nvf0_compute

It fixes the initialization of the compute state and allows me to
launch 'test_input_global' (ie. ./compute 8) on my GK208 without
any dmesg fails. That's a good start but more patches are coming. :-)


This branch indeed works somewhat better, but things still hang on the

test_system_values compute test for me (this is the first test executed
I did not try the others). So this seems to need more work.


What about test_input_global? test_system_values doesn't work on my
side but it doesn't hang the GPU.


Yes that one works.


Could you please provide dmesg log?


[2.786631] nouveau :01:00.0: NVIDIA GK208B (b06070b1)
[2.914291] nouveau :01:00.0: bios: version 80.28.79.00.0b
[2.937909] nouveau :01:00.0: priv: HUB0: 086014  (1f70820c)
[2.937953] nouveau :01:00.0: fb: 1024 MiB DDR3
[3.623202] [TTM] Zone  kernel: Available graphics memory: 2010556 kiB
[3.623205] [TTM] Initializing pool allocator
[3.623241] [TTM] Initializing DMA pool allocator
[3.623440] nouveau :01:00.0: DRM: VRAM: 1024 MiB
[3.623442] nouveau :01:00.0: DRM: GART: 1048576 MiB
[3.623447] nouveau :01:00.0: DRM: TMDS table version 2.0
[3.623449] nouveau :01:00.0: DRM: DCB version 4.0
[3.623451] nouveau :01:00.0: DRM: DCB outp 00: 01000f02 00020030
[3.623454] nouveau :01:00.0: DRM: DCB outp 01: 02011f62 00020010
[3.623456] nouveau :01:00.0: DRM: DCB outp 02: 02022f10 
[3.623458] nouveau :01:00.0: DRM: DCB conn 00: 1031
[3.623460] nouveau :01:00.0: DRM: DCB conn 01: 2161
[3.623462] nouveau :01:00.0: DRM: DCB conn 02: 0200
[3.627283] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[3.627285] [drm] Driver supports precise vblank timestamp query.
[3.671871] nouveau :01:00.0: DRM: MM: using COPY for buffer copies
[3.889940] nouveau :01:00.0: DRM: allocated 1920x1080 fb:
0x6, bo 88011905
[3.890952] fbcon: nouveaufb (fb0) is primary device
[4.132343] Console: switching to colour frame buffer device 240x67
[4.134930] nouveau :01:00.0: fb0: nouveaufb frame buffer device
[4.141094] [drm] Initialized nouveau 1.3.1 20120801 for :01:00.0
on minor 0



[ 1713.421460] nouveau :01:00.0: gr: TRAP ch 6 [003fa32000
compute[21117]]
[ 1713.421471] nouveau :01:00.0: gr: GPC0/TPC1/MP trap: global
 [] warp 3000e [MEM_OUT_OF_BOUNDS]
[ 1713.441248] nouveau :01:00.0: gr: TRAP ch 6 [003fa32000
compute[21117]]
[ 1713.441260] nouveau :01:00.0: gr: GPC0/TPC0/MP trap: global
0004 [MULTIPLE_WARP_ERRORS] warp 20005 [MISALIGNED_PC]
[ 1713.441265] nouveau :01:00.0: gr: GPC0/TPC1/MP trap: global
0004 [MULTIPLE_WARP_ERRORS] warp 20005 [MISALIGNED_PC]
[ 1717.773839] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1717.773848] nouveau :01:00.0: fifo: sw engine fault on channel 2,
recovering...
[ 1719.776529] nouveau :01:00.0: fifo: runlist 0 update timeout
[ 1722.068923] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1726.363660] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1730.658395] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1734.951720] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1739.241861] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1743.532005] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1747.826728] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1752.121462] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1756.416200] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1760.710930] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1765.005663] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1769.300396] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1773.595135] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1777.889863] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1782.184598] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1786.479328] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1789.730020] nouveau :01:00.0: compute[21117]: failed to idle
channel 6 [compute[21117]]
[ 1790.774060] nouveau :01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT]
[ 1791.729963] nouveau :01:00.0: timeout at
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c:47/gk104_fifo_gpfifo_kick()!

[ 1791.729966] nouveau :01:00.0: fifo: channel 6 [compute[21117]]
kick timeout
[ 1791.729973] nouveau: compute[21117]::a06f: detach gr
failed, -16
[ 1791.731401] nouveau :01:00.0: fifo: SCHED_ERROR 0d []
[ 1793.731275] nouveau :01

Re: [Nouveau] NV50 compute support questions

2015-12-04 Thread Samuel Pitoiset

On 12/04/2015 09:45 AM, Hans de Goede wrote:

Hi,

On 02-12-15 19:33, Samuel Pitoiset wrote:

On 12/02/2015 04:34 PM, Hans de Goede wrote:

On 01-12-15, Samuel Pitoiset wrote:

 >>> Ok, here is a MMT trace of vectorAdd:
 >>>
 >>> https://fedorapeople.org/~jwrdegoede/vectorAdd.log.gz
 >>
 >> Hi Hans,
 >>
 >> Thanks a lot.
 >
 > Well, I didn't know but Martin has a GK208...
 > I just tested the compute support on his card and ... it works
without
 > any changes. :-)
 >
 > I'm sorry, I was sure the compute support didn't work on this
chipset.

No need to be sorry because, ...

 > Feel free to test on your GK208 and report back if you have problems.

I've done that, and for me it does not work, if I try to enable compute
support like this:

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 461fcaa..ab4ea85 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -187,7 +187,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen,
enum pipe_cap param)
 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 case PIPE_CAP_COMPUTE:
-  return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
+  return 1;
 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ?
1 : 0;

@@ -246,8 +246,6 @@ nvc0_screen_get_shader_param(struct pipe_screen
*pscreen, unsigned shader,
   return 0;
break;
 case PIPE_SHADER_COMPUTE:
-  if (class_3d > NVE4_3D_CLASS)
- return 0;
break;
 default:
return 0;
@@ -574,11 +572,10 @@ nvc0_screen_init_compute(struct nvc0_screen
*screen)
 case 0xd0:
return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 case 0xe0:
-  return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 case 0xf0:
 case 0x100:
 case 0x110:
-  return 0;
+  return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 default:
return -1;
 }

Then as soon as I do startx (which starts gnome-shell) the machine
freezes. This is with mesa-master with the above changes on top.

X / gnome-shell will happily work of I do not call
nve4_screen_compute_setup()
but then test/trivial/compute fails with a null-ptr exception.

Do you perhaps have some extra patches in your tree, or am I just
unlucky ?

I've tested this on both a 4.2 and a 4.4-rc3 kernel.

Hi,

My bad... I used the wrong card on reator (which is the REing machine
of Martin). The primary card is a GK106 and the second one is the
GK208. That doesn't explain why I did something wrong but heh? :-)

You are right. With those bits added locally, the compute support
totally hangs the GPU on my GK208 (NV108), and a reboot is needed.

Please give a shot at this branch :
http://cgit.freedesktop.org/~hakzsam/mesa/log/?h=nvf0_compute

It fixes the initialization of the compute state and allows me to
launch 'test_input_global' (ie. ./compute 8) on my GK208 without
any dmesg fails. That's a good start but more patches are coming. :-)

This branch indeed works somewhat better, but things still hang on the

test_system_values compute test for me (this is the first test executed
I did not try the others). So this seems to need more work.

What about test_input_global? test_system_values doesn't work on my side 
but it doesn't hang the GPU. Could you please provide dmesg log?

I've ordered a GTX740 (GK107) card, which should arrive soon, and
I'll be using that so I can (hopefully) focus on the llvm tgsi bits
again.

Yeah, GK107 will do the job. :-)

Btw, according to the trace you sent me, you have a GK208b (NV106).

Right, sorry I thought the differences between GK208 and GK208b would
not matter.

I don't know exactly the differences between these two chipsets but 
since test_system_values hangs your GPU and not mine, I think they are some.

Thanks for all the input / help!

Regards,

Hans

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Re: [Nouveau] [mesa v3 1/9] nouveau: bump required libdrm version to 2.4.66

2015-12-17 Thread Samuel Pitoiset


This series is:

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

On 12/17/2015 12:21 AM, Ben Skeggs wrote:

From: Ben Skeggs <bske...@redhat.com>

v2. forgot bump for non-gallium driver

Signed-off-by: Ben Skeggs <bske...@redhat.com>
---
  configure.ac | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/configure.ac b/configure.ac
index b6680d0..965c6f7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -72,8 +72,8 @@ LIBDRM_REQUIRED=2.4.60
  LIBDRM_RADEON_REQUIRED=2.4.56
  LIBDRM_AMDGPU_REQUIRED=2.4.63
  LIBDRM_INTEL_REQUIRED=2.4.61
-LIBDRM_NVVIEUX_REQUIRED=2.4.33
-LIBDRM_NOUVEAU_REQUIRED=2.4.62
+LIBDRM_NVVIEUX_REQUIRED=2.4.66
+LIBDRM_NOUVEAU_REQUIRED=2.4.66
  LIBDRM_FREEDRENO_REQUIRED=2.4.65
  DRI2PROTO_REQUIRED=2.6
  DRI3PROTO_REQUIRED=1.0



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Re: [Nouveau] [mesa v3 8/9] nvc0: remove use of deprecated sw class identifier

2015-12-18 Thread Samuel Pitoiset




On 12/18/2015 11:19 AM, Emil Velikov wrote:

The commit summary "remove use of deprecated..." is no longer
applicable. Feel free to tweak (use nvif provided class name/define ?)
before pushing.


Well, the commit summary is fine by me because the old sw class 
identifier is actually deprecated with that new interface and won"t work 
if it's not updated accordingly.


But, feel free to change it. :-)



-Emil
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Re: [Nouveau] [libdrm v3 01/14] nouveau: import and install a selection of nvif headers from the kernel

2015-12-18 Thread Samuel Pitoiset


Hi Ben,

I don't feel comfortable enough with the libdrm nouveau code to give you 
my Rb for this series, but as this seems work as expected, this series is:


Tested-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

Thanks for your work!

On 12/17/2015 12:20 AM, Ben Skeggs wrote:

From: Ben Skeggs <bske...@redhat.com>

This commit also modifies the install path of the main libdrm_nouveau
header to be under a nouveau/ subdirectory.

Signed-off-by: Ben Skeggs <bske...@redhat.com>
---
  include/drm/nouveau_drm.h|   1 +
  nouveau/Makefile.am  |  11 +++-
  nouveau/libdrm_nouveau.pc.in |   2 +-
  nouveau/nvif/cl0080.h|  45 ++
  nouveau/nvif/cl9097.h|  44 ++
  nouveau/nvif/class.h | 141 +++
  nouveau/nvif/if0002.h|  38 
  nouveau/nvif/if0003.h|  33 ++
  nouveau/nvif/ioctl.h | 132 
  nouveau/nvif/unpack.h|  28 +
  10 files changed, 473 insertions(+), 2 deletions(-)
  create mode 100644 nouveau/nvif/cl0080.h
  create mode 100644 nouveau/nvif/cl9097.h
  create mode 100644 nouveau/nvif/class.h
  create mode 100644 nouveau/nvif/if0002.h
  create mode 100644 nouveau/nvif/if0003.h
  create mode 100644 nouveau/nvif/ioctl.h
  create mode 100644 nouveau/nvif/unpack.h

diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index 87aefc5..e418f9f 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -200,6 +200,7 @@ struct drm_nouveau_sarea {
  #define DRM_NOUVEAU_GROBJ_ALLOC0x04
  #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05
  #define DRM_NOUVEAU_GPUOBJ_FREE0x06
+#define DRM_NOUVEAU_NVIF   0x07
  #define DRM_NOUVEAU_GEM_NEW0x40
  #define DRM_NOUVEAU_GEM_PUSHBUF0x41
  #define DRM_NOUVEAU_GEM_CPU_PREP   0x42
diff --git a/nouveau/Makefile.am b/nouveau/Makefile.am
index 25ea6dc..76cdeca 100644
--- a/nouveau/Makefile.am
+++ b/nouveau/Makefile.am
@@ -14,9 +14,18 @@ libdrm_nouveau_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@

  libdrm_nouveau_la_SOURCES = $(LIBDRM_NOUVEAU_FILES)

-libdrm_nouveauincludedir = ${includedir}/libdrm
+libdrm_nouveauincludedir = ${includedir}/libdrm/nouveau
  libdrm_nouveauinclude_HEADERS = $(LIBDRM_NOUVEAU_H_FILES)

+libdrm_nouveaunvifincludedir = ${includedir}/libdrm/nouveau/nvif
+libdrm_nouveaunvifinclude_HEADERS = nvif/class.h \
+   nvif/cl0080.h \
+   nvif/cl9097.h \
+   nvif/if0002.h \
+   nvif/if0003.h \
+   nvif/ioctl.h \
+   nvif/unpack.h
+
  pkgconfigdir = @pkgconfigdir@
  pkgconfig_DATA = libdrm_nouveau.pc

diff --git a/nouveau/libdrm_nouveau.pc.in b/nouveau/libdrm_nouveau.pc.in
index 9abfd81..7d0622e 100644
--- a/nouveau/libdrm_nouveau.pc.in
+++ b/nouveau/libdrm_nouveau.pc.in
@@ -7,5 +7,5 @@ Name: libdrm_nouveau
  Description: Userspace interface to nouveau kernel DRM services
  Version: @PACKAGE_VERSION@
  Libs: -L${libdir} -ldrm_nouveau
-Cflags: -I${includedir} -I${includedir}/libdrm
+Cflags: -I${includedir} -I${includedir}/libdrm -I${includedir}/libdrm/nouveau
  Requires.private: libdrm
diff --git a/nouveau/nvif/cl0080.h b/nouveau/nvif/cl0080.h
new file mode 100644
index 000..331620a
--- /dev/null
+++ b/nouveau/nvif/cl0080.h
@@ -0,0 +1,45 @@
+#ifndef __NVIF_CL0080_H__
+#define __NVIF_CL0080_H__
+
+struct nv_device_v0 {
+   __u8  version;
+   __u8  pad01[7];
+   __u64 device;   /* device identifier, ~0 for client default */
+};
+
+#define NV_DEVICE_V0_INFO  0x00
+#define NV_DEVICE_V0_TIME  0x01
+
+struct nv_device_info_v0 {
+   __u8  version;
+#define NV_DEVICE_INFO_V0_IGP  0x00
+#define NV_DEVICE_INFO_V0_PCI  0x01
+#define NV_DEVICE_INFO_V0_AGP  0x02
+#define NV_DEVICE_INFO_V0_PCIE 0x03
+#define NV_DEVICE_INFO_V0_SOC  0x04
+   __u8  platform;
+   __u16 chipset;  /* from NV_PMC_BOOT_0 */
+   __u8  revision; /* from NV_PMC_BOOT_0 */
+#define NV_DEVICE_INFO_V0_TNT  0x01
+#define NV_DEVICE_INFO_V0_CELSIUS  0x02
+#define NV_DEVICE_INFO_V0_KELVIN   0x03
+#define NV_DEVICE_INFO_V0_RANKINE  0x04
+#define NV_DEVICE_INFO_V0_CURIE0x05
+#define NV_DEVICE_INFO_V0_TESLA0x06
+#define NV_DE

Re: [Nouveau] NV50 compute support questions

2015-11-30 Thread Samuel Pitoiset




On 11/30/2015 02:27 PM, Hans de Goede wrote:

Hi,

On 26-11-15 13:52, Samuel Pitoiset wrote:




I do not have a GK106, I've a GK208, and IIRC that one is known to not
work,
I guess I can give it a try.


Compute support is not supported on GK110+, yeah...

If you provide me a MMT trace of, for example, vectorAdd from the CUDA
samples I could have a look.


Ok, here is a MMT trace of vectorAdd:

https://fedorapeople.org/~jwrdegoede/vectorAdd.log.gz


Hi Hans,

Thanks a lot.



Regards,

Hans


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Re: [Nouveau] NV50 compute support questions

2015-12-01 Thread Samuel Pitoiset




On 11/30/2015 04:13 PM, Samuel Pitoiset wrote:



On 11/30/2015 02:27 PM, Hans de Goede wrote:

Hi,

On 26-11-15 13:52, Samuel Pitoiset wrote:




I do not have a GK106, I've a GK208, and IIRC that one is known to not
work,
I guess I can give it a try.


Compute support is not supported on GK110+, yeah...

If you provide me a MMT trace of, for example, vectorAdd from the CUDA
samples I could have a look.


Ok, here is a MMT trace of vectorAdd:

https://fedorapeople.org/~jwrdegoede/vectorAdd.log.gz


Hi Hans,

Thanks a lot.


Well, I didn't know but Martin has a GK208...
I just tested the compute support on his card and ... it works without 
any changes. :-)


I'm sorry, I was sure the compute support didn't work on this chipset.

Feel free to test on your GK208 and report back if you have problems.

Thanks.





Regards,

Hans




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