Re: [Nouveau] [PATCH v3 04/27] drm: Don't test for IRQ support in VBLANK ioctls

2021-06-26 Thread Thierry Reding
On Thu, Jun 24, 2021 at 11:07:57AM +0200, Thomas Zimmermann wrote: > Hi > > Am 24.06.21 um 10:51 schrieb Jani Nikula: > > On Thu, 24 Jun 2021, Thomas Zimmermann wrote: > > > Hi > > > > > > Am 24.06.21 um 10:06 schrieb Jani Nikula: > > > > On Thu, 24 Jun 2021, Thomas Zimmermann wrote: > > > > >

Re: [Nouveau] [PATCH v3 21/27] drm/tegra: Don't set struct drm_device.irq_enabled

2021-06-26 Thread Thierry Reding
-by: Daniel Vetter > --- > drivers/gpu/drm/tegra/drm.c | 7 --- > 1 file changed, 7 deletions(-) Acked-by: Thierry Reding signature.asc Description: PGP signature ___ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH] nouveau/gem: fix user-after-free in nouveau_gem_new

2021-05-17 Thread Thierry Reding
On Mon, May 17, 2021 at 09:32:44AM -0400, Jeremy Cline wrote: > On Mon, May 17, 2021 at 11:19:02AM +0200, Thierry Reding wrote: > > On Mon, May 17, 2021 at 10:56:29AM +0200, Thierry Reding wrote: > > > On Tue, May 11, 2021 at 06:35:53PM +0200, Karol Herbst wrote: > >

Re: [Nouveau] [PATCH] nouveau/gem: fix user-after-free in nouveau_gem_new

2021-05-17 Thread Thierry Reding
On Mon, May 17, 2021 at 10:56:29AM +0200, Thierry Reding wrote: > On Tue, May 11, 2021 at 06:35:53PM +0200, Karol Herbst wrote: > > If ttm_bo_init fails it will already call ttm_bo_put, so we don't have to > > do it through

Re: [Nouveau] [PATCH] nouveau/gem: fix user-after-free in nouveau_gem_new

2021-05-17 Thread Thierry Reding
[nouveau] > drm_ioctl_kernel+0xb2/0x100 [drm] > drm_ioctl+0x215/0x390 [drm] > nouveau_drm_ioctl+0x55/0xa0 [nouveau] > __x64_sys_ioctl+0x83/0xb0 > do_syscall_64+0x33/0x40 > entry_SYSCALL_64_after_hwframe+0x44/0xae > > Fixes: 019cbd4a4feb3 "drm/nouveau: Initialize GEM

Re: [Nouveau] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini

2021-04-23 Thread Thierry Reding
On Thu, Apr 22, 2021 at 01:18:09PM -0400, Lyude Paul wrote: > On Tue, 2021-04-20 at 02:16 +0300, Ville Syrjälä wrote: > > > > The init vs. register split is intentional. Registering the thing > > and allowing userspace access to it before the rest of the driver > > is ready isn't particularly

Re: [Nouveau] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini

2021-04-23 Thread Thierry Reding
On Fri, Apr 23, 2021 at 12:11:06AM -0400, Lyude Paul wrote: > On Thu, 2021-04-22 at 18:33 -0400, Lyude Paul wrote: > > OK - talked with Ville a bit on this and did some of my own research, I > > actually think that moving i2c to drm_dp_aux_init() is the right decision > > for > > the time being.

Re: [Nouveau] [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini

2021-04-23 Thread Thierry Reding
On Thu, Apr 22, 2021 at 06:33:44PM -0400, Lyude Paul wrote: > OK - talked with Ville a bit on this and did some of my own research, I > actually think that moving i2c to drm_dp_aux_init() is the right decision for > the time being. The reasoning behind this being that as shown by my previous >

Re: [Nouveau] [PATCH 03/30] drm/tegra: Don't register DP AUX channels before connectors

2021-04-14 Thread Thierry Reding
On Fri, Feb 19, 2021 at 04:52:59PM -0500, Lyude Paul wrote: > As pointed out by the documentation for drm_dp_aux_register(), > drm_dp_aux_init() should be used in situations where the AUX channel for a > display driver can potentially be registered before it's respective DRM > driver. This is the

Re: [Nouveau] [PATCH v2 05/20] drm/dp: Add backpointer to drm_device in drm_dp_aux

2021-03-30 Thread Thierry Reding
rely on drm_dp_aux->drm_dev to always be > non-NULL until drm_dp_aux_register() has been called. We make sure to point > this out in the documentation for struct drm_dp_aux. > > Signed-off-by: Lyude Paul > --- [...] > drivers/gpu/drm/tegra/dpaux.c

Re: [Nouveau] [PATCH v2 02/20] drm/tegra: Don't register DP AUX channels before connectors

2021-03-29 Thread Thierry Reding
to use > the AUX channel before we've associated it with it's DRM connector. > > Signed-off-by: Lyude Paul > --- > drivers/gpu/drm/tegra/dpaux.c | 11 ++- > 1 file changed, 6 insertions(+), 5 deletions(-) Acked-by: Thierry Reding

Re: [Nouveau] [PATCH 0/6] drm/nouveau: Support sync FDs and sync objects

2020-09-24 Thread Thierry Reding
On Wed, Sep 23, 2020 at 05:21:24PM +0200, Daniel Vetter wrote: > On Wed, Sep 23, 2020 at 11:18:53AM +0200, Thierry Reding wrote: > > On Fri, Aug 28, 2020 at 12:40:10PM +0200, Thierry Reding wrote: > > > From: Thierry Reding > > > > > > Hi, > > &

Re: [Nouveau] [PATCH 0/6] drm/nouveau: Support sync FDs and sync objects

2020-09-23 Thread Thierry Reding
On Fri, Aug 28, 2020 at 12:40:10PM +0200, Thierry Reding wrote: > From: Thierry Reding > > Hi, > > This series implements a new IOCTL to submit push buffers that can > optionally return a sync FD or sync object to userspace. This is useful > in cases where userspace

Re: [Nouveau] [PATCH v2 14/21] drm/tegra: Introduce GEM object functions

2020-09-17 Thread Thierry Reding
omas Zimmermann > --- > drivers/gpu/drm/tegra/drm.c | 4 > drivers/gpu/drm/tegra/gem.c | 8 > 2 files changed, 8 insertions(+), 4 deletions(-) Acked-by: Thierry Reding signature.asc Description: PGP signature ___ Nouveau mailing list No

[Nouveau] [PATCH 5/6] drm/nouveau: Support DMA fence arrays

2020-08-28 Thread Thierry Reding
From: Thierry Reding A DMA fence can be composed of multiple fences in an array. Support this in the Nouveau driver by iteratively synchronizing to each DMA fence in the array. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nouveau_fence.c | 31 ++--- 1 file

[Nouveau] [PATCH 6/6] drm/nouveau: Allow zero pushbuffer submits

2020-08-28 Thread Thierry Reding
From: Thierry Reding These are useful in cases where only a fence is to be created to wait for existing jobs in the command stream. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nouveau_gem.c | 197 +- 1 file changed, 99 insertions(+), 98 deletions(-) diff

[Nouveau] [PATCH 4/6] drm/nouveau: Support sync FDs and syncobjs

2020-08-28 Thread Thierry Reding
From: Thierry Reding Extends the new NOUVEAU_GEM_PUSHBUF2 IOCTL to accept and emit one or more sync FDs and/or DRM native sync objects. Signed-off-by: Thierry Reding --- Note: If acceptable, this should be merged into the previous patch that adds the new IOCTL. drivers/gpu/drm/nouveau

[Nouveau] [PATCH 3/6] drm/nouveau: Support fence FDs at kickoff

2020-08-28 Thread Thierry Reding
From: Thierry Reding Add a new NOUVEAU_GEM_PUSHBUF2 IOCTL that accepts and emits a sync fence FD from/to userspace if requested by the corresponding flags. Based heavily on work by Lauri Peltonen Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nouveau_drm.c | 1 + drivers/gpu/drm

[Nouveau] [PATCH 1/6] drm/nouveau: Split nouveau_fence_sync()

2020-08-28 Thread Thierry Reding
From: Thierry Reding Turn nouveau_fence_sync() into a low-level helper that adds fence waits to the channel command stream. The new nouveau_bo_sync() helper replaces the previous nouveau_fence_sync() implementation. It passes each of the buffer object's fences to nouveau_fence_sync() in turn

[Nouveau] [PATCH 0/6] drm/nouveau: Support sync FDs and sync objects

2020-08-28 Thread Thierry Reding
From: Thierry Reding Hi, This series implements a new IOCTL to submit push buffers that can optionally return a sync FD or sync object to userspace. This is useful in cases where userspace wants to synchronize operations between the GPU and another driver (such as KMS for display). Among other

[Nouveau] [PATCH 2/6] drm/nouveau: Add nouveau_fence_ref()

2020-08-28 Thread Thierry Reding
From: Thierry Reding This is a simple wrapper that increments the reference count of the backing DMA fence. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nouveau_fence.c | 9 + drivers/gpu/drm/nouveau/nouveau_fence.h | 1 + 2 files changed, 10 insertions(+) diff --git

[Nouveau] [PATCH] drm/nouveau: gr/gk20a: Use firmware version 0

2020-06-03 Thread Thierry Reding
From: Thierry Reding Tegra firmware doesn't actually use any version numbers and passing -1 causes the existing firmware binaries not to be found. Use version 0 to find the correct files. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 2 +- 1 file changed

[Nouveau] [PATCH] drm/nouveau: gp10b: Use gp100_grctx and gp100_gr_zbc

2020-01-15 Thread Thierry Reding
From: Thierry Reding gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 1 + drivers/gpu

[Nouveau] [PATCH] drm/nouveau: gm20b, gp10b: Fix Falcon bootstrapping

2020-01-15 Thread Thierry Reding
From: Thierry Reding The low-level Falcon bootstrapping callbacks are expected to return 0 on success or a negative error code on failure. However, the implementation on Tegra returns the ID or mask of the Falcons that were bootstrapped on success, thus breaking the calling code, which treats

Re: [Nouveau] [PATCH v3 0/9] drm/nouveau: Various fixes for GP10B

2019-12-10 Thread Thierry Reding
On Tue, Dec 10, 2019 at 06:15:30PM +1000, Ben Skeggs wrote: > On Mon, 9 Dec 2019 at 22:00, Thierry Reding wrote: > > > > From: Thierry Reding > > > > Hi Ben, > > > > here's a revised subset of the patches I had sent out a couple of weeks > > ag

[Nouveau] [PATCH v3 8/9] drm/nouveau: gp10b: Add custom L2 cache implementation

2019-12-09 Thread Thierry Reding
From: Thierry Reding There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding --- Changes in v2: - remove IOMMU_API protection

[Nouveau] [PATCH v3 9/9] drm/nouveau: gp10b: Use correct copy engine

2019-12-09 Thread Thierry Reding
From: Thierry Reding gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine

[Nouveau] [PATCH v3 7/9] drm/nouveau: secboot: Read WPR configuration from GPU registers

2019-12-09 Thread Thierry Reding
From: Thierry Reding The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding --- .../drm/nouveau/nvkm/subdev

[Nouveau] [PATCH v3 0/9] drm/nouveau: Various fixes for GP10B

2019-12-09 Thread Thierry Reding
From: Thierry Reding Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet

[Nouveau] [PATCH v3 4/9] drm/nouveau: tegra: Do not try to disable PCI device

2019-12-09 Thread Thierry Reding
From: Thierry Reding When Nouveau is instantiated on top of a platform device, the dev->pdev field will be NULL and calling pci_disable_device() will crash. Move the PCI disabling code to the PCI specific driver removal code. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouv

[Nouveau] [PATCH v3 5/9] drm/nouveau: tegra: Avoid pulsing reset twice

2019-12-09 Thread Thierry Reding
From: Thierry Reding When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power

[Nouveau] [PATCH v3 6/9] drm/nouveau: tegra: Set clock rate if not set

2019-12-09 Thread Thierry Reding
From: Thierry Reding If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu

[Nouveau] [PATCH v3 1/9] iommu: Document iommu_fwspec::flags field

2019-12-09 Thread Thierry Reding
From: Thierry Reding When this field was added in commit 5702ee24182f ("ACPI/IORT: Check ATS capability in root complex nodes"), the kerneldoc comment wasn't updated at the same time. Acked-by: Joerg Roedel Signed-off-by: Thierry Reding --- include/linux/iommu.h | 1 + 1 file

[Nouveau] [PATCH v3 3/9] drm/nouveau: fault: Add support for GP10B

2019-12-09 Thread Thierry Reding
From: Thierry Reding There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault

[Nouveau] [PATCH v3 2/9] iommu: Add dummy dev_iommu_fwspec_get() helper

2019-12-09 Thread Thierry Reding
From: Thierry Reding This dummy implementation is useful to avoid a dependency on the IOMMU_API Kconfig symbol in drivers that can optionally use the IOMMU API. In order to fully use this, also move the struct iommu_fwspec definition out of the IOMMU_API protected region. Acked-by: Joerg

Re: [Nouveau] [PATCH v2 0/9] drm/nouveau: Various fixes for GP10B

2019-11-18 Thread Thierry Reding
On Sat, Nov 02, 2019 at 06:56:28PM +0100, Thierry Reding wrote: > From: Thierry Reding > > Hi Ben, > > here's a revised subset of the patches I had sent out a couple of weeks > ago. I've reworked the BAR2 accesses in the way that you had suggested, > which at least

Re: [Nouveau] [PATCH 1/3] drm/nouveau/kms/nv50-: Call outp_atomic_check_view() before handling PBN

2019-11-18 Thread Thierry Reding
nv50/disp.c | 44 ++--- > 1 file changed, 24 insertions(+), 20 deletions(-) Looks reasonable: Reviewed-by: Thierry Reding > diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c > b/drivers/gpu/drm/nouveau/dispnv50/disp.c > index 549486f1d937..6327aaf37c08 10

Re: [Nouveau] [PATCH 2/3] drm/nouveau/kms/nv50-: Store the bpc we're using in nv50_head_atom

2019-11-18 Thread Thierry Reding
16 BPC (see the definitions for SOR_STATE_ASY_PIXELDEPTH_BPP_*). With the above anything higher than 10 BPC will be treated the same and likely lead to wrong results. So I think either a WARN for the "default" case or additional cases for the other values would be good to have. Like I said

Re: [Nouveau] [PATCH] RFC: drm/nouveau: Make BAR1 support optional

2019-11-08 Thread Thierry Reding
On Fri, Nov 08, 2019 at 05:02:07PM +0100, Thierry Reding wrote: > From: Thierry Reding > > The purpose of BAR1 is primarily to make memory accesses coherent. > However, some GPUs do not have BAR1 functionality. For example, the > GV11B found on the Xavier SoC is DMA coheren

[Nouveau] [PATCH v2 4/9] drm/nouveau: tegra: Do not try to disable PCI device

2019-11-02 Thread Thierry Reding
From: Thierry Reding When Nouveau is instantiated on top of a platform device, the dev->pdev field will be NULL and calling pci_disable_device() will crash. Move the PCI disabling code to the PCI specific driver removal code. Reviewed-by: Lyude Paul Signed-off-by: Thierry Reding --- driv

[Nouveau] [PATCH v2 5/9] drm/nouveau: tegra: Avoid pulsing reset twice

2019-11-02 Thread Thierry Reding
From: Thierry Reding When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power

[Nouveau] [PATCH v2 7/9] drm/nouveau: secboot: Read WPR configuration from GPU registers

2019-11-02 Thread Thierry Reding
From: Thierry Reding The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding --- .../drm/nouveau/nvkm/subdev

[Nouveau] [PATCH v2 8/9] drm/nouveau: gp10b: Add custom L2 cache implementation

2019-11-02 Thread Thierry Reding
From: Thierry Reding There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding --- Changes in v2: - remove IOMMU_API protection

[Nouveau] [PATCH v2 6/9] drm/nouveau: tegra: Set clock rate if not set

2019-11-02 Thread Thierry Reding
From: Thierry Reding If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu

[Nouveau] [PATCH v2 3/9] drm/nouveau: fault: Add support for GP10B

2019-11-02 Thread Thierry Reding
From: Thierry Reding There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault

[Nouveau] [PATCH v2 9/9] drm/nouveau: gp10b: Use correct copy engine

2019-11-02 Thread Thierry Reding
From: Thierry Reding gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine

[Nouveau] [PATCH v2 2/9] iommu: Add dummy dev_iommu_fwspec_get() helper

2019-11-02 Thread Thierry Reding
From: Thierry Reding This dummy implementation is useful to avoid a dependency on the IOMMU_API Kconfig symbol in drivers that can optionally use the IOMMU API. In order to fully use this, also move the struct iommu_fwspec definition out of the IOMMU_API protected region. Suggested-by: Ben

[Nouveau] [PATCH v2 0/9] drm/nouveau: Various fixes for GP10B

2019-11-02 Thread Thierry Reding
From: Thierry Reding Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet

[Nouveau] [PATCH v2 1/9] iommu: Document iommu_fwspec::flags field

2019-11-02 Thread Thierry Reding
From: Thierry Reding When this field was added in commit 5702ee24182f ("ACPI/IORT: Check ATS capability in root complex nodes"), the kerneldoc comment wasn't updated at the same time. Signed-off-by: Thierry Reding --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+)

Re: [Nouveau] [PATCH 3/6] drm/nouveau: Remove bogus gk20a aperture callback

2019-09-20 Thread Thierry Reding
On Tue, Sep 17, 2019 at 11:02:54AM +0200, Thierry Reding wrote: > On Tue, Sep 17, 2019 at 01:43:13PM +1000, Ben Skeggs wrote: > > On Tue, 17 Sep 2019 at 01:18, Thierry Reding > > wrote: > > > > > > From: Thierry Reding > > > > > > The gk

Re: [Nouveau] [PATCH 0/2] drm/nouveau: Two more fixes

2019-09-17 Thread Thierry Reding
On Tue, Sep 17, 2019 at 04:07:54PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 00:36, Thierry Reding wrote: > > > > From: Thierry Reding > > > > Hi Ben, > > > > I messed up the ordering of patches in my tree a bit, so these two fixes > > go

Re: [Nouveau] [PATCH 2/6] drm/nouveau: fault: Widen engine field

2019-09-17 Thread Thierry Reding
On Tue, Sep 17, 2019 at 01:48:20PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote: > > > > From: Thierry Reding > > > > The engine field in the FIFO fault information registers is actually 9 > > bits wide. > Looks like this

Re: [Nouveau] [PATCH 1/6] drm/nouveau: fault: Store aperture in fault information

2019-09-17 Thread Thierry Reding
On Tue, Sep 17, 2019 at 01:47:25PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote: > > > > From: Thierry Reding > > > > The fault information register contains data about the aperture that > > caused the failure. This can be use

Re: [Nouveau] [PATCH 3/6] drm/nouveau: Remove bogus gk20a aperture callback

2019-09-17 Thread Thierry Reding
On Tue, Sep 17, 2019 at 01:43:13PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 01:18, Thierry Reding wrote: > > > > From: Thierry Reding > > > > The gk20a (as well as all subsequent Tegra instantiations of the GPU) do > > in fact use the same aperture

Re: [Nouveau] [PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers

2019-09-17 Thread Thierry Reding
On Tue, Sep 17, 2019 at 01:49:57PM +1000, Ben Skeggs wrote: > On Tue, 17 Sep 2019 at 01:04, Thierry Reding wrote: > > > > From: Thierry Reding > > > > The GPUs found on Tegra SoCs have registers that can be used to read the > > WPR configuration. Use th

Re: [Nouveau] [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached

2019-09-17 Thread Thierry Reding
On Mon, Sep 16, 2019 at 05:15:25PM +0100, Robin Murphy wrote: > On 16/09/2019 16:57, Thierry Reding wrote: > > On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote: > > > Hi Thierry, > > > > > > On 16/09/2019 16:04, Thierry Reding

Re: [Nouveau] [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached

2019-09-16 Thread Thierry Reding
On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote: > Hi Thierry, > > On 16/09/2019 16:04, Thierry Reding wrote: > > From: Thierry Reding > > > > If the GPU is already attached to an IOMMU, don't detach it and setup an > > explicit IOMMU domain. Sinc

Re: [Nouveau] [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation

2019-09-16 Thread Thierry Reding
On Mon, Sep 16, 2019 at 05:49:46PM +0200, Thierry Reding wrote: > On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote: > > On 16/09/2019 16:04, Thierry Reding wrote: > > > From: Thierry Reding > > > > > > There are extra registers that need to be progra

Re: [Nouveau] [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation

2019-09-16 Thread Thierry Reding
On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote: > On 16/09/2019 16:04, Thierry Reding wrote: > > From: Thierry Reding > > > > There are extra registers that need to be programmed to make the level 2 > > cache work on GP10B, such as the stream ID register th

[Nouveau] [PATCH 0/6] drm/nouveau: Preparatory work for GV11B support

2019-09-16 Thread Thierry Reding
From: Thierry Reding Hi Ben, these are a couple of patches that are in preparation for adding GV11B support. The fundamental issue that these are trying to solve is that the GV11B is the first Tegra incarnation of the GPU where the aperture really matters. All prior generations would accept any

[Nouveau] [PATCH 6/6] drm/nouveau: Program aperture field where necessary

2019-09-16 Thread Thierry Reding
From: Thierry Reding Some registers and instance block entries need the aperture to be programmed correctly. This is important on recent Tegra GPUs where the GPU actually checks the value of this field and faults if an invalid aperture is programmed. For example GV11B no longer supports VRAM

[Nouveau] [PATCH 5/6] drm/nouveau: Remove unused nvkm_vmm_func->aper() implementations

2019-09-16 Thread Thierry Reding
From: Thierry Reding These implementations are now all unused. Remove them. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 2 -- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c | 14 -- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c

[Nouveau] [PATCH 4/6] drm/nouveau: Implement nvkm_memory_aperture()

2019-09-16 Thread Thierry Reding
From: Thierry Reding The aperture of a buffer is always specific to where its memory was allocated from. Furthermore, the encoding of the aperture is always the same, regardless of GPU generation. Implement the memory target to aperture conversion in one central place and make the aperture

[Nouveau] [PATCH 1/6] drm/nouveau: fault: Store aperture in fault information

2019-09-16 Thread Thierry Reding
From: Thierry Reding The fault information register contains data about the aperture that caused the failure. This can be useful in debugging aperture related programming bugs. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h | 1 + drivers/gpu/drm/nouveau

[Nouveau] [PATCH 3/6] drm/nouveau: Remove bogus gk20a aperture callback

2019-09-16 Thread Thierry Reding
From: Thierry Reding The gk20a (as well as all subsequent Tegra instantiations of the GPU) do in fact use the same apertures as regular GPUs. Prior to gv11b there are no checks in hardware for the aperture, so we get away with setting VRAM as the aperture for buffers that are actually in system

[Nouveau] [PATCH 2/6] drm/nouveau: fault: Widen engine field

2019-09-16 Thread Thierry Reding
From: Thierry Reding The engine field in the FIFO fault information registers is actually 9 bits wide. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev

[Nouveau] [PATCH 11/11] arm64: tegra: Enable SMMU for GPU on Tegra186

2019-09-16 Thread Thierry Reding
From: Thierry Reding The GPU has a connection to the ARM SMMU found on Tegra186, which can be used to support large pages. Make sure the GPU is attached to the SMMU to take advantage of its capabilities. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file

[Nouveau] [PATCH 10/11] arm64: tegra: Enable GPU on Jetson TX2

2019-09-16 Thread Thierry Reding
From: Alexandre Courbot Enable the GPU node for the Jetson TX2 board. Signed-off-by: Alexandre Courbot Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-

[Nouveau] [PATCH 07/11] drm/nouveau: gk20a: Implement custom MMU class

2019-09-16 Thread Thierry Reding
From: Thierry Reding The GPU integrated in NVIDIA Tegra SoCs is connected to system memory via two paths: one direct path to the memory controller and another path that goes through a system MMU first. It's not typically necessary to go through the system MMU because the GPU's MMU can already

[Nouveau] [PATCH 09/11] drm/nouveau: tegra: Fall back to 32-bit DMA mask without IOMMU

2019-09-16 Thread Thierry Reding
From: Thierry Reding The GPU can usually address more than 32-bit, even without being attached to an IOMMU. However, if the GPU is not attached to an IOMMU, it's likely that there is no IOMMU in the system, in which case any buffers allocated by Nouveau will likely end up in a region of memory

[Nouveau] [PATCH 05/11] drm/nouveau: gp10b: Use correct copy engine

2019-09-16 Thread Thierry Reding
From: Thierry Reding gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine

[Nouveau] [PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation

2019-09-16 Thread Thierry Reding
From: Thierry Reding There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding --- .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h

[Nouveau] [PATCH 08/11] drm/nouveau: tegra: Skip IOMMU initialization if already attached

2019-09-16 Thread Thierry Reding
From: Thierry Reding If the GPU is already attached to an IOMMU, don't detach it and setup an explicit IOMMU domain. Since Nouveau can now properly handle the case of the DMA API being backed by an IOMMU, just continue using the DMA API. Signed-off-by: Thierry Reding --- .../drm/nouveau/nvkm

[Nouveau] [PATCH 06/11] drm/nouveau: gk20a: Set IOMMU bit for DMA API if appropriate

2019-09-16 Thread Thierry Reding
From: Thierry Reding Detect if the DMA API is backed by an IOMMU and set the IOMMU bit if so. This is needed to make sure IOMMU addresses are properly translated even the explicit IOMMU API is not used. Signed-off-by: Thierry Reding --- .../drm/nouveau/nvkm/subdev/instmem/gk20a.c | 35

[Nouveau] [PATCH 02/11] drm/nouveau: tegra: Set clock rate if not set

2019-09-16 Thread Thierry Reding
From: Thierry Reding If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu

[Nouveau] [PATCH 01/11] drm/nouveau: tegra: Avoid pulsing reset twice

2019-09-16 Thread Thierry Reding
From: Thierry Reding When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power

[Nouveau] [PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers

2019-09-16 Thread Thierry Reding
From: Thierry Reding The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding --- .../drm/nouveau/nvkm/subdev

[Nouveau] [PATCH 2/2] drm/nouveau: tegra: Do not try to disable PCI device

2019-09-16 Thread Thierry Reding
From: Thierry Reding When Nouveau is instantiated on top of a platform device, the dev->pdev field will be NULL and calling pci_disable_device() will crash. Move the PCI disabling code to the PCI specific driver removal code. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouv

[Nouveau] [PATCH 1/2] drm/nouveau: tegra: Fix NULL pointer dereference

2019-09-16 Thread Thierry Reding
From: Thierry Reding Fill in BAR2 callbacks for instance memory. There's no BAR2 on Tegra GPUs, but buffers are all in system memory anyway, so just return the plain address. Signed-off-by: Thierry Reding --- .../drm/nouveau/nvkm/subdev/instmem/gk20a.c | 30 +++ 1 file

[Nouveau] [PATCH 0/2] drm/nouveau: Two more fixes

2019-09-16 Thread Thierry Reding
From: Thierry Reding Hi Ben, I messed up the ordering of patches in my tree a bit, so these two fixes got separated from the others. I don't consider these particularily urgent because the crash that the first one fixes only happens on gp10b which we don't enable by default yet and the second

[Nouveau] [PATCH 0/4] drm/nouveau: Miscellaneous fixes

2019-09-16 Thread Thierry Reding
From: Thierry Reding Hi Ben, these are fixes for a couple of issues that I've been running into when testing on various Tegra boards. The first two patches fix up issues in the fix that I had sent out earlier to fix the regression introduced in drm-misc-next. The first one is critical because

[Nouveau] [PATCH 2/4] drm/nouveau: prime: Extend DMA reservation object lock

2019-09-16 Thread Thierry Reding
From: Thierry Reding Prior to commit 019cbd4a4feb ("drm/nouveau: Initialize GEM object before TTM object"), the reservation object was locked across all of the buffer object creation. After splitting nouveau_bo_new() into separate nouveau_bo_alloc() and nouveau_bo_init()

[Nouveau] [PATCH 3/4] drm/nouveau: Fix ordering between TTM and GEM release

2019-09-16 Thread Thierry Reding
From: Thierry Reding When the last reference to a TTM BO is dropped, ttm_bo_release() will acquire the DMA reservation object's wound/wait mutex while trying to clean up (ttm_bo_cleanup_refs_or_queue() via ttm_bo_release()). It is therefore essential that drm_gem_object_release() be called after

[Nouveau] [PATCH 4/4] drm/nouveau: gm20b: Avoid BAR1 teardown during init

2019-09-16 Thread Thierry Reding
From: Thierry Reding Writing the 0x1704 (BUS_BAR1_BLOCK) register causes the GPU to probe the memory region at the programmed address. The result is an address decode error in the external memory controller because address 0, which is what is written to the register, is not designated

[Nouveau] [PATCH 1/4] drm/nouveau: Fix fallout from reservation object rework

2019-09-16 Thread Thierry Reding
From: Thierry Reding Commit 019cbd4a4feb ("drm/nouveau: Initialize GEM object before TTM object") introduced a subtle change in how the buffer allocation size is handled. Prior to that change, the size would get aligned to at least a page, whereas after that change a non-page-aligned

Re: [Nouveau] [Intel-gfx] [PATCH v6 08/17] drm/ttm: use gem vma_node

2019-09-10 Thread Thierry Reding
On Sat, Sep 07, 2019 at 09:58:46PM -0400, Ilia Mirkin wrote: > On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding > wrote: > > > > On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote: > > > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote: > > > > >

Re: [Nouveau] [Intel-gfx] [PATCH v6 08/17] drm/ttm: use gem vma_node

2019-08-21 Thread Thierry Reding
On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote: > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote: > > > > Hi, > > > > > > Changing the order doesn't look hard. Patch attached (untested, have no > > > > test hardware). But maybe I missed some detail ... > > > > > > I came up

Re: [Nouveau] [Intel-gfx] [PATCH v6 08/17] drm/ttm: use gem vma_node

2019-08-16 Thread Thierry Reding
On Mon, Aug 05, 2019 at 04:01:10PM +0200, Gerd Hoffmann wrote: > Drop vma_node from ttm_buffer_object, use the gem struct > (base.vma_node) instead. > > Signed-off-by: Gerd Hoffmann > Reviewed-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +- >

Re: [Nouveau] [Intel-gfx] [PATCH v6 08/17] drm/ttm: use gem vma_node

2019-08-14 Thread Thierry Reding
necessary the GEM object can be initialized in between. I think that's slightly more flexible and easier to understand than a boolean flag. Thierry From a1130a6affcb7c00133e89f3e498cb6757f5bb51 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 14 Aug 2019 11:00:48 +0200 Subject: [PATCH] drm/nouveau: Initialize GEM object

Re: [Nouveau] [PATCH 26/26] drm/: Don't set FBINFO_(FLAG_)DEFAULT

2019-01-26 Thread Thierry Reding
n Skeggs > Cc: Sandy Huang > Cc: "Heiko Stübner" > Cc: Thierry Reding > Cc: Jonathan Hunter > Cc: Hans de Goede > Cc: Greg Kroah-Hartman > Cc: Daniel Vetter > Cc: Bartlomiej Zolnierkiewicz > Cc: Alexander Kapshuk > Cc: linux-arm-ker...@

Re: [Nouveau] [PATCH 7/7] drm: Split out drm_probe_helper.h

2018-12-12 Thread Thierry Reding
ont.c | 2 +- > drivers/gpu/drm/xen/xen_drm_front_conn.c | 2 +- > drivers/gpu/drm/xen/xen_drm_front_gem.c | 2 +- > drivers/gpu/drm/xen/xen_drm_front_kms.c | 2 +- > drivers/gpu/drm/zte/zx_drm_drv.c |

Re: [Nouveau] next/master boot bisection: Oops in nouveau driver on jetson-tk1

2018-12-10 Thread Thierry Reding
On Mon, Dec 10, 2018 at 02:25:59PM +, Mark Brown wrote: > On Mon, Dec 10, 2018 at 10:00:08AM +, Guillaume Tucker wrote: > > On 08/12/2018 00:08, Lyude Paul wrote: > > > uh > > > didn't we fix this weeks ago? with "drm/nouveau: tegra: Call > > > nouveau_drm_device_init()" > > >

Re: [Nouveau] TK1: DRM, Nouveau and VIC

2018-12-10 Thread Thierry Reding
On Mon, Dec 10, 2018 at 03:20:19PM +, Marcel Ziswiler wrote: > Hi Thierry > > On Mon, 2018-12-10 at 12:00 +0100, Thierry Reding wrote: > > On Mon, Dec 10, 2018 at 11:21:47AM +0100, Thierry Reding wrote: > > > On Sat, Dec 08, 2018 at 02:54:45PM +, Marcel Ziswiler w

Re: [Nouveau] TK1: DRM, Nouveau and VIC

2018-12-10 Thread Thierry Reding
On Mon, Dec 10, 2018 at 11:21:47AM +0100, Thierry Reding wrote: > On Sat, Dec 08, 2018 at 02:54:45PM +, Marcel Ziswiler wrote: > > Hi Thierry et al. > > > > I noticed that since commit 3dde5a2342cd ("ARM: tegra: Add VIC on > > Tegra124") graphics on Apali

Re: [Nouveau] next/master boot: 142 boots: 2 failed, 130 passed with 7 offline, 3 conflicts (next-20181129)

2018-11-29 Thread Thierry Reding
On Thu, Nov 29, 2018 at 11:44:13AM +, Mark Brown wrote: > On Thu, Nov 29, 2018 at 03:23:59AM -0800, kernelci.org bot wrote: > > Today's -next crashes on Jetson TK1 when the Nouveau module is loaded if > it can't find firmware: > > [7.617291] nouveau 5700.gpu: Linked as a consumer to

Re: [Nouveau] [PATCH 1/4] drm/edid: Pass connector to AVI inforframe functions

2018-11-23 Thread Thierry Reding
n Park > Cc: Russell King > Cc: CK Hu > Cc: Philipp Zabel > Cc: Rob Clark > Cc: Ben Skeggs > Cc: Tomi Valkeinen > Cc: Sandy Huang > Cc: "Heiko Stübner" > Cc: Benjamin Gaignard > Cc: Vincent Abriou > Cc: Thierry Reding > Cc: Eric Anholt >

[Nouveau] [PATCH] drm/nouveau: tegra: Call nouveau_drm_device_init()

2018-11-23 Thread Thierry Reding
From: Thierry Reding As part of commit cfea88a4d866 ("drm/nouveau: Start using new drm_dev initialization helpers"), the initialization of the Nouveau DRM device was reworked and along the way the platform driver initialization was left incomplete. Add a call to nouveau_drm_device_init

Re: [Nouveau] [PATCH 2/2] drm/atomic: Create and use __drm_atomic_helper_crtc_reset() everywhere

2018-11-15 Thread Thierry Reding
gt; Cc: Rodrigo Vivi > Cc: Philipp Zabel > Cc: CK Hu > Cc: Matthias Brugger > Cc: Rob Clark > Cc: Ben Skeggs > Cc: Tomi Valkeinen > Cc: Laurent Pinchart > Cc: Kieran Bingham > Cc: Sandy Huang > Cc: "Heiko Stübner" > Cc: Thierry Reding > Cc: Jon

Re: [Nouveau] [PATCH] drm/nouveau: tegra: Initialize mode configuration

2018-11-07 Thread Thierry Reding
On Wed, Nov 07, 2018 at 10:52:11AM -0500, Ilia Mirkin wrote: > On Wed, Nov 7, 2018 at 10:34 AM Thierry Reding > wrote: > > > > On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote: > > > On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote: &

Re: [Nouveau] [PATCH] drm/nouveau: tegra: Initialize mode configuration

2018-11-07 Thread Thierry Reding
On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote: > On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote: > > From: Thierry Reding > > > > Irrespective of whether or not the device has any usable outputs, the > > modesetting helpers will try to

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