Hi
Am 28.10.20 um 20:55 schrieb Daniel Vetter:
> On Wed, Oct 28, 2020 at 8:02 PM Thomas Zimmermann wrote:
>>
>> Hi
>>
>> Am 28.10.20 um 17:06 schrieb Daniel Vetter:
>>> So ever since syzbot discovered fbcon, we have solid proof that it's
>>> full of bugs. And often the solution is to just delete
So ever since syzbot discovered fbcon, we have solid proof that it's
full of bugs. And often the solution is to just delete code and remove
features, e.g. 50145474f6ef ("fbcon: remove soft scrollback code").
Now the problem is that most modern-ish drivers really only treat
fbcon as an dumb
Am 29.10.20 um 11:14 schrieb Daniel Vetter:
> So ever since syzbot discovered fbcon, we have solid proof that it's
> full of bugs. And often the solution is to just delete code and remove
> features, e.g. 50145474f6ef ("fbcon: remove soft scrollback code").
>
> Now the problem is that most
On 28. 10. 20, 17:06, Daniel Vetter wrote:
So ever since syzbot discovered fbcon, we have solid proof that it's
full of bugs. And often the solution is to just delete code and remove
features, e.g. 50145474f6ef ("fbcon: remove soft scrollback code").
...
--- a/drivers/video/fbdev/core/fbcon.c
So ever since syzbot discovered fbcon, we have solid proof that it's
full of bugs. And often the solution is to just delete code and remove
features, e.g. 50145474f6ef ("fbcon: remove soft scrollback code").
Now the problem is that most modern-ish drivers really only treat
fbcon as an dumb
Turing requires some changes to FIFO interrupt handling due to changes
in HW register layout. It also requires some changes to implement robust
channel (RC) recovery. This preparatory patch moves the functions
requiring changes into nvkm/engine/fifo/tu102.c so they can be altered
without affecting
Turing reports MMU fault interrupts via new top level interrupt
registers. The old PMC MMU interrupt vector is not used by the HW. This
means we can remap the new top-level MMU interrupt to the exisiting PMC
MMU bit which simplifies the implementation until all interrupts are
moved over to using
Previous hardware allowed a MMU fault to be generated by software to
trigger a context switch for engine recovery. Turing has the capability
to preempt all work from a specific runlist processor and removed the
registers currently used for triggering MMU faults. Attempting to access
these
Some of the low level FIFO interrupt status bits have changed for
Turing. Update the handling of these to match the hardware.
Signed-off-by: Alistair Popple
---
.../gpu/drm/nouveau/nvkm/engine/fifo/tu102.c | 78 +++
1 file changed, 9 insertions(+), 69 deletions(-)
diff --git
This is an initial series of patches to improve channel recovery on Turing GPUs
with the goal of improving reliability enough to eventually enable SVM for
Turing. It's likely follow up patches will be required to fully address problems
with less trivial workloads than what I have been able to test
This is no longer needed now that tu102_mc_intr_stat has been updated to
look at the correct top-level interrupt bits.
Signed-off-by: Alistair Popple
---
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | 3 ---
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h | 1 -
11 matches
Mail list logo
