Re: [OE-core] [PATCH] riscv: Add configure cache entries for libidl

[Khem Raj]

On 9/21/21 12:05 PM, Khem Raj wrote:



On Tue, Sep 21, 2021 at 11:16 AM Ross Burton > wrote:


libidl was removed long ago, along with ORBit.  Can we just drop
these entirely?


Check layer index if it does not appear there then I am fine with 
dropping it entirely


I dont see this recipe on layer index so I think it should be safe to 
delete these cached vars. I will send a v2 to remove it from other site 
files too.






Ross

On Tue, 21 Sept 2021 at 18:02, Khem Raj mailto:raj.k...@gmail.com>> wrote:
 >
 > These were hidden in meta-networking
 >
 > Signed-off-by: Khem Raj mailto:raj.k...@gmail.com>>
 > ---
 >  meta/site/riscv32-linux | 3 +++
 >  meta/site/riscv64-linux | 3 +++
 >  2 files changed, 6 insertions(+)
 >
 > diff --git a/meta/site/riscv32-linux b/meta/site/riscv32-linux
 > index 97de628e22..acc32fd03c 100644
 > --- a/meta/site/riscv32-linux
 > +++ b/meta/site/riscv32-linux
 > @@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
 >
 >  # startup-notification
 >  lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
 > +
 > +# libidl
 > +libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
 > diff --git a/meta/site/riscv64-linux b/meta/site/riscv64-linux
 > index 38bc5f044d..cf78133ee0 100644
 > --- a/meta/site/riscv64-linux
 > +++ b/meta/site/riscv64-linux
 > @@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
 >
 >  # startup-notification
 >  lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
 > +
 > +# libidl
 > +libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
 > --
 > 2.33.0
 >
 >
 > 
 >



-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#156231): 
https://lists.openembedded.org/g/openembedded-core/message/156231
Mute This Topic: https://lists.openembedded.org/mt/85770609/21656
Group Owner: openembedded-core+ow...@lists.openembedded.org
Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub 
[arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [OE-core] [PATCH] riscv: Add configure cache entries for libidl

[Khem Raj]

On Tue, Sep 21, 2021 at 11:16 AM Ross Burton  wrote:

> libidl was removed long ago, along with ORBit.  Can we just drop these
> entirely?


Check layer index if it does not appear there then I am fine with dropping
it entirely

>
>
> Ross
>
> On Tue, 21 Sept 2021 at 18:02, Khem Raj  wrote:
> >
> > These were hidden in meta-networking
> >
> > Signed-off-by: Khem Raj 
> > ---
> >  meta/site/riscv32-linux | 3 +++
> >  meta/site/riscv64-linux | 3 +++
> >  2 files changed, 6 insertions(+)
> >
> > diff --git a/meta/site/riscv32-linux b/meta/site/riscv32-linux
> > index 97de628e22..acc32fd03c 100644
> > --- a/meta/site/riscv32-linux
> > +++ b/meta/site/riscv32-linux
> > @@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
> >
> >  # startup-notification
> >  lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
> > +
> > +# libidl
> > +libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
> > diff --git a/meta/site/riscv64-linux b/meta/site/riscv64-linux
> > index 38bc5f044d..cf78133ee0 100644
> > --- a/meta/site/riscv64-linux
> > +++ b/meta/site/riscv64-linux
> > @@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
> >
> >  # startup-notification
> >  lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
> > +
> > +# libidl
> > +libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
> > --
> > 2.33.0
> >
> >
> > 
> >
>

-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#156228): 
https://lists.openembedded.org/g/openembedded-core/message/156228
Mute This Topic: https://lists.openembedded.org/mt/85770609/21656
Group Owner: openembedded-core+ow...@lists.openembedded.org
Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub 
[arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [OE-core] [PATCH] riscv: Add configure cache entries for libidl

[Ross Burton]

libidl was removed long ago, along with ORBit.  Can we just drop these entirely?

Ross

On Tue, 21 Sept 2021 at 18:02, Khem Raj  wrote:
>
> These were hidden in meta-networking
>
> Signed-off-by: Khem Raj 
> ---
>  meta/site/riscv32-linux | 3 +++
>  meta/site/riscv64-linux | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/meta/site/riscv32-linux b/meta/site/riscv32-linux
> index 97de628e22..acc32fd03c 100644
> --- a/meta/site/riscv32-linux
> +++ b/meta/site/riscv32-linux
> @@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
>
>  # startup-notification
>  lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
> +
> +# libidl
> +libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
> diff --git a/meta/site/riscv64-linux b/meta/site/riscv64-linux
> index 38bc5f044d..cf78133ee0 100644
> --- a/meta/site/riscv64-linux
> +++ b/meta/site/riscv64-linux
> @@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
>
>  # startup-notification
>  lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
> +
> +# libidl
> +libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
> --
> 2.33.0
>
>
> 
>

-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#156226): 
https://lists.openembedded.org/g/openembedded-core/message/156226
Mute This Topic: https://lists.openembedded.org/mt/85770609/21656
Group Owner: openembedded-core+ow...@lists.openembedded.org
Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub 
[arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[OE-core] [PATCH] riscv: Add configure cache entries for libidl

[Khem Raj]

These were hidden in meta-networking

Signed-off-by: Khem Raj 
---
 meta/site/riscv32-linux | 3 +++
 meta/site/riscv64-linux | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/meta/site/riscv32-linux b/meta/site/riscv32-linux
index 97de628e22..acc32fd03c 100644
--- a/meta/site/riscv32-linux
+++ b/meta/site/riscv32-linux
@@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
 
 # startup-notification
 lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
+
+# libidl
+libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
diff --git a/meta/site/riscv64-linux b/meta/site/riscv64-linux
index 38bc5f044d..cf78133ee0 100644
--- a/meta/site/riscv64-linux
+++ b/meta/site/riscv64-linux
@@ -9,3 +9,6 @@ glib_cv_uscore=${glib_cv_uscore=no}
 
 # startup-notification
 lf_cv_sane_realloc=${lf_cv_sane_realloc=yes}
+
+# libidl
+libIDL_cv_long_long_format=${libIDL_cv_long_long_format=ll}
-- 
2.33.0


-=-=-=-=-=-=-=-=-=-=-=-
Links: You receive all messages sent to this group.
View/Reply Online (#156219): 
https://lists.openembedded.org/g/openembedded-core/message/156219
Mute This Topic: https://lists.openembedded.org/mt/85770609/21656
Group Owner: openembedded-core+ow...@lists.openembedded.org
Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub 
[arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-