Hi Michael,
the fragment of OpenOCD log shows that CPU0 (M7 core) cannot be halted.
What is programmed in M7 startup?
On 11/08/2023 22:34, Banducci, Michael wrote:
I started based on the example OpenOCD configs for the STM32H745 and
H747 and attempted to build a configuration file (see below)
Have you tried using the ST fork of OpenOCD?
https://github.com/sysprogs/openocd-st/
Is this of any use?
https://visualgdb.com/tutorials/arm/stm32/multicore/startup/
Hi all,
I'm attempting to get Zephyr working on the M4 core of an STM32H755. I'm using
an ST-Link v3set on Windows 11 with OpenOCD v. 0.12.0.
I am able to flash a compiled binary via OpenOCD, but I have so far been unable
to get to a place where I can debug the second core. I started based on t
> Do you have a link?
This perhaps?
https://community.st.com/t5/stm32-mcu-products/stm32f746-cortex-m7-silicon-bug-singlestep-lands-in-interrupt/m-p/357481
> On 11 Aug 2023, at 15:56, James Murray wrote:
>
> I believe that this has been discussed on ST's forum.
Do you have a link?
> Some core
> revisions have this bug and ST's response is that it will not be fixed.
> OpenOCD already prints an alert on connection for buggy cores.
>
> STM32F745
> > On 7 Aug 2023, at 10:45, Tomas Vanek
> > wrote:
> >
> > The problem with a debug break induced into an interrupt handler is
> > same as we observed
> > in other Cortex-M7 versions.
>
> ok, so probably all STM Cortex-M7 cores are affected.
>
> did you inform someone at STM/Arm?
>
> > Curre
