This is an automated email from Gerrit.
Antonio Borneo (borneo.anto...@gmail.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/230
-- gerrit
commit dad8906a0f3ae3ba81cc5f2d4c4582b960144dc0
Author: Antonio Borneo <borneo.anto...@gmail.com>
Date: Fri Nov 18 13:09:14 2011 +0800
TCL: Add board file for EVALSPEAr300
Initial support for SPEAr300 chip and for evaluation
board named EVALSPEAr300.
Currently supports only those parts in common with
SPEAr310.
Change-Id: I8075aa721cf3dfaac561ee51e5df4ce9a2992e3e
Signed-off-by: Antonio Borneo <borneo.anto...@gmail.com>
diff --git a/tcl/board/spear300evb.cfg b/tcl/board/spear300evb.cfg
new file mode 100644
index 0000000..9f95703
--- /dev/null
+++ b/tcl/board/spear300evb.cfg
@@ -0,0 +1,44 @@
+# Configuration for the ST SPEAr300 Evaluation board
+# EVALSPEAr300 Rev. 1.0
+# http://www.st.com/spear
+#
+# Date: 2010-11-27
+# Author: Antonio Borneo <borneo.anto...@gmail.com>
+
+# The standard board has JTAG SRST not connected.
+# This script targets such boards using quirky code to bypass the issue.
+
+
+source [find mem_helper.tcl]
+source [find target/spear3xx.cfg]
+source [find chip/st/spear/spear3xx_ddr.tcl]
+source [find chip/st/spear/spear3xx.tcl]
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+
+# Serial NOR on SMI CS0. 8Mbyte.
+set _FLASHNAME1 $_CHIPNAME.snor
+flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
+
+if { [info exists BOARD_HAS_SRST] } {
+ # Modified board has SRST on JTAG connector
+ reset_config trst_and_srst separate srst_gates_jtag \
+ trst_push_pull srst_open_drain
+} else {
+ # Standard board has no SRST on JTAG connector
+ reset_config trst_only separate srst_gates_jtag trst_push_pull
+ source [find chip/st/spear/quirk_no_srst.tcl]
+}
+
+$_TARGETNAME configure -event reset-init { spear300evb_init }
+
+proc spear300evb_init {} {
+ reg pc 0xffff0020; # loop forever
+
+ sp3xx_clock_default
+ sp3xx_common_init
+ sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
+ sp300_init
+}
diff --git a/tcl/board/spear300evb_mod.cfg b/tcl/board/spear300evb_mod.cfg
new file mode 100644
index 0000000..91cad5f
--- /dev/null
+++ b/tcl/board/spear300evb_mod.cfg
@@ -0,0 +1,26 @@
+# Configuration for the ST SPEAr300 Evaluation board
+# EVALSPEAr300 Rev. 1.0, modified to enable SRST on JTAG connector
+# http://www.st.com/spear
+#
+# List of board modifications to enable SRST, as reported in
+# ST Application Note (FIXME: add reference).
+# - Modifications on the top layer:
+# 1. replace reset chip U4 with a STM6315SDW13F;
+# - Modifications on the bottom layer:
+# 2. add 0 ohm resistor R10. It is located close to JTAG connector.
+# 3. add a 10K ohm pull-up resistor on the reset wire named as
+# POWERGOOD in the schematic.
+#
+# The easier way to do modification 3, is to use a resistor in package
+# 0603 and solder it between R10 and R54:
+# - one pad soldered with the pad of R54 connected to 3.3V (this
+# is the pad of R54 far from JTAG connector J4)
+# - the other pad soldered with the nearest pad of R10.
+#
+# Date: 2011-11-18
+# Author: Antonio Borneo <borneo.anto...@gmail.com>
+
+
+# Modified boards has SRST on JTAG connector
+set BOARD_HAS_SRST 1
+source [find board/spear300evb.cfg]
diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
index 17ab228..ce9e0ca 100644
--- a/tcl/chip/st/spear/spear3xx.tcl
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -80,7 +80,13 @@ proc sp3xx_common_init {} {
}
-# Specific init scripts for ST SPEAr310 system on chip
+# Specific init scripts for ST SPEAr300
+proc sp300_init {} {
+ mww 0x99000000 0x00003fff ;# RAS function enable
+}
+
+
+# Specific init scripts for ST SPEAr310
proc sp310_init {} {
mww 0xb4000008 0x00002ff4 ;# RAS function enable
--
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