This is an automated email from Gerrit.
"Name of user not set <chris.whee...@narfindustries.com>" just uploaded a new
patch set to Gerrit, which you can find at
https://review.openocd.org/c/openocd/+/8143
-- gerrit
commit 60f201d6f70cad0f7a0e0d01a130350a3e557dc5
Author: WheelNarf <chris.whee...@narfindustries.com>
Date: Mon Feb 12 13:10:50 2024 -0800
jtag/drivers/imx_gpio: add configurable gpio address space size to
accommodate other imx chips. Use macros to have consistency with
https://review.openocd.org/c/openocd/+/7732
Change-Id: I70b09c0e7877af39932f8fa366701b2386bdafc2
Signed-off-by: WheelNarf <chris.whee...@narfindustries.com>
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index 2fd0fad85e..5448579337 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -22,12 +22,25 @@
#define IMX_GPIO_REGS_DR (sizeof(uint32_t) * 0)
#define IMX_GPIO_REGS_GDIR (sizeof(uint32_t) * 1)
-#define IMX_GPIO_REGS_PSR (sizeof(uint32_t) * 1)
-#define IMX_GPIO_REGS_ICR1 (sizeof(uint32_t) * 1)
-#define IMX_GPIO_REGS_ICR2 (sizeof(uint32_t) * 1)
-#define IMX_GPIO_REGS_IMR (sizeof(uint32_t) * 1)
-#define IMX_GPIO_REGS_ISR (sizeof(uint32_t) * 1)
-#define IMX_GPIO_REGS_EDGE_SEL (sizeof(uint32_t) * 1)
+#define IMX_GPIO_REGS_PSR (sizeof(uint32_t) * 2)
+#define IMX_GPIO_REGS_ICR1 (sizeof(uint32_t) * 3)
+#define IMX_GPIO_REGS_ICR2 (sizeof(uint32_t) * 4)
+#define IMX_GPIO_REGS_IMR (sizeof(uint32_t) * 5)
+#define IMX_GPIO_REGS_ISR (sizeof(uint32_t) * 6)
+#define IMX_GPIO_REGS_EDGE_SEL (sizeof(uint32_t) * 7)
+
+/* GPIO setup macros */
+#define IMX_GPIO_REG_READ(g, offset) \
+ (*(pio_base + ((g / 32) * imx_gpio_peri_size + offset) /
sizeof(uint32_t)))
+
+#define IMX_GPIO_REG_WRITE(g, offset, value) \
+ (*(pio_base + ((g / 32) * imx_gpio_peri_size + offset) /
sizeof(uint32_t)) = (value))
+
+#define IMX_GPIO_SET_REG_BITS(g, offset, bit_mask) \
+ (*(pio_base + ((g / 32) * imx_gpio_peri_size + offset) /
sizeof(uint32_t)) |= (bit_mask))
+
+#define IMX_GPIO_CLEAR_REG_BITS(g, offset, bit_mask) \
+ (*(pio_base + ((g / 32) * imx_gpio_peri_size + offset) /
sizeof(uint32_t)) &= ~(bit_mask))
static uint32_t imx_gpio_peri_base = IMX_GPIO_BASE;
static uint32_t imx_gpio_peri_size = IMX_GPIO_SIZE;
@@ -35,22 +48,22 @@ static uint32_t imx_gpio_peri_size = IMX_GPIO_SIZE;
static int dev_mem_fd;
/* imx_gpio_peri_size is in bytes so using 1 byte pointer to be able to
address arbitrary sizes for different chips */
-static volatile uint8_t *pio_base;
+static volatile uint32_t *pio_base;
/* GPIO setup functions */
static inline bool gpio_mode_get(int g)
{
- return pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_GDIR] >>
(g & 0x1F) & 1;
+ return IMX_GPIO_REG_READ(g, IMX_GPIO_REGS_GDIR) >> (g & 0x1F) & 1;
}
static inline void gpio_mode_input_set(int g)
{
- pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_GDIR] &= ~(1u
<< (g & 0x1F));
+ IMX_GPIO_CLEAR_REG_BITS(g, IMX_GPIO_REGS_GDIR, 1u << (g & 0x1F));
}
static inline void gpio_mode_output_set(int g)
{
- pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_GDIR] |= (1u <<
(g & 0x1F));
+ IMX_GPIO_SET_REG_BITS(g, IMX_GPIO_REGS_GDIR, 1u << (g & 0x1F));
}
static inline void gpio_mode_set(int g, int m)
@@ -60,17 +73,17 @@ static inline void gpio_mode_set(int g, int m)
static inline void gpio_set(int g)
{
- pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_DR] |= (1u <<
(g & 0x1F));
+ IMX_GPIO_SET_REG_BITS(g, IMX_GPIO_REGS_DR, 1u << (g & 0x1F));
}
static inline void gpio_clear(int g)
{
- pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_DR] &= ~(1u <<
(g & 0x1F));
+ IMX_GPIO_CLEAR_REG_BITS(g, IMX_GPIO_REGS_DR, 1u << (g & 0x1F));
}
static inline bool gpio_level(int g)
{
- return pio_base[(g / 32) * imx_gpio_peri_size + IMX_GPIO_REGS_DR] >> (g
& 0x1F) & 1;
+ return IMX_GPIO_REG_READ(g, IMX_GPIO_REGS_DR) >> (g & 0x1F) & 1;
}
static bb_value_t imx_gpio_read(void);
--
