[OpenOCD-devel] Atmel ATSAME70 examination incomplete at startup

[Jay Maynard]

I'm trying to get an Atmel ATSAME70Q20A working with OpenOCD. I have an Olimex 
JTAG-TINY and ARM-JTAG-SWD connected, and the system works with our previous 
board running an AT91SAM7X. This is a new board design, so there may be a 
hardware issue. I've tried both the 0.10.0 distribution release and the tip of 
the git repository tree built today (from the Czech mirror, since Sourceforge 
seems not to have git access running yet).

The results vary some between runs. Sometimes, it doesn't power up the debug 
domain (see https://pastebin.com/NHXavQQL for an example). Other times, it gets 
the debug domain powered up, but can't find the AHB-AP (see 
https://pastebin.com/X4XeFdam ). Still others, it finds the AHB-AP, but then 
gets a fault trying to write to it (see https://pastebin.com/KQtpF537 ). The 
last case, at least, seems to have a problem: two bits are being written as 1 
to a register that the architecture defines as should be zero.

I've spent some time online on the IRC channel trying to get this running with 
the help of some folks there, but no luck. They suggested I ask you folks. Any 
ideas?



[cid:image001.png@01D3AA54.F60EDBA0]Jay Maynard | Software Engineer
Kahler Automation | 808 Timberlake Road, 
Fairmont, MN 56031 | Main: 507-235-6648
jmayn...@kahlerautomation.com

The information in this communication, including any attachments, is intended 
only for the person or entity to which it is addressed and may contain 
confidential, proprietary, and/or privileged material. Any review, 
retransmission, dissemination or other use of, or taking of any action in 
reliance upon, this information by persons or entities other than the intended 
recipient is prohibited. If you received this in error, please contact the 
sender and delete the material from all computers.

--
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot___
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel

Re: [OpenOCD-devel] Atmel ATSAME70 examination incomplete at startup

[jaymaynard]

The Olimex ARM-JTAG-SWD has a 27 ohm resistor in series with the SRST line.
I’m using about a 3-inch ribbon cable between it and the board; the SWD
adapter is plugged directly into the JTAG-TINY, as they recommend.


Jay Maynard, K5ZC
http://plus.google.com/+JayMaynard


2018-02-24 12:48:23 + Michael Schwingen  :

> On Sat, 24 Feb 2018 00:52:44 +0100
> Tomas Vanek via OpenOCD-devel 
> wrote:
>
> On 24.02.2018 0:04, Jay Maynard wrote:
> More important is a small series resistor (33 ohm) on SWD - ringing
> prevention. Again not necessary if the cable to adapter is short.
>
>
> However, "short" may mean "really short" - I had signal integrity
> trouble doing SWD on a STM32 using a busblaster (FT2232 - my old version
> of the PCB has no series resistors on board), with 15cm cable. Adding
> series resistors to SWD and SWCLK fixed that.
>
> cu
> Michael
>
> --
>
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! 
> http://sdm.link/slashdot
> ___
> OpenOCD-devel mailing list
> OpenOCD-devel@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/openocd-devel
>
--
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot___
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel

Re: [OpenOCD-devel] Atmel ATSAME70 examination incomplete at startup

[Michael Schwingen]

On Sat, 24 Feb 2018 00:52:44 +0100
Tomas Vanek via OpenOCD-devel 
wrote:

> On 24.02.2018 0:04, Jay Maynard wrote:
> More important is a small series resistor (33 ohm) on SWD - ringing 
> prevention. Again not necessary if the cable to adapter is short.

However, "short" may mean "really short" - I had signal integrity
trouble doing SWD on a STM32 using a busblaster (FT2232 - my old version
of the PCB has no series resistors on board), with 15cm cable. Adding
series resistors to SWD and SWCLK fixed that.

cu
Michael

--
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
___
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel

[OpenOCD-devel] [PATCH]: 0c3b050 target/arm_adi_v5: extend apcsw command to accept arbitrary bits

[gerrit]

This is an automated email from Gerrit.

Tomas Vanek (van...@fbl.cz) just uploaded a new patch set to Gerrit, which you 
can find at http://openocd.zylin.com/4431

-- gerrit

commit 0c3b050eb98f420a9c773d70218273aba00f2aa2
Author: Tomas Vanek 
Date:   Fri Feb 23 00:03:20 2018 +0100

target/arm_adi_v5: extend apcsw command to accept arbitrary bits

apcsw command was limited to SPROT bit only.

Now user can manipulate any bit except size and addrinc fields.
Can be used e.g. to set bus signal 'cacheable' on Cortex-M7

Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa
Signed-off-by: Tomas Vanek 

diff --git a/doc/openocd.texi b/doc/openocd.texi
index c128a4d..8262b72 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8232,9 +8232,11 @@ memory bus access [0-255], giving additional time to 
respond to reads.
 If @var{value} is defined, first assigns that.
 @end deffn
 
-@deffn Command {dap apcsw} [0 / 1]
-fix CSW_SPROT from register AP_REG_CSW on selected dap.
-Defaulting to 0.
+@deffn Command {dap apcsw} [value [mask]]
+Change CSW bits. CSW fields size and addrinc are dynamicaly set according
+to requirements of a tranfer, so these bits are not allowed to set.
+Other CSW bits like implementation dependent SPROT or HPROTx can be changed
+by this command. Refer to ARM ADI v5 manual for details.
 @end deffn
 
 @deffn Command {dap ti_be_32_quirks} [@option{enable}]
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index dfbc5ad..19565f2 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -96,8 +96,7 @@ static uint32_t max_tar_block_size(uint32_t 
tar_autoincr_block, uint32_t address
 
 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
 {
-   csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
-   ap->csw_default;
+   csw |= ap->csw_default;
 
if (csw != ap->csw_value) {
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
@@ -636,6 +635,8 @@ struct adiv5_dap *dap_init(void)
dap->ap[i].memaccess_tck = 255;
/* Number of bits for tar autoincrement, impl. dep. at least 10 
*/
dap->ap[i].tar_autoincr_block = (1<<10);
+   /* default CSW value */
+   dap->ap[i].csw_default = CSW_DBGSWENABLE | CSW_MASTER_DEBUG | 
CSW_HPROT;
}
INIT_LIST_HEAD(>cmd_journal);
return dap;
@@ -1602,22 +1603,30 @@ COMMAND_HANDLER(dap_apcsw_command)
struct arm *arm = target_to_arm(target);
struct adiv5_dap *dap = arm->dap;
 
-   uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
+   uint32_t apcsw = dap->ap[dap->apsel].csw_default;
+   uint32_t csw_val, csw_mask;
 
switch (CMD_ARGC) {
case 0:
command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" 
PRIx32,
(dap->apsel), apcsw);
-   break;
+   return ERROR_OK;
case 1:
-   COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
-   /* AP address is in bits 31:24 of DP_SELECT */
-   if (sprot > 1)
+   COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
+   if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
+   LOG_ERROR("CSW value cannot include size and addrinc 
fields");
return ERROR_COMMAND_SYNTAX_ERROR;
-   if (sprot)
-   apcsw |= CSW_SPROT;
-   else
-   apcsw &= ~CSW_SPROT;
+   }
+   apcsw = csw_val;
+   break;
+   case 2:
+   COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
+   COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
+   if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
+   LOG_ERROR("CSW mask cannot include size and addrinc 
fields");
+   return ERROR_COMMAND_SYNTAX_ERROR;
+   }
+   apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1750,8 +1759,8 @@ static const struct command_registration dap_commands[] = 
{
.name = "apcsw",
.handler = dap_apcsw_command,
.mode = COMMAND_EXEC,
-   .help = "Set csw access bit ",
-   .usage = "[sprot]",
+   .help = "Set CSW default bits",
+   .usage = "[value [mask]]",
},
 
{

-- 

--
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
___
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel

[OpenOCD-devel] [PATCH]: 163e515 gdb_server: fix vCont

[gerrit]

This is an automated email from Gerrit.

Tomas Vanek (van...@fbl.cz) just uploaded a new patch set to Gerrit, which you 
can find at http://openocd.zylin.com/4432

-- gerrit

commit 163e51538608b0ef9a027cf421e23dd2db61285e
Author: Tomas Vanek 
Date:   Fri Feb 23 19:27:28 2018 +0100

gdb_server: fix vCont

Change-Id: Ic79db7c2b798a35283ff752e9b12475486a1f31a
Signed-off-by: Tomas Vanek 

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index cbf1ca9..c341dca 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2598,8 +2598,8 @@ static bool gdb_handle_vcont_packet(struct connection 
*connection, const char *p
if (parse[0] == 'c') {
LOG_DEBUG("target %s continue", target_name(target));
log_add_callback(gdb_log_callback, connection);
-   retval = target_resume(target, 1, 0, 0, 0);
-   if (retval == ERROR_OK) {
+   target_resume(target, 1, 0, 0, 0);
+   if (target->state == TARGET_RUNNING) {
gdb_connection->frontend_state = TARGET_RUNNING;
target_call_event_callbacks(target, 
TARGET_EVENT_GDB_START);
}
@@ -2639,15 +2639,17 @@ static bool gdb_handle_vcont_packet(struct connection 
*connection, const char *p
}
 
LOG_DEBUG("target %s single-step thread %"PRId64, 
target_name(ct), thread_id);
+   log_add_callback(gdb_log_callback, connection);
+   target_call_event_callbacks(ct, TARGET_EVENT_GDB_START);
+
retval = target_step(ct, 1, 0, handle_breakpoint);
if (retval == ERROR_OK) {
gdb_signal_reply(target, connection);
/* stop forwarding log packets! */
log_remove_callback(gdb_log_callback, 
connection);
} else
-   if (retval == ERROR_TARGET_TIMEOUT) {
+   if (target->state == TARGET_RUNNING) {
gdb_connection->frontend_state = TARGET_RUNNING;
-   target_call_event_callbacks(ct, 
TARGET_EVENT_GDB_START);
}
} else {
LOG_ERROR("Unknown vCont packet");

-- 

--
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
___
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel