Looks like posting an URI only is regarded as a spam?! See OpenOCD gerrit,
patch #4282
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** [tickets:#164] samr30 patch**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Oct 27, 2017 10:21 AM UTC by Martin Deicke
**Last Updated:** Mon Oct 30, 2017 05:10 PM UTC
**Owner:** OpenOCD-Gerrit
The problem is much wider. Many event handlers work with the current target as
it were the target issuing the event. Unfortunately this assumption is not
valid in multi-target config.
See recent conversation topic 'current target in Tcl event' in devel mailing
list.
Try http://openocd.zylin.com/
Please test http://openocd.zylin.com/4295 with extended fix instead of 4293
---
** [tickets:#168] examine-end event handler unable to access memory with two
targets**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Nov 17, 2017 07:19 AM UTC by Christopher Head
**Last Updated:** Fri Nov 1
Can you try revert
http://openocd.zylin.com/gitweb?p=openocd.git;a=commitdiff;h=568e84236bf3b58f4eef73cbed70f3544b44df1f
or set STLINK_TRACE_SIZE to 1024 or 2048 ?
---
** [tickets:#174] stlink-v2-1 with firmware V2J30M19 timeouts in bulk transfer
reads of trace endpoint**
**Status:** new
**Mi
http://openocd.zylin.com/4282
---
** [tickets:#164] samr30 patch**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Oct 27, 2017 10:21 AM UTC by Martin Deicke
**Last Updated:** Wed Nov 01, 2017 09:14 AM UTC
**Owner:** OpenOCD-Gerrit
**Attachments:**
-
[r30.patch](https://sourceforge.net/
No, erase takes place just once.
However I spotted some inefficient operation during write in the at91sam4.c:
1) FMR register is set before every page write and it is read-modify-write
operation. It should be done just once per flash write.
2) EFC_StartCommand checks status before every EFC comm
See http://openocd.zylin.com/4611
---
** [tickets:#188] samg55 start of debug speedup**
**Status:** new
**Milestone:** 0.9.0
**Labels:** samg
**Created:** Tue Jun 05, 2018 09:20 AM UTC by Filip
**Last Updated:** Sat Jul 21, 2018 11:11 AM UTC
**Owner:** nobody
**Attachments:**
- [Screenshot at
You should set the QSPI memory range as read only by 'mem' command in gdb.
Alternatively you can use not yet merged QSPI driver
http://openocd.zylin.com/4321
---
** [tickets:#211] Enable break points on QSPI debugging + OpenOCD**
**Status:** new
**Milestone:** 0.9.0
**Created:** Thu Nov 29,
See https://sourceforge.net/p/openocd/tickets/211/
---
** [tickets:#212] OpenOCD External QSPI debugging and setting breakpoints**
**Status:** new
**Milestone:** 0.9.0
**Labels:** QSPI Flash
**Created:** Fri Nov 30, 2018 06:16 AM UTC by Nivedh
**Last Updated:** Fri Nov 30, 2018 06:16 AM UTC
**
Paul, can you please submit your patch to http://openocd.zylin.com/
See http://openocd.org/doc/doxygen/html/patchguide.html for detials.
Thanks
---
** [tickets:#196] ath79 flash driver requires CPU address, where core driver
passes offset**
**Status:** new
**Milestone:** 0.9.0
**Created:** Wed
You need to apply the patch http://openocd.zylin.com/4321 and recompile OpenOCD
from source. Feel free to create a gerrit account at http://openocd.zylin.com
and join discussion with developers. We cannot support not merged patches here
in the bug tracker.
---
** [tickets:#211] Enable break p
Fixed in http://openocd.zylin.com/#/c/4821/1
---
** [tickets:#196] ath79 flash driver requires CPU address, where core driver
passes offset**
**Status:** new
**Milestone:** 0.9.0
**Created:** Wed Jul 25, 2018 03:34 PM UTC by Paul Bartholomew
**Last Updated:** Mon Dec 03, 2018 12:10 PM UTC
**Ow
Please test http://openocd.zylin.com/4926 and give a feedback to author.
---
** [tickets:#227] Latest STM32F7 chip causes flash probe assertion**
**Status:** new
**Milestone:** 0.9.0
**Created:** Thu Feb 21, 2019 05:19 PM UTC by Robert Campbell
**Last Updated:** Thu Feb 21, 2019 05:20 PM UTC
**
The board config file is intended for ST Nucleo L073RZ board. The on-board MCU
has 20kB RAM, more than enough for the requested 8kB work area. If you use
similar, not the same MCU (and different board), do not use
st_nucleo_l073rz.cfg directly. Make your own config (you can get inspiration
fro
It might be an issue of the flash driver then. Please attach -d3 log of failed
programming. Thanks
---
** [tickets:#231] STM32L07x dual bank fails flashing**
**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 31, 2019 09:57 AM UTC by Martin Jäger
**Last Updated:** Thu Apr 04, 2019 09:05
The debug log shows that CPU waits for the end of half page write with stalled
AHB and the adapter polling suffers from long waits. It seems just question of
probability if and when the adapter exceeds MAX_WAIT_RETRIES (8).
The write algo in contrib/loaders/flash/stm32/stm32lx.S should check FLAS
1) You are using an modified OpenOCD source from
https://github.com/sysprogs/openocd
We do not know what eventual changes was made by sysprogs. Please run the
officialOpenOCD code if you want to report bugs - see
http://openocd.org/getting-openocd/
2) Be aware of https://sourceforge.net/p/openo
Thanks for the report.
SMC_PMSTAT is checked because flashing in VLPR mode is not possible.
When I implemented this check, I did not know about "Initial Product Rev" (Z
part).
RM reads that Z dev has a Mode Controller instead of SMC at 0x4007e000.
So to fix this problem correctly, we should intr
The first line of target config says:
`samdXX devices only support SWD transports.`
This is valid also for SAML, SAMR and SAMC series.
And your log says:
`Info : auto-selecting first available session transport "jtag". To override
use 'transport select '.`
You should add
`transport select swd`
SAM D51, E54, E53 and E51 familes were not supported by 0.10.0 release.
Use a newer OpenOCD build and target/atsame5x.cfg config.
---
** [tickets:#240] openocd fails using ATMEL ICE initialization debugging of
SAMD51**
**Status:** new
**Milestone:** 0.9.0
**Created:** Thu May 30, 2019 10:36 P
I believe the issue might be similar to
https://sourceforge.net/p/openocd/tickets/231/
Please see -d3 log if the adapter exceeds MAX_WAIT_RETRIES (8).
---
** [tickets:#242] STM32L0x too high SWD clock**
**Status:** new
**Milestone:** 0.9.0
**Labels:** STM32
**Created:** Thu Jul 04, 2019 04:30
Checking the FLASH_SR BSY bit in the flash loader does not help. AHB gets
stalled in flash write operation before the algo can check BSY.
Please test
http://openocd.zylin.com/5270
where the target algo is removed and memory block writes are used intead.
The speed is slightly slower. Unpredictable
This ticket is probably a duplicate of
https://sourceforge.net/p/openocd/tickets/231/
Please test
http://openocd.zylin.com/5270
---
** [tickets:#243] cann't flash into Nucleo-L053R8 board**
**Status:** new
**Milestone:** 0.9.0
**Created:** Sat Jul 06, 2019 04:36 PM UTC by Yutao
**Last Updated:*
This ticket is probably a duplicate of
https://sourceforge.net/p/openocd/tickets/231/
Please test
http://openocd.zylin.com/5270
---
** [tickets:#248] stm32l0.cfg fails when stm32l0_enable_HSI16 called**
**Status:** new
**Milestone:** 0.9.0
**Created:** Sat Aug 03, 2019 08:35 PM UTC by Ola Oni
Please test
http://openocd.zylin.com/5270
---
** [tickets:#242] STM32L0x too high SWD clock**
**Status:** new
**Milestone:** 0.9.0
**Labels:** STM32
**Created:** Thu Jul 04, 2019 04:30 PM UTC by Patrik Bachan
**Last Updated:** Fri Jul 05, 2019 11:46 AM UTC
**Owner:** nobody
Hi,
when calling
Please check if
http://openocd.zylin.com/5271
solves the problem.
---
** [tickets:#247] STM32L031K6 (NUCLEO-L031K6): flash mass erase fails**
**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Jul 28, 2019 01:51 PM UTC by Karolis M
**Last Updated:** Sun Jul 28, 2019 01:51 PM UTC
**Owner:** n
Please test http://openocd.zylin.com/5348
---
** [tickets:#260] write protection not supported - nrf52840 / laird ble654 / **
**Status:** new
**Milestone:** 0.9.0
**Created:** Wed Nov 27, 2019 06:37 AM UTC by Matthias Schuh
**Last Updated:** Wed Nov 27, 2019 06:37 AM UTC
**Owner:** nobody
Dea
Looks strange.
Please be aware that code base [https://github.com/sysprogs/openocd] is not
same as our "official" source, so it might be a problem of sysprog's changes.
Let's hope it's not the case.
I tested programming with our fresh git master code in almost identical setup:
FTDI based SWD r
My code uses Kinetis SDK. It is available for free, you just need to make
account @ nxp and request SDK from the generator at https://mcuxpresso.nxp.com
The SDK is far from perfect, but you can at least take some inspiration from
it...
BTW if the FCF block is missing from your binary at all then
> I will put together Github tutorial on this and include the "Bash Script" for
> creating a nice "OpenOCD Programmer" over the next week.
Please do not. The hackish way works for you but offseting slpitted parts of
bin file is error prone and pontentially dangerous for others. Better learn
mor
> Why they put this block as an obstacle to normal programming is beyond belief.
Sure, Freescale wins the competition for the most stupid flash protection.
>From the log I recalled what the flash driver does to protect FCF from bad
>data.
It looks like there is some difference between the OpenOC
Finally I understand what's causing the problem.
Sector erase does not set FSEC field to unsecure as mass erase does. So if user
issue sector erase followed device reset then the device gets locked (not
permanently but it's a trouble as well).
To prevent this the OpenOCD kinetis flash driver bui
Noel, thanks for warm words!
Please test http://openocd.zylin.com/5753
The change does not fix the problem itself but improves verbosity so that an
user should know what's wrong.
---
** [tickets:#270] Kinetis MK22FX512: Error writing FCF Block 0X400 - 0x40f**
**Status:** new
**Milestone:** 0.
BTW FOPT = 0xf9 might be set for a good reason. Check NMI pin in your board.
---
** [tickets:#270] Kinetis MK22FX512: Error writing FCF Block 0X400 - 0x40f**
**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Jun 14, 2020 06:14 AM UTC by Noel Diviney
**Last Updated:** Fri Jul 03, 2020 08:03
Indeed!
In the revision D Microchip added ATSAME51G18A and ATSAME51G19A, which were not
known in the time of writing the atsame5 driver.
Please test and review http://openocd.zylin.com/5984
---
** [tickets:#288] DID 61810006 (Microchip ATSAME51G18A) Not supported**
**Status:** new
**Milestone
I suspect the command -c "at91samd bootloader 0" does not work as expected and
flash stays locked.
You have first issue "init" to close up OpenOCD initialization, then prepare
the device for programming by "reset init". The script "program" calls both
"init" and "reset init", but it is too late
at91samd bootloader command help reads:
..."Changes are stored immediately but take affect after the MCU is reset"
So you need add one more "reset init" before "flash write_image..."
---
** [tickets:#299] OpenOCD SAMD21 programming from RPI Error Flash write
discontinued / NVM programming error
BTW: I'm sure your original commands resulted in error
Error: The 'at91samd bootloader' command must be used after 'init'
Next time please copy whole OpenOCD output!
---
** [tickets:#299] OpenOCD SAMD21 programming from RPI Error Flash write
discontinued / NVM programming error**
**Status:**
Both logs shows a parity error at SWD level.
The problem is most probably in the wiring (too long wires, crosstalks between
SWCLK and SWDIO, poor grounding, EMI etc...)
---
** [tickets:#299] OpenOCD SAMD21 programming from RPI Error Flash write
discontinued / NVM programming error**
**Sta
It's not an error, it's OpenOCD evolution.
'flash info' now shows PROTECTION BLOCKS (with numbers you may need for flash
protect command). If you want to see flash pages, just issue
flash info 0 sectors
http://openocd.org/doc/html/Flash-Commands.html#Flash-Commands
---
** [tickets:#3
RM 4.1.3 Write protection option bytes:
For STM32F03x, STM32F04x, STM32F05x and STM32F07x devices, WRP bits from 0 to
31 are protecting the Flash memory by sector of 4 kB.
For STM32F09x devices, WRP bits from 0 to 30 are protecting the first 124 kB by
sector of
4 kB and the bit 31 is protecting t
> while reading this, I remembered this fix
> http://openocd.zylin.com/#/c/5444/
Yeah, Tarek, this fix was the first I checked for a regression. But it wasn't
there, ppage_size=4 for F0x has been in the driver since F0x introduction in
2014.
I believe changing ppage_size to 2 for all (?) F0x de
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