This is an automated email from Gerrit.
Matthias Welwarsky (matth...@welwarsky.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/3760
-- gerrit
commit ba48f648e84085379d94dab45066bf9b0b6f6952
Author: Matthias Welwarsky <matthias.welwar...@sysgo.com>
Date: Fri Sep 16 15:31:29 2016 +0200
aarch64: use correct A64 instructions for cache handling
Replace A32 MCR with proper A64 MSR opcodes
Change-Id: I64a60b17a58a26b199d2d1b2d5d91098e0c8cbd0
Signed-off-by: Matthias Welwarsky <matthias.welwar...@sysgo.com>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 558de08..e56396f 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2235,7 +2235,7 @@ static int aarch64_write_phys_memory(struct target
*target,
* wrong addresses will be invalidated!
*
* For both ICache and DCache, walk all cache lines in the
- * address range. Cortex-A8 has fixed 64 byte line length.
+ * address range. Cortex-A has fixed 64 byte line length.
*
* REVISIT per ARMv7, these may trigger watchpoints ...
*/
@@ -2246,12 +2246,12 @@ static int aarch64_write_phys_memory(struct target
*target,
* with MVA to PoU
* MCR p15, 0, r0, c7, c5, 1
*/
- for (uint32_t cacheline = address;
- cacheline < address + size * count;
+ for (uint32_t cacheline = 0;
+ cacheline < size * count;
cacheline += 64) {
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
- cacheline);
+ ARMV8_MSR_GP(SYSTEM_ICIVAU, 0),
+ address + cacheline);
if (retval != ERROR_OK)
return retval;
}
@@ -2263,12 +2263,12 @@ static int aarch64_write_phys_memory(struct target
*target,
* with MVA to PoC
* MCR p15, 0, r0, c7, c6, 1
*/
- for (uint32_t cacheline = address;
- cacheline < address + size * count;
+ for (uint32_t cacheline = 0;
+ cacheline < size * count;
cacheline += 64) {
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
- cacheline);
+ ARMV8_MSR_GP(SYSTEM_DCCVAU, 0),
+ address + cacheline);
if (retval != ERROR_OK)
return retval;
}
diff --git a/src/target/armv8.c b/src/target/armv8.c
index fdebf5b..09e7ec3 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -34,7 +34,6 @@
#include <unistd.h>
#include "armv8_opcodes.h"
-#include "arm_opcodes.h"
#include "target.h"
#include "target_type.h"
@@ -471,7 +470,7 @@ static int _armv8_flush_all_data(struct target *target)
/* DCCISW */
/* LOG_INFO ("%d %d %x",c_way,c_index,value); */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
+ ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
value);
if (retval != ERROR_OK)
goto done;
--
------------------------------------------------------------------------------
_______________________________________________
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel
