This is an automated email from Gerrit.
Matthias Welwarsky (matth...@welwarsky.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/3756
-- gerrit
commit e63a5829dfc7964909da479828231ec5f077061f
Author: Matthias Welwarsky <matthias.welwar...@sysgo.com>
Date: Fri Sep 16 15:18:47 2016 +0200
aarch64: remove armv7-a virt-to-phys code
Page table layout in aarch64 is very different from armv7-a layout.
Remove the incorrect handling, to be replaced correct armv8 code in a
later patch
Change-Id: I64c728a72a24f9f4177726ccc07a02a8ca0d56ce
Signed-off-by: Matthias Welwarsky <matthias.welwar...@sysgo.com>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index fc93bb0..3881f7e 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2623,12 +2623,8 @@ static int aarch64_virt2phys(struct target *target,
target_addr_t virt,
if (retval != ERROR_OK)
goto done;
*phys = ret;
- } else {/* use this method if armv8->memory_ap not selected
- * mmu must be enable in order to get a correct translation */
- retval = aarch64_mmu_modify(target, 1);
- if (retval != ERROR_OK)
- goto done;
- retval = armv8_mmu_translate_va_pa(target, virt, phys, 1);
+ } else {
+ LOG_ERROR("AAR64 processor not support translate va to pa");
}
done:
return retval;
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 57e256b..fccb17c 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -389,104 +389,30 @@ done:
return retval;
}
+static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t
*val)
+{
+ LOG_ERROR("4K page Address translation need to add");
+ return ERROR_FAIL;
+}
+
/* method adapted to cortex A : reused arm v4 v5 method*/
int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
{
- uint32_t first_lvl_descriptor = 0x0;
- uint32_t second_lvl_descriptor = 0x0;
- int retval;
+ int retval = ERROR_FAIL;
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
- uint32_t ttb = 0; /* default ttb0 */
- if (armv8->armv8_mmu.ttbr1_used == -1)
- armv8_read_ttbcr(target);
- if ((armv8->armv8_mmu.ttbr1_used) &&
- (va > (0xffffffff & armv8->armv8_mmu.ttbr0_mask))) {
- /* select ttb 1 */
- ttb = 1;
- }
+
retval = dpm->prepare(dpm);
+ retval += armv8_read_ttbcr(target);
if (retval != ERROR_OK)
goto done;
-
- /* MRC p15,0,<Rt>,c2,c0,ttb */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
- &ttb);
- if (retval != ERROR_OK)
- return retval;
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
- 4, 1, (uint8_t *)&first_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
- &first_lvl_descriptor);
- /* reuse armv4_5 piece of code, specific armv8 changes may come later
*/
- LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
-
- if ((first_lvl_descriptor & 0x3) == 0) {
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
- }
-
-
- if ((first_lvl_descriptor & 0x3) == 2) {
- /* section descriptor */
- *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
- return ERROR_OK;
- }
-
- if ((first_lvl_descriptor & 0x3) == 1) {
- /* coarse page table */
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffffc00) | ((va &
0x000ff000) >> 10),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- } else if ((first_lvl_descriptor & 0x3) == 3) {
- /* fine page table */
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffff000) | ((va &
0x000ffc00) >> 8),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- }
-
- second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
- &second_lvl_descriptor);
-
- LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
-
- if ((second_lvl_descriptor & 0x3) == 0) {
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
- }
-
- if ((second_lvl_descriptor & 0x3) == 1) {
- /* large page descriptor */
- *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
- return ERROR_OK;
- }
-
- if ((second_lvl_descriptor & 0x3) == 2) {
- /* small page descriptor */
- *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
- return ERROR_OK;
- }
-
- if ((second_lvl_descriptor & 0x3) == 3) {
- *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
- return ERROR_OK;
- }
-
- /* should not happen */
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
+ if (armv8->page_size == 0)
+ return armv8_4K_translate(target, va, val);
done:
- return retval;
+ dpm->finish(dpm);
+ return ERROR_FAIL;
}
/* V8 method VA TO PA */
diff --git a/src/target/armv8.h b/src/target/armv8.h
index b9e3f12..884d39a 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -228,6 +228,18 @@ target_to_armv8(struct target *target)
#define CTI_GATE 0x140
#define CTI_UNLOCK 0xFB0
+#define PAGE_SIZE_4KB 0x1000
+#define PAGE_SIZE_4KB_LEVEL0_BITS 39
+#define PAGE_SIZE_4KB_LEVEL1_BITS 30
+#define PAGE_SIZE_4KB_LEVEL2_BITS 21
+#define PAGE_SIZE_4KB_LEVEL3_BITS 12
+
+#define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) <<
PAGE_SIZE_4KB_LEVEL0_BITS)
+#define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) <<
PAGE_SIZE_4KB_LEVEL1_BITS)
+#define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) <<
PAGE_SIZE_4KB_LEVEL2_BITS)
+#define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) <<
PAGE_SIZE_4KB_LEVEL3_BITS)
+
+#define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
int armv8_arch_state(struct target *target);
int armv8_identify_cache(struct target *target);
--
------------------------------------------------------------------------------
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