Moin,
Thanks for your warm welcome and comments.
On 19.07.2010 00:20, David Brownell wrote:
I think the best approach would be if you could
provide patches to openocd/master for
improvements for this architecture.
Yes, I think it's recognized that the current code
has weaknesses. Blame
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/arm720t.c | 16
src/target/arm920t.c |5 +++--
src/target/arm920t.h |2 +-
src/target/arm926ejs.c |6 --
src/target/armv4_5_mmu.c |5 -
src/target/armv4_5_mmu.h |2 +-
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/cortex_a8.c | 33 -
1 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 9a90180..76c3d37 100644
--- a/src/target/cortex_a8.c
+++
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/arm11.c |2 +-
src/target/arm720t.c | 22 ++-
src/target/arm7_9_common.c | 14 ++--
src/target/arm7_9_common.h |2 +-
src/target/arm920t.c | 48
SWD support is coming soon?
I'll prepare the patch for versaloon.
For some CortexM3(STM32, LPC1700), TMS of JTAG is multiplexed as SWDIO of
SWD.
There is a specific sequence used to enter into JTAG or SWD mode.
But on JTAG/SWD dongle side, TMS is output while SWDIO is bi-directional.
By my
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/arm_adi_v5.c | 20 +++-
src/target/cortex_m3.c | 44 +---
2 files changed, 48 insertions(+), 16 deletions(-)
diff --git a/src/target/arm_adi_v5.c
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/arm_adi_v5.c | 12 ---
src/target/cortex_m3.c | 91 --
2 files changed, 78 insertions(+), 25 deletions(-)
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/arm_adi_v5.c | 44 -
src/target/cortex_m3.c | 55 ++
2 files changed, 73 insertions(+), 26 deletions(-)
diff --git a/src/target/arm_adi_v5.c
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/arm_adi_v5.c | 43 ---
1 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 39d8bde..b26175b 100644
---
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/adi_v5_jtag.c |5 -
src/target/arm7_9_common.c | 27 +--
src/target/arm7tdmi.c | 17 +
src/target/arm920t.c | 14 +++---
src/target/arm926ejs.c | 16
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/adi_v5_jtag.c | 16
1 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 185bd54..8731a1a 100644
--- a/src/target/adi_v5_jtag.c
+++
From 8f5e84bf8dabfddc6b853c522fdc29be90c93746 Mon Sep 17 00:00:00 2001
From: Spencer Oliver ntfr...@users.sourceforge.net
Date: Fri, 16 Jul 2010 16:59:35 +0100
Subject: [PATCH 2/4] cfg: update rsc-w910 script
- Only enable the FMI (NAND) and DMA clocks.
- Select NAND interface on the MFSEL.
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From d249057adfeb3f652df86ad321577744910b6e21 Mon Sep 17 00:00:00 2001
From: Spencer Oliver ntfr...@users.sourceforge.net
Date: Fri, 16 Jul 2010 16:56:41 +0100
Subject: [PATCH 1/4] docs: missing parameter from nand check_bad_blocks
Signed-off-by: Spencer Oliver ntfr...@users.sourceforge.net
---
From 4611f87f0aeba42d21fc6c197e904a0c97731bf7 Mon Sep 17 00:00:00 2001
From: Spencer Oliver ntfr...@users.sourceforge.net
Date: Mon, 19 Jul 2010 12:22:18 +0100
Subject: [PATCH 4/4] flash: add nuc910 nand driver
This adds a nand driver support for the nuc910 target.
Note that ECC is not currently
found by inspection
Signed-off-by: Øyvind Harboe oyvind.har...@zylin.com
---
src/target/arm_dpm.c | 28 ++--
1 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 4fbe5e3..012316b 100644
---
* Rename 'pause' variable to 'enter_pause'
* Change its type from 'int' to 'bool' to reflect usage.
Signed-off-by: Zachary T Welch z...@superlucidity.net
---
src/jtag/drivers/bitq.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/jtag/drivers/bitq.c
[PATCH 1/4] armv4_5: add algorithms instruction breakpoint support
[PATCH 2/4] armv7m: exit_point optional for armv7m_run_algorithm
[PATCH 3/4] mips32: exit_point optional for mips32_run_algorithm
[PATCH 4/4] flash: remove algorithm exit_point address for supported targets
From: Spencer Oliver ntfr...@users.sourceforge.net
Update the arm_checksum_memory and arm_blank_check_memory
algorithms to use a breakpoint instruction on v5 arch.
Signed-off-by: Spencer Oliver ntfr...@users.sourceforge.net
---
src/target/armv4_5.c | 22 --
1 files
From: Spencer Oliver ntfr...@users.sourceforge.net
As the armv7m uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm4_5 codebase.
Signed-off-by: Spencer Oliver ntfr...@users.sourceforge.net
---
src/target/armv7m.c
From: Spencer Oliver ntfr...@users.sourceforge.net
As the mips32 uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm codebase.
Signed-off-by: Spencer Oliver ntfr...@users.sourceforge.net
---
src/target/mips32.c |
From: Spencer Oliver ntfr...@users.sourceforge.net
For the above targets the exit_point is
optional when used with run_algorithm, so remove it.
This makes updating the algorithm less error prone.
Signed-off-by: Spencer Oliver ntfr...@users.sourceforge.net
---
src/flash/nor/lpc2000.c |2
Considering the huge number of identical if (retval != ERROR_OK)
return retval; added in this and your other patches, maybe we should
reuse the CHECK_RETVAL macro from arm11.h as a general mechanism to
reduce the clutter? It may not be the best of practices to return from
a macro, but rules are
On Mon, Jul 19, 2010 at 9:56 PM, Andreas Fritiofson
andreas.fritiof...@gmail.com wrote:
Considering the huge number of identical if (retval != ERROR_OK)
return retval; added in this and your other patches, maybe we should
reuse the CHECK_RETVAL macro from arm11.h as a general mechanism to
On 2010-07-17 02:29, David Brownell wrote:
1. There are 3 pins required for SWD right? SWDIO, SWCLK and reset?
And power (2 pins) ...
a. SWCLK is TCK?
b. SWDIO is TMS?
SWDI and SWDO == SWDIO: bidirectional.
TMS is unidirectional.
I was asking whether SWDIO is always multiplexed with
On 2010-07-19 12:40, simon qian wrote:
SWD support is coming soon?
I hope so (; Probably we all do.
4\/3!!
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Quick update on $SUBJECT: it's come up OK for me
recently, possibly resetting or halting the
stellaris target was a key step.
I could see the TPIU, ITM, and DWT instead of
spurious NVICs. And on LPC1768, the ETM also.
Puzzling, but now less worrisome...
- Dave
SWD support is coming soon?
Plans unchanged; yes. Next patch will be
transport glue for SWD ... then it'll be time to
update drivers to support it, and tweak things
to fill in the holes.
I'll prepare the patch for versaloon.
Good, that'll help.
- Dave
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