Move most declarations in <target/armv4_5.h> to <target/arm.h>
and update users.
What's left in the older file is stuff that I think should be
removed ... the old register cache access stuff, which makes it
awkward to support microcontroller profile (Cortex-M) cores.
The armv4_5_run_algorithm() declaration was moved too, even
though it's not yet as generic as it probably ought to be.
---
src/flash/nand/arm_io.c | 2
src/flash/nand/orion.c | 2
src/flash/nor/aduc702x.c | 2
src/flash/nor/cfi.c | 2
src/flash/nor/lpc2900.c | 2
src/flash/nor/str7x.c | 2
src/target/Makefile.am | 1
src/target/arm.h | 206 +++++++++++++++++++++++++++++++++++++++++
src/target/arm11.h | 2
src/target/arm7_9_common.c | 1
src/target/arm7_9_common.h | 2
src/target/arm_dpm.c | 2
src/target/arm_semihosting.c | 1
src/target/arm_simulator.c | 1
src/target/armv4_5.c | 1
src/target/armv4_5.h | 171 ----------------------------------
src/target/armv7a.h | 18 ---
src/target/armv7m.h | 2
src/target/etb.c | 2
src/target/etm.c | 2
src/target/etm_dummy.c | 2
src/target/oocd_trace.c | 2
src/target/xscale.c | 1
src/target/xscale.h | 2
24 files changed, 231 insertions(+), 200 deletions(-)
--- a/src/flash/nand/arm_io.c
+++ b/src/flash/nand/arm_io.c
@@ -27,7 +27,7 @@
#include "core.h"
#include "arm_io.h"
#include <helper/binarybuffer.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <target/algorithm.h>
--- a/src/flash/nand/orion.c
+++ b/src/flash/nand/orion.c
@@ -28,7 +28,7 @@
#include "imp.h"
#include "arm_io.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
struct orion_nand_controller
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -27,7 +27,7 @@
#include <helper/binarybuffer.h>
#include <helper/time_support.h>
#include <target/algorithm.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
static int aduc702x_build_sector_list(struct flash_bank *bank);
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -26,7 +26,7 @@
#include "imp.h"
#include "cfi.h"
#include "non_cfi.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -26,7 +26,7 @@
#include "imp.h"
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <target/image.h>
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -26,7 +26,7 @@
#include "imp.h"
#include "str7x.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -97,6 +97,7 @@ MIPS32_SRC = \
noinst_HEADERS = \
algorithm.h \
+ arm.h \
arm_dpm.h \
arm_jtag.h \
arm_adi_v5.h \
--- /dev/null
+++ b/src/target/arm.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2005 by Dominic Rath
+ * dominic.r...@gmx.de
+ *
+ * Copyright (C) 2008 by Spencer Oliver
+ * s...@spen-soft.co.uk
+ *
+ * Copyright (C) 2009 by Øyvind Harboe
+ * oyvind.har...@zylin.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#ifndef ARM_H
+#define ARM_H
+
+#include <target/target.h>
+#include <helper/command.h>
+
+
+/**
+ * @file
+ * Holds the interface to ARM cores.
+ *
+ * At this writing, only "classic ARM" cores built on the ARMv4 register
+ * and mode model are supported. The Thumb2-only microcontroller profile
+ * support has not yet been integrated, affecting Cortex-M parts.
+ */
+
+/**
+ * These numbers match the five low bits of the *PSR registers on
+ * "classic ARM" processors, which build on the ARMv4 processor
+ * modes and register set.
+ */
+enum arm_mode {
+ ARM_MODE_USR = 16,
+ ARM_MODE_FIQ = 17,
+ ARM_MODE_IRQ = 18,
+ ARM_MODE_SVC = 19,
+ ARM_MODE_ABT = 23,
+ ARM_MODE_MON = 26,
+ ARM_MODE_UND = 27,
+ ARM_MODE_SYS = 31,
+ ARM_MODE_ANY = -1
+};
+
+const char *arm_mode_name(unsigned psr_mode);
+bool is_arm_mode(unsigned psr_mode);
+
+/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
+enum arm_state {
+ ARM_STATE_ARM,
+ ARM_STATE_THUMB,
+ ARM_STATE_JAZELLE,
+ ARM_STATE_THUMB_EE,
+};
+
+extern const char *arm_state_strings[];
+
+#define ARM_COMMON_MAGIC 0x0A450A45
+
+/**
+ * Represents a generic ARM core, with standard application registers.
+ *
+ * There are sixteen application registers (including PC, SP, LR) and a PSR.
+ * Cortex-M series cores do not support as many core states or shadowed
+ * registers as traditional ARM cores, and only support Thumb2 instructions.
+ */
+struct arm {
+ int common_magic;
+ struct reg_cache *core_cache;
+
+ /** Handle to the CPSR; valid in all core modes. */
+ struct reg *cpsr;
+
+ /** Handle to the SPSR; valid only in core modes with an SPSR. */
+ struct reg *spsr;
+
+ /** Support for arm_reg_current() */
+ const int *map;
+
+ /**
+ * Indicates what registers are in the ARM state core register set.
+ * ARM_MODE_ANY indicates the standard set of 37 registers,
+ * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
+ * more registers are shadowed, for "Secure Monitor" mode.
+ */
+ enum arm_mode core_type;
+
+ /** Record the current core mode: SVC, USR, or some other mode. */
+ enum arm_mode core_mode;
+
+ /** Record the current core state: ARM, Thumb, or otherwise. */
+ enum arm_state core_state;
+
+ /** Flag reporting unavailability of the BKPT instruction. */
+ bool is_armv4;
+
+ /** Flag reporting whether semihosting is active. */
+ bool is_semihosting;
+
+ /** Value to be returned by semihosting SYS_ERRNO request. */
+ int semihosting_errno;
+
+ /** Backpointer to the target. */
+ struct target *target;
+
+ /** Handle for the debug module, if one is present. */
+ struct arm_dpm *dpm;
+
+ /** Handle for the Embedded Trace Module, if one is present. */
+ struct etm_context *etm;
+
+ /* FIXME all these methods should take "struct arm *" not target */
+
+ /** Retrieve all core registers, for display. */
+ int (*full_context)(struct target *target);
+
+ /** Retrieve a single core register. */
+ int (*read_core_reg)(struct target *target, struct reg *reg,
+ int num, enum arm_mode mode);
+ int (*write_core_reg)(struct target *target, struct reg *reg,
+ int num, enum arm_mode mode, uint32_t value);
+
+ /** Read coprocessor register. */
+ int (*mrc)(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t *value);
+
+ /** Write coprocessor register. */
+ int (*mcr)(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t value);
+
+ void *arch_info;
+};
+
+/** Convert target handle to generic ARM target state handle. */
+static inline struct arm *target_to_arm(struct target *target)
+{
+ return target->arch_info;
+}
+
+static inline bool is_arm(struct arm *arm)
+{
+ return arm && arm->common_magic == ARM_COMMON_MAGIC;
+}
+
+struct arm_algorithm {
+ int common_magic;
+
+ enum arm_mode core_mode;
+ enum arm_state core_state;
+};
+
+struct arm_reg {
+ int num;
+ enum arm_mode mode;
+ struct target *target;
+ struct arm *armv4_5_common;
+ uint32_t value;
+};
+
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
+
+extern const struct command_registration arm_command_handlers[];
+
+int arm_arch_state(struct target *target);
+int arm_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size);
+
+int arm_init_arch_info(struct target *target, struct arm *arm);
+
+/* REVISIT rename this once it's usable by ARMv7-M */
+int armv4_5_run_algorithm(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info);
+
+int arm_checksum_memory(struct target *target,
+ uint32_t address, uint32_t count, uint32_t *checksum);
+int arm_blank_check_memory(struct target *target,
+ uint32_t address, uint32_t count, uint32_t *blank);
+
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+
+extern struct reg arm_gdb_dummy_fp_reg;
+extern struct reg arm_gdb_dummy_fps_reg;
+
+#endif /* ARM_H */
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -23,7 +23,7 @@
#ifndef ARM11_H
#define ARM11_H
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <target/arm_dpm.h>
#define ARM11_TAP_DEFAULT TAP_INVALID
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -39,6 +39,7 @@
#include "arm_semihosting.h"
#include "algorithm.h"
#include "register.h"
+#include "armv4_5.h"
/**
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -29,7 +29,7 @@
#ifndef ARM7_9_COMMON_H
#define ARM7_9_COMMON_H
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <target/arm_jtag.h>
#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -21,7 +21,7 @@
#include "config.h"
#endif
-#include "armv4_5.h" /* REVISIT to become arm.h */
+#include "arm.h"
#include "arm_dpm.h"
#include <jtag/jtag.h>
#include "register.h"
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -34,6 +34,7 @@
#include "config.h"
#endif
+#include "arm.h"
#include "armv4_5.h"
#include "register.h"
#include "arm_semihosting.h"
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -24,6 +24,7 @@
#include "config.h"
#endif
+#include "arm.h"
#include "armv4_5.h"
#include "arm_disassembler.h"
#include "arm_simulator.h"
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,6 +27,7 @@
#include "config.h"
#endif
+#include "arm.h"
#include "armv4_5.h"
#include "arm_jtag.h"
#include "breakpoints.h"
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -26,39 +26,10 @@
#ifndef ARMV4_5_H
#define ARMV4_5_H
-#include <target/target.h>
-#include <helper/command.h>
-
-
-/**
- * These numbers match the five low bits of the *PSR registers on
- * "classic ARM" processors, which build on the ARMv4 processor
- * modes and register set.
+/* This stuff "knows" that its callers aren't talking
+ * to microcontroller profile (current Cortex-M) parts.
+ * We want to phase it out so core code can be shared.
*/
-enum arm_mode {
- ARM_MODE_USR = 16,
- ARM_MODE_FIQ = 17,
- ARM_MODE_IRQ = 18,
- ARM_MODE_SVC = 19,
- ARM_MODE_ABT = 23,
- ARM_MODE_MON = 26,
- ARM_MODE_UND = 27,
- ARM_MODE_SYS = 31,
- ARM_MODE_ANY = -1
-};
-
-const char *arm_mode_name(unsigned psr_mode);
-bool is_arm_mode(unsigned psr_mode);
-
-/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
-enum arm_state {
- ARM_STATE_ARM,
- ARM_STATE_THUMB,
- ARM_STATE_JAZELLE,
- ARM_STATE_THUMB_EE,
-};
-
-extern const char *arm_state_strings[];
/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
* index into the armv4_5_core_reg_map array. Its remaining users are
@@ -76,140 +47,4 @@ extern const int armv4_5_core_reg_map[8]
/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
enum { ARMV4_5_CPSR = 31, };
-#define ARM_COMMON_MAGIC 0x0A450A45
-
-/**
- * Represents a generic ARM core, with standard application registers.
- *
- * There are sixteen application registers (including PC, SP, LR) and a PSR.
- * Cortex-M series cores do not support as many core states or shadowed
- * registers as traditional ARM cores, and only support Thumb2 instructions.
- */
-struct arm
-{
- int common_magic;
- struct reg_cache *core_cache;
-
- /** Handle to the CPSR; valid in all core modes. */
- struct reg *cpsr;
-
- /** Handle to the SPSR; valid only in core modes with an SPSR. */
- struct reg *spsr;
-
- /** Support for arm_reg_current() */
- const int *map;
-
- /**
- * Indicates what registers are in the ARM state core register set.
- * ARM_MODE_ANY indicates the standard set of 37 registers,
- * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
- * more registers are shadowed, for "Secure Monitor" mode.
- */
- enum arm_mode core_type;
-
- /** Record the current core mode: SVC, USR, or some other mode. */
- enum arm_mode core_mode;
-
- /** Record the current core state: ARM, Thumb, or otherwise. */
- enum arm_state core_state;
-
- /** Flag reporting unavailability of the BKPT instruction. */
- bool is_armv4;
-
- /** Flag reporting whether semihosting is active. */
- bool is_semihosting;
-
- /** Value to be returned by semihosting SYS_ERRNO request. */
- int semihosting_errno;
-
- /** Backpointer to the target. */
- struct target *target;
-
- /** Handle for the debug module, if one is present. */
- struct arm_dpm *dpm;
-
- /** Handle for the Embedded Trace Module, if one is present. */
- struct etm_context *etm;
-
- /* FIXME all these methods should take "struct arm *" not target */
-
- /** Retrieve all core registers, for display. */
- int (*full_context)(struct target *target);
-
- /** Retrieve a single core register. */
- int (*read_core_reg)(struct target *target, struct reg *reg,
- int num, enum arm_mode mode);
- int (*write_core_reg)(struct target *target, struct reg *reg,
- int num, enum arm_mode mode, uint32_t value);
-
- /** Read coprocessor register. */
- int (*mrc)(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
- uint32_t *value);
-
- /** Write coprocessor register. */
- int (*mcr)(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
- uint32_t value);
-
- void *arch_info;
-};
-
-/** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target *target)
-{
- return target->arch_info;
-}
-
-static inline bool is_arm(struct arm *arm)
-{
- return arm && arm->common_magic == ARM_COMMON_MAGIC;
-}
-
-struct arm_algorithm
-{
- int common_magic;
-
- enum arm_mode core_mode;
- enum arm_state core_state;
-};
-
-struct arm_reg
-{
- int num;
- enum arm_mode mode;
- struct target *target;
- struct arm *armv4_5_common;
- uint32_t value;
-};
-
-struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
-
-int arm_arch_state(struct target *target);
-int arm_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size);
-
-extern const struct command_registration arm_command_handlers[];
-
-int arm_init_arch_info(struct target *target, struct arm *arm);
-
-int armv4_5_run_algorithm(struct target *target,
- int num_mem_params, struct mem_param *mem_params,
- int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
- int timeout_ms, void *arch_info);
-
-int arm_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum);
-int arm_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank);
-
-void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
-struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
-
-extern struct reg arm_gdb_dummy_fp_reg;
-extern struct reg arm_gdb_dummy_fps_reg;
-
#endif /* ARMV4_5_H */
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -20,7 +20,7 @@
#define ARMV7A_H
#include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <target/armv4_5_mmu.h>
#include <target/armv4_5_cache.h>
#include <target/arm_dpm.h>
@@ -114,22 +114,6 @@ target_to_armv7a(struct target *target)
/* See ARMv7a arch spec section C10.8 */
#define CPUDBG_AUTHSTATUS 0xFB8
-struct armv7a_algorithm
-{
- int common_magic;
-
- enum arm_mode core_mode;
- enum arm_state core_state;
-};
-
-struct armv7a_core_reg
-{
- int num;
- enum arm_mode mode;
- struct target *target;
- struct armv7a_common *armv7a_common;
-};
-
int armv7a_arch_state(struct target *target);
struct reg_cache *armv7a_build_reg_cache(struct target *target,
struct armv7a_common *armv7a_common);
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -27,7 +27,7 @@
#define ARMV7M_COMMON_H
#include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
/* define for enabling armv7 gdb workarounds */
#if 1
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -21,7 +21,7 @@
#include "config.h"
#endif
-#include "armv4_5.h"
+#include "arm.h"
#include "etm.h"
#include "etb.h"
#include "register.h"
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -21,7 +21,7 @@
#include "config.h"
#endif
-#include "armv4_5.h"
+#include "arm.h"
#include "etm.h"
#include "etb.h"
#include "image.h"
--- a/src/target/etm_dummy.c
+++ b/src/target/etm_dummy.c
@@ -21,7 +21,7 @@
#include "config.h"
#endif
-#include "armv4_5.h"
+#include "arm.h"
#include "etm_dummy.h"
--- a/src/target/oocd_trace.c
+++ b/src/target/oocd_trace.c
@@ -21,7 +21,7 @@
#include "config.h"
#endif
-#include "armv4_5.h"
+#include "arm.h"
#include "oocd_trace.h"
/*
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -37,6 +37,7 @@
#include "register.h"
#include "image.h"
#include "arm_opcodes.h"
+#include "armv4_5.h"
/*
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -23,7 +23,7 @@
#ifndef XSCALE_H
#define XSCALE_H
-#include <target/armv4_5.h>
+#include <target/arm.h>
#include <target/armv4_5_mmu.h>
#include <target/trace.h>
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