Hi,
I am trying to use a USB JTAG dongle (NGX ARM JTAG) compatible with oocdlink
for flash programming a LPC1768 processor.
I can successfully program the LPC1768 with this setup. But, being a noob
with open-ocd, I am a little confused with my current setup.
I am using openocd-0.4.0.
upon executing reset init, the output is as follows:
> reset init
JTAG tap: lpc1768.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part:
0xba00, ve
r: 0x4)
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x1fff0080 msp: 0x10001ffc
I think on a reset init, the pc should be ideally pointed to 0x00000000. But
here it is pointing to boot rom. (probably to the instruction where it waits
for the flash boot loader to sample the set bootloader mode pin low). My
rudimentary understanding is that on boot, the PC should be 0x00000000 after
which a jump is programmed to the bootloader location.
I have attached my configuration file below. Hopefully someone can shed some
light on this for me.
lpc1768.cfg
#***************************************
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
clocked with 4MHz internal RC oscillator
jtag_rclk 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1768
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
#set _ENDIAN little
set _CCLK 4000
}
interface ft2232
ft2232_device_desc "NGX JTAG A"
ft2232_layout oocdlink
ft2232_vid_pid 0x0403 0x6010
#delays on reset lines
jtag_nsrst_delay 20
jtag_ntrst_delay 20
# LPC2000 & LPC1700 -> SRST causes TRST
#reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst separate
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
$_TARGETNAME
# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip
SRAM)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
-work-area-backup 0
# REVISIT is there any good reason to have this reset-init event handler??
# Normally they should set up (board-specific) clocking then probe the
flash...
$_TARGETNAME configure -event reset-init {
# Force NVIC.VTOR to point to flash at 0 ...
# WHY? This is it's reset value; we run right after reset!!
mwb 0xE000ED08 0x00
#mwb 0x400FC10C 0x00
#mwb 0x400FC040 0x01
#flash probe 0
}
# LPC1768 has 512kB of user-available FLASH (bootloader is located in
separate dedicated region).
# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk>
[calc_checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 $_CCLK
calc_checksum
# 4MHz / 6 = 666kHz, so use 500
#jtag_khz 50
#init
#soft_reset_halt
#reset init
#flash write_image erase main_1768.hex 0 ihex
#resume 0
#exit
-amit
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